IEEE 802.3by 2016
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IEEE Standard for Ethernet — Amendment 2: Media Access Control Parameters, Physical Layers, and Management Parameters for 25 Gb/s Operation Amendment 2: Media Access Control Parameters,
Physical Layers, and Management Parameters for 25 Gb/s Operation
| Published By | Publication Date | Number of Pages |
| IEEE | 2016 | 244 |
Amendment Standard – Superseded. This amendment to IEEE Std 802.3-2015 adds Physical Layer (PHY) specifications and management parameters for 25 Gb/s operation over twinaxial copper cabling (25GBASE-CR and 25GBASE-CR-S), electrical backplanes (25GBASE-KR and 25GBASE-KR-S), and multimode fiber (25GBASE-SR). This amendment also specifies a 25 Gigabit Attachment Unit Interface (25GAUI) and optional Energy Efficient Ethernet (EEE).
PDF Catalog
| PDF Pages | PDF Title |
|---|---|
| 1 | IEEE Std 802.3by-2016 Front cover |
| 2 | Title page |
| 4 | Important Notices and Disclaimers Concerning IEEE Standards Documents |
| 7 | Participants |
| 11 | Introduction |
| 14 | Contents |
| 28 | IMPORTANT NOTICE |
| 29 | 1. Introduction 1.1 Overview 1.1.3 Architectural perspectives 1.1.3.2 Compatibility interfaces 1.3 Normative references 1.4 Definitions |
| 30 | 1.5 Abbreviations |
| 31 | 4. Media Access Control 4.4 Specific implementations 4.4.2 MAC parameters |
| 32 | 30. Management 30.3 Layer management for DTEs 30.3.2 PHY device managed object class 30.3.2.1 PHY device attributes 30.3.2.1.2 aPhyType 30.3.2.1.3 aPhyTypeList 30.3.2.1.5 aSymbolErrorDuringCarrier 30.5 Layer management for medium attachment units (MAUs) 30.5.1 MAU managed object class 30.5.1.1 MAU attributes 30.5.1.1.2 aMAUType |
| 33 | 30.5.1.1.4 aMediaAvailable 30.5.1.1.15 aFECAbility |
| 34 | 30.5.1.1.16 aFECMode 30.5.1.1.17 aFECCorrectedBlocks |
| 35 | 30.5.1.1.18 aFECUncorrectableBlocks 30.6 Management for link Auto-Negotiation 30.6.1 Auto-Negotiation managed object class 30.6.1.1 Auto-Negotiation attributes 30.6.1.1.5 aAutoNegLocalTechnologyAbility |
| 36 | 45. Management Data Input/Output (MDIO) Interface 45.2 MDIO Interface Registers 45.2.1 PMA/PMD registers |
| 37 | 45.2.1.1 PMA/PMD control 1 register (Register 1.0) 45.2.1.1.3 Speed selection (1.0.13, 1.0.6, 1.0.5:2) 45.2.1.2 PMA/PMD status 1 register (Register 1.1) 45.2.1.2.3 Fault (1.1.7) |
| 38 | 45.2.1.4 PMA/PMD speed ability (Register 1.4) 45.2.1.4.a 25G capable (1.4.11) 45.2.1.6 PMA/PMD control 2 register (Register 1.7) |
| 39 | 45.2.1.7 PMA/PMD status 2 register (Register 1.8) 45.2.1.7.4 Transmit fault (1.8.11) 45.2.1.7.5 Receive fault (1.8.10) 45.2.1.8 PMD transmit disable register (Register 1.9) |
| 40 | 45.2.1.10 PMA/PMD extended ability register (Register 1.11) 45.2.1.10.aa 25G extended abilities (1.11.12) 45.2.1.14 EEE capability (Register 1.16) 45.2.1.14.4a 25GBASE-R deep sleep (1.16.2) 45.2.3.4.5 25G capable (3.4.4) |
| 41 | 45.2.1.14b 25G PMA/PMD extended ability register (Register 1.19) 45.2.1.14b.1 25GBASE-SR ability (1.19.4) 45.2.1.14b.2 25GBASE-CR ability (1.19.3) 45.2.1.14b.3 25GBASE-CR-S ability (1.19.2) 45.2.1.14b.4 25GBASE-KR ability (1.19.1) |
| 42 | 45.2.1.14b.5 25GBASE-KR-S ability (1.19.0) 45.2.1.80 BASE-R PMD control register (Register 1.150) 45.2.1.81 BASE-R PMD status register (Register 1.151) 45.2.1.82 BASE-R LP coefficient update, lane 0 register (Register 1.152) 45.2.1.83 BASE-R LP status report, lane 0 register (Register 1.153) 45.2.1.84 BASE-R LD coefficient update, lane 0 register (Register 1.154) 45.2.1.85 BASE-R LD status report, lane 0 register (Register 1.155) |
| 43 | 45.2.1.94 Single-lane PHY 10GBASE-R FEC corrected blocks counter (Register 1.172, 1.173) 45.2.1.95 Single-lane PHY 10GBASE-R FEC uncorrected blocks counter (Register 1.174, 1.175) 45.2.1.96 CAUI-4 chip-to-moduleC2M and 25GAUI C2M recommended CTLE register (Register 1.179) 45.2.1.96.1 Recommended CTLE peaking (1.179.4:1) 45.2.1.97 25GAUI C2C and lane 0 CAUI-4 chip-to-chipC2C transmitter equalization, receive direction, lane 0 register (Register 1.180) |
| 44 | 45.2.1.97.1 Request flag (1.180.15) 45.2.1.97.2 Post-cursor request (1.180.14:12) 45.2.1.97.3 Pre-cursor request (1.180.11:10) 45.2.1.97.4 Post-cursor remote setting (1.180.9:7) 45.2.1.97.5 Pre-cursor remote setting (1.180.6:5) 45.2.1.97.6 Post-cursor local setting (1.180.4:2) 45.2.1.97.7 Pre-cursor local setting (1.180.1:0) |
| 45 | 45.2.1.99 25GAUI C2C and lane 0 CAUI-4 chip-to-chipC2C transmitter equalization, transmit direction, lane 0 register (Register 1.184) 45.2.1.99.1 Request flag (1.184.15) 45.2.1.99.2 Post-cursor request (1.184.14:12) 45.2.1.99.3 Pre-cursor request (1.184.11:10) 45.2.1.99.4 Post-cursor remote setting (1.184.9:7) 45.2.1.99.5 Pre-cursor remote setting (1.184.6:5) |
| 46 | 45.2.1.99.6 Post-cursor local setting (1.184.4:2) 45.2.1.99.7 Pre-cursor local setting (1.184.1:0) 45.2.1.101 RS-FEC control register (Register 1.200) 45.2.1.101.a 25G RS-FEC enable (1.200.2) 45.2.1.101.1 FEC bypass indication enable (1.200.1) 45.2.1.101.2 FEC bypass correction enable (1.200.0) |
| 47 | 45.2.1.102 RS-FEC status register (Register 1.201) 45.2.1.102.1 PCS align status (1.201.15) 45.2.1.102.2 RS-FEC align status (1.201.14) 45.2.1.102.7 RS-FEC high SER (1.201.2) 45.2.1.102.8 FEC bypass indication ability (1.201.1) 45.2.1.102.9 FEC bypass correction ability (1.201.0) |
| 48 | 45.2.1.103 RS-FEC corrected codewords counter (Register 1.202, 1.203) 45.2.1.104 RS-FEC uncorrected codewords counter (Register 1.204, 1.205) 45.2.1.106 RS-FEC symbol error counter lane 0 (Register 1.210, 1.211) 45.2.3 PCS registers 45.2.3.1 PCS control 1 register (Register 3.0) |
| 49 | 45.2.3.2 PCS status 1 register (Register 3.1) 45.2.3.2.7 PCS receive link status (3.1.2) 45.2.3.4 PCS speed ability (Register 3.4) 45.2.3.6 PCS control 2 register (Register 3.7) |
| 50 | 45.2.3.6.1 PCS type selection (3.7.2:0) 45.2.3.7 PCS status 2 register (Register 3.8) 45.2.3.7.3a 25GBASE-R capable (3.8.7) 45.2.3.9 EEE control and capability (Register 3.20) |
| 51 | 45.2.3.9.2a 25GBASE-R deep sleep (3.20.11) 45.2.3.9.2b 25GBASE-R fast wake (3.20.10) 45.2.3.13 BASE-R and 10GBASE-T PCS status 1 register (Register 3.32) 45.2.3.13.1 BASE-R and 10GBASE-T receive link status (3.32.12) 45.2.3.13.4 BASE-R and 10GBASE-T PCS high BER (3.32.1) 45.2.3.13.5 BASE-R and 10GBASE-T PCS block lock (3.32.0) 45.2.3.14 BASE-R and 10GBASE-T PCS status 2 register (Register 3.33) 45.2.3.14.1 Latched block lock (3.33.15) |
| 52 | 45.2.3.14.2 Latched high BER (3.33.14) 45.2.3.14.3 BER (3.33.13:8) 45.2.3.14.4 Errored blocks (3.33.7:0) 45.2.3.15 10/25GBASE-R PCS test pattern seed A (Registers 3.34 through 3.37) 45.2.3.16 10/25GBASE-R PCS test pattern seed B (Registers 3.38 through 3.41) 45.2.3.17 BASE-R PCS test-pattern control register (Register 3.42) |
| 53 | 45.2.7 Auto-Negotiation registers 45.2.7.12 Backplane Ethernet, BASE-R copper status (Register 7.48) |
| 54 | 45.2.7.12.1a RS-FEC negotiated (7.48.7) 45.2.7.12.2 Negotiated Port Type (7.48.1, 7.48.2, 7.48.3, 7.48.5, 7.48.6, 7.48.8, 7.48.9, 7.48.10, 7.48.11, 7.48.12, 7.48.13) 45.2.7.13 EEE advertisement (Register 7.60) 45.2.7.13.a 25GBASE-R EEE supported (7.60.14) |
| 55 | 45.2.7.14 EEE link partner ability (Register 7.61) |
| 56 | 45.5 Protocol implementation conformance statement (PICS) proforma for Clause 45, Management Data Input/Output (MDIO) interface 45.5.3 PICS proforma tables for the Management Data Input Output (MDIO) interface 45.5.3.3 PMA/PMD management functions |
| 57 | 69. Introduction to Ethernet operation over electrical backplanes 69.1 Overview 69.1.1 Scope 69.1.2 Relationship of Backplane Ethernet to the ISO OSI reference model |
| 59 | 69.2 Summary of Backplane Ethernet Sublayers 69.2.1 Reconciliation sublayer and media independent interfaces 69.2.3 Physical Layer signaling systems |
| 60 | 69.3 Delay constraints 69.5 Protocol implementation conformance statement (PICS) proforma |
| 61 | 73. Auto-Negotiation for backplane and copper cable assembly 73.2 Relationship to the ISO/IEC Open Systems Interconnection (OSI) reference model 73.3 Functional specifications |
| 62 | 73.6 Link codeword encoding 73.6.4 Technology Ability Field |
| 63 | 73.6.5 FEC capability 73.6.5.1 FEC resolution for 25G PHYs 73.6.5.2 FEC resolution for 10 Gb/s per lane PHYs |
| 64 | 73.6.5.3 FEC control variables 73.7 Receive function requirements 73.7.1 DME page reception 73.7.6 Priority Resolution function |
| 65 | 73.6 Management register requirements 73.10 State diagrams and variable definitions 73.10.1 State diagram variables |
| 67 | 74. Forward Error Correction (FEC) sublayer for BASE-R PHYs 74.1 Overview |
| 68 | 74.3 Relationship to other sublayers 74.4 Inter-sublayer interfaces |
| 69 | 74.4.1a Functional block diagram for 25GBASE-R PHYs |
| 70 | 74.5 FEC service interface 74.5.1a 25GBASE-R service primitives |
| 71 | 74.6 Delay constraints 74.7 FEC principle of operation 74.7.4 Functions within FEC sublayer 74.7.4.1 Reverse gearbox function 74.7.4.1.2 Reverse gearbox function for 25GBASE-R, 40GBASE-R, and 100GBASE-R |
| 72 | 74.7.4.3 FEC transmission bit ordering |
| 73 | 74.7.4.4 FEC (2112,2080) encoder 74.7.4.5 FEC decoder |
| 74 | 74.7.4.5.1 FEC (2112,2080) decoding |
| 75 | 74.7.4.6 FEC receive bit ordering |
| 76 | 74.7.4.8 FEC rapid block synchronization for EEE (optional) |
| 77 | 74.8 FEC MDIO function mapping 74.8.1 FEC capability 74.9 BASE-R PHY test-pattern mode |
| 78 | 74.11 Protocol implementation conformance statement (PICS) proforma for Clause 74, Forward Error Correction (FEC) sublayer for BASE-R PHYs 74.11.3 Major capabilities/options 74.11.5 FEC Requirements |
| 79 | 78. Energy-Efficient Ethernet (EEE) 78.1 Overview 78.1.1 LPI Signaling 78.1.3 Reconciliation sublayer operation 78.1.3.3 PHY LPI operation 78.1.3.3.1 PHY LPI transmit operation |
| 80 | 78.1.4 PHY types optionally supporting EEE 78.2 LPI mode timing parameters description 78.5 Communication link access latency |
| 81 | 78.5.2 25 Gb/s, 40 Gb/s, and 100 Gb/s PHY extension using 25GAUI, XLAUI, or CAUI-n |
| 82 | 90. Ethernet support for time synchronization protocols 90.1 Introduction |
| 83 | 105. Introduction to 25 Gb/s networks 105.1 Overview 105.1.1 Scope 105.1.2 Relationship of 25 Gigabit Ethernet to the ISO OSI reference model 105.1.3 Nomenclature |
| 85 | 105.2 Physical Layer signaling systems 105.3 Summary of 25 Gigabit Ethernet sublayers 105.3.1 Reconciliation Sublayer (RS) and 25 Gigabit Media Independent Interface (25GMII) |
| 86 | 105.3.2 Physical Coding Sublayer (PCS) 105.3.3 Forward Error Correction (FEC) sublayer 105.3.4 Physical Medium Attachment (PMA) sublayer 105.3.5 Physical Medium Dependent (PMD) sublayer 105.3.6 Auto-Negotiation (AN) 105.3.7 Management interface (MDIO/MDC) 105.3.8 Management |
| 87 | 105.4 Service interface specification method and notation 105.4.1 Inter-sublayer service interface 105.4.2 Instances of the Inter-sublayer service interface |
| 88 | 105.4.3 Semantics of inter-sublayer service interface primitives 105.4.3.1 IS_UNITDATA.request 105.4.3.1.1 Semantics of the service primitive 105.4.3.1.2 When generated 105.4.3.1.3 Effect of receipt 105.4.3.2 IS_UNITDATA.indication 105.4.3.2.1 Semantics of the service primitive |
| 89 | 105.4.3.2.2 When generated 105.4.3.2.3 Effect of receipt |
| 90 | 105.4.3.3 IS_SIGNAL.indication 105.4.3.3.1 Semantics of the service primitive |
| 91 | 105.4.3.3.2 When generated 105.4.3.3.3 Effect of receipt 105.4.3.4 IS_TX_MODE.request 105.4.3.4.1 Semantics of the service primitive 105.4.3.4.2 When generated 105.4.3.4.3 Effect of receipt 105.4.3.5 IS_RX_MODE.request 105.4.3.5.1 Semantics of the service primitive 105.4.3.5.2 When generated |
| 92 | 105.4.3.5.3 Effect of receipt 105.4.3.6 IS_RX_LPI_ACTIVE.request 105.4.3.6.1 Semantics of the service primitive 105.4.3.6.2 When generated 105.4.3.6.3 Effect of receipt 105.4.3.7 IS_ENERGY_DETECT.indication 105.4.3.7.1 Semantics of the service primitive 105.4.3.7.2 When generated 105.4.3.7.3 Effect of receipt |
| 93 | 105.4.3.8 IS_RX_TX_MODE.indication 105.4.3.8.1 Semantics of the service primitive 105.4.3.8.2 When generated 105.4.3.8.3 Effect of receipt 105.5 Delay constraints 105.6 State diagrams |
| 94 | 105.7 Protocol implementation conformance statement (PICS) proforma |
| 95 | 106. Reconciliation Sublayer (RS) and Media Independent Interface (25GMII) for 25 Gb/s operation 106.1 Overview |
| 96 | 106.1.1 Summary of major concepts 106.1.2 Application 106.1.3 Rate of operation 106.1.4 Delay constraints |
| 97 | 106.1.5 Allocation of functions 106.1.6 25GMII structure 106.1.7 Mapping of 25GMII signals to PLS service primitives 106.1.7.1 Mapping of PLS_DATA.request 106.1.7.2 Mapping of PLS_DATA.indication 106.1.7.3 Mapping of PLS_CARRIER.indication 106.1.7.4 Mapping of PLS_SIGNAL.indication |
| 98 | 106.1.7.5 Mapping of PLS_DATA_VALID.indication 106.2 25GMII data stream 106.3 25GMII functional specifications 106.4 LPI Assertion and Detection |
| 99 | 106.5 Protocol implementation conformance statement (PICS) proforma for Clause 106 Reconciliation Sublayer (RS) and Media Independent Interface (25GMII) for 25 Gb/s operation 106.5.1 Introduction 106.5.2 Identification 106.5.2.1 Implementation identification 106.5.2.2 Protocol summary |
| 100 | 106.5.2.3 Major capabilities/options 106.5.3 PICS proforma Tables for Reconciliation Sublayer and 25 Gigabit Media Independent Interface 106.5.3.1 General 106.5.3.2 Mapping of PLS service primitives 106.5.3.3 25GMII signal functional specifications. |
| 101 | 107. Physical Coding Sublayer (PCS) for 64B/66B, type 25GBASE-R 107.1 Overview 107.1.1 Scope 107.1.2 Relationship of 25GBASE-R to other standards 107.1.3 Summary of 25GBASE-R sublayers 107.1.3.1 Physical Coding Sublayer (PCS) 107.1.4 Inter-sublayer interfaces |
| 102 | 107.1.4.1 PCS service interface (25GMII) 107.1.4.2 Physical Medium Attachment (PMA) service interface 107.2 Functions within the PCS |
| 103 | 107.2.1 Notation conventions 107.2.2 Transmission order |
| 104 | 107.2.3 Test-pattern generator 107.3 LPI |
| 105 | 107.3 Delay constraints 107.4 Support for Auto-Negotiation |
| 106 | 107.5 Protocol implementation conformance statement (PICS) proforma for Clause 107, Physical Coding Sublayer (PCS) for 64B/66B, type 25GBASE-R 107.5.1 Introduction 107.5.2 Identification 107.5.2.1 Implementation identification 107.5.2.2 Protocol summary |
| 107 | 107.5.3 Major capabilities/options 107.5.4 25G PCS 107.5.4.1 Clause 49 functionality 107.5.4.2 Test-pattern generator 107.5.4.3 LPI |
| 108 | 107.5.4.4 Delay Constraints |
| 109 | 108. Reed-Solomon Forward Error Correction (RS-FEC) sublayer for 25GBASE-R PHYs 108.1 Overview 108.1.1 Scope 108.1.2 Position of RS-FEC in the 25GBASE-R PHY sublayers 108.2 FEC service interface |
| 110 | 108.3 PMA compatibility |
| 111 | 108.4 Delay constraints 108.5 Functions within the 25GBASE-R RS-FEC sublayer 108.5.1 Functional block diagram 108.5.2 Transmit function 108.5.2.1 Block synchronization 108.5.2.2 Rate compensation for codeword markers in the transmit direction 108.5.2.3 64B/66B to 256B/257B transcoder |
| 113 | 108.5.2.4 Codeword marker insertion 108.5.2.5 Reed-Solomon encoder 108.5.2.6 Codeword serialization 108.5.2.7 RS-FEC encoding for rapid codeword lock (EEE deep sleep) |
| 115 | 108.5.3 Receive function 108.5.3.1 Codeword marker lock 108.5.3.2 Reed-Solomon decoder |
| 116 | 108.5.3.3 Codeword monitor |
| 117 | 108.5.3.4 Codeword marker removal 108.5.3.5 256B/257B to 64B/66B transcoder 108.5.3.6 Rate compensation for codeword markers in the receive direction 108.5.3.7 Rapid codeword lock for EEE deep sleep |
| 118 | 108.5.3.8 Receive bit ordering 108.5.4 Detailed functions and state diagrams 108.5.4.1 State diagram conventions 108.5.4.2 State variables |
| 120 | 108.5.4.3 Functions 108.5.4.4 Counters |
| 121 | 108.5.4.5 Timers |
| 122 | 108.5.4.6 State diagrams |
| 123 | 108.6 25GBASE-R RS-FEC MDIO function mapping |
| 124 | 108.6.1 FEC_bypass_correction_enable 108.6.2 FEC_bypass_indication_enable |
| 125 | 108.6.3 25G RS-FEC Enable 108.6.4 FEC_bypass_correction_ability 108.6.5 FEC_bypass_indication_ability 108.6.6 FEC_high_ser 108.6.7 FEC_corrected_cw_counter 108.6.8 FEC_uncorrected_cw_counter |
| 126 | 108.6.9 FEC_symbol_error_counter_0 108.6.10 align_status |
| 127 | 108.7 Protocol implementation conformance statement (PICS) proforma for Clause 108, Reed-Solomon Forward Error Correction (RS-FEC) sublayer for 25GBASE-R PHYs 108.7.1 Introduction 108.7.2 Identification 108.7.2.1 Implementation identification 108.7.2.2 Protocol summary |
| 128 | 108.7.3 Major capabilities/options 108.7.4 PICS proforma tables for Reed-Solomon Forward Error Correction (RS-FEC) sublayer for 25GBASE-R PHYs 108.7.4.1 Transmit function |
| 129 | 108.7.4.2 Receive function |
| 130 | 108.7.4.3 State diagrams 108.7.4.4 MDIO function mapping |
| 131 | 109. Physical Medium Attachment (PMA) sublayer, type 25GBASE-R 109.1 Overview 109.1.1 Scope 109.1.2 Position of the PMA in the 25GBASE-R sublayers |
| 132 | 109.1.3 Summary of functions |
| 133 | 109.1.4 PMA sublayer positioning |
| 134 | 109.2 PMA service interface |
| 135 | 109.3 Service interface below PMA |
| 136 | 109.4 Functions within the PMA 109.4.1 Signal drivers 109.4.2 PMA local loopback mode 109.4.3 PMA remote loopback mode 109.4.4 PMA test patterns |
| 137 | 109.4.4.1 Transmit PRBS31 test-pattern generation 109.4.4.2 Receive PRBS31 test-pattern generation 109.4.4.3 Transmit PRBS31 test-pattern checking |
| 138 | 109.4.4.4 Receive PRBS31 test-pattern checking 109.4.4.5 Transmit PRBS9 test-pattern generation 109.4.4.6 Receive PRBS9 test-pattern generation 109.4.4.7 Transmit square wave test-pattern generation |
| 139 | 109.4.5 Energy Efficient Ethernet for 25GAUI 109.5 Delay constraints 109.6 PMA MDIO function mapping |
| 142 | 109.7 Protocol implementation conformance statement (PICS) proforma for Clause 109, Physical Medium Attachment (PMA) sublayer, type 25GBASE-R 109.7.1 Introduction 109.7.2 Identification 109.7.2.1 Implementation identification 109.7.2.2 Protocol summary |
| 143 | 109.7.3 PICS proforma tables for the 25GBASE-R PMA Sublayer 109.7.4 Major capabilities/options 109.7.4.1 PMA functions |
| 144 | 109.7.4.2 PMA characteristics |
| 145 | 110. Physical Medium Dependent (PMD) sublayer and baseband medium, type 25GBASE-CR and 25GBASE-CR-S 110.1 Overview |
| 146 | 110.2 PMD service interface |
| 147 | 110.3 PCS requirements for Auto-Negotiation (AN) service interface 110.4 Delay constraints |
| 148 | 110.5 PMD MDIO function mapping 110.6 FEC modes |
| 149 | 110.7 PMD functional specifications 110.7.1 Link block diagram |
| 150 | 110.7.2 PMD transmit function |
| 151 | 110.7.3 PMD receive function 110.7.4 Global PMD signal detect function 110.7.5 Global PMD transmit disable function |
| 152 | 110.7.6 Loopback mode 110.7.7 PMD fault function 110.7.8 PMD transmit fault function 110.7.9 PMD receive fault function 110.7.10 PMD control function 110.8 Electrical characteristics 110.8.1 Signal levels |
| 153 | 110.8.2 Signal paths 110.8.3 Transmitter characteristics 110.8.4 Receiver characteristics 110.8.4.1 Receiver input amplitude tolerance 110.8.4.2 Receiver interference tolerance test |
| 155 | 110.8.4.2.1 Test setup 110.8.4.2.2 Test channel 110.8.4.2.3 Test channel calibration |
| 157 | 110.8.4.2.4 Pattern generator and noise injection 110.8.4.2.5 Test procedure 110.8.4.3 Receiver jitter tolerance |
| 158 | 110.8.4.4 Signaling rate range 110.9 Channel characteristics 110.10 Cable assembly characteristics |
| 159 | 110.10.1 Characteristic impedance and reference impedance 110.10.2 Cable assembly insertion loss 110.10.3 Cable assembly differential return loss |
| 160 | 110.10.4 Differential to common-mode return loss 110.10.5 Differential to common-mode conversion loss 110.10.6 Common-mode to common-mode return loss 110.10.7 Cable assembly Channel Operating Margin |
| 161 | 110.10.7.1 Channel signal and crosstalk path calculations |
| 162 | 110.10.7.1.1 Channel signal path 110.10.7.1.2 Channel crosstalk paths |
| 163 | 110.10.7.2 Signal and crosstalk paths used in calculation of COM 110.10.7.2.1 SFP28 to SFP28 110.10.7.2.2 QSFP28 to SFP28 110.10.7.2.3 SFP28 to QSFP28 |
| 164 | 110.10.7.2.4 QSFP28 to QSFP28 110.11 MDI specification 110.11.1 Single-lane MDI connectors |
| 165 | 110.12 Environmental specifications |
| 166 | 110.13 Protocol implementation conformance statement (PICS) proforma for Clause 110, Physical Medium Dependent (PMD) sublayer and baseband medium, type 25GBASE-CR and 25GBASE-CR-S 110.13.1 Introduction 110.13.2 Identification 110.13.2.1 Implementation identification 110.13.2.2 Protocol summary |
| 167 | 110.13.3 Major capabilities/options |
| 168 | 110.13.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and baseband medium, type 25GBASE-CR and 25GBASE-CR-S 110.13.4.1 PMD functional specifications |
| 169 | 110.13.4.2 Management functions 110.13.4.3 Transmitter specifications |
| 171 | 110.13.4.4 Receiver specifications |
| 172 | 110.13.4.5 Cable assembly specifications 110.13.4.6 MDI connector specifications |
| 173 | 110.13.4.7 Environmental specifications |
| 174 | 111. Physical Medium Dependent (PMD) sublayer and baseband medium, type 25GBASE-KR and 25GBASE-KR-S 111.1 Overview |
| 175 | 111.2 PMD service interface |
| 176 | 111.3 PCS requirements for Auto-Negotiation (AN) service interface 111.4 Delay constraints 111.5 PMD MDIO function mapping |
| 177 | 111.6 FEC modes |
| 178 | 111.7 PMD functional specifications 111.7.1 Link block diagram 111.7.2 PMD transmit function |
| 179 | 111.7.3 PMD receive function 111.7.4 Global PMD signal detect function 111.7.5 Global PMD transmit disable function 111.7.6 Loopback mode |
| 180 | 111.7.7 PMD fault function 111.7.8 PMD transmit fault function 111.7.9 PMD receive fault function 111.7.10 PMD control function 111.8 Electrical characteristics 111.8.1 MDI |
| 181 | 111.8.2 Transmitter characteristics 111.8.3 Receiver characteristics 111.8.3.1 Receiver interference tolerance |
| 183 | 111.8.3.2 Receiver jitter tolerance |
| 184 | 111.9 Channel characteristics 111.9.1 25GBASE-KR channel 111.9.2 25GBASE-KR-S channel |
| 185 | 111.10 Environmental specifications |
| 186 | 111.11 Protocol implementation conformance statement (PICS) proforma for Clause 111, Physical Medium Dependent (PMD) sublayer and baseband medium, type 25GBASE-KR and 25GBASE-KR-S 111.11.1 Introduction 111.11.2 Identification 111.11.2.1 Implementation identification 111.11.2.2 Protocol summary |
| 187 | 111.11.3 Major capabilities/options |
| 188 | 111.11.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and baseband medium, type 25GBASE-KR and 25GBASE-KR-S 111.11.4.1 Functional specifications |
| 189 | 111.11.4.2 Transmitter characteristics |
| 191 | 111.11.4.3 Receiver characteristics 111.11.4.4 Channel characteristics |
| 192 | 111.11.4.5 Environmental specifications |
| 193 | 112. Physical Medium Dependent (PMD) sublayer and medium, type 25GBASE-SR 112.1 Overview |
| 194 | 112.1.1 Bit error ratio 112.2 Physical Medium Dependent (PMD) service interface |
| 195 | 112.3 Delay constraints 112.4 PMD MDIO function mapping |
| 196 | 112.5 PMD functional specifications 112.5.1 PMD block diagram |
| 197 | 112.5.2 PMD transmit function 112.5.3 PMD receive function 112.5.4 PMD global signal detect function |
| 198 | 112.5.5 PMD reset function 112.5.6 PMD global transmit disable function (optional) 112.5.7 PMD fault function (optional) 112.5.8 PMD transmit fault function (optional) 112.5.9 PMD receive fault function (optional) 112.6 PMD to MDI optical specifications for 25GBASE-SR |
| 199 | 112.6.1 25GBASE-SR transmitter optical specifications 112.6.2 25GBASE-SR receive optical specifications 112.6.3 25GBASE-SR illustrative link power budget 112.7 Definition of optical parameters and measurement methods 112.7.1 Test patterns for optical parameters |
| 200 | 112.7.2 Center wavelength and spectral width 112.7.3 Average optical power 112.7.4 Optical Modulation Amplitude (OMA) 112.7.5 Transmitter and dispersion eye closure (TDEC) 112.7.6 Extinction ratio 112.7.7 Transmitter optical waveform (transmit eye) 112.7.8 Stressed receiver sensitivity 112.8 Safety, installation, environment, and labeling 112.8.1 General safety |
| 201 | 112.8.2 Laser safety 112.8.3 Installation 112.8.4 Environment 112.8.5 Electromagnetic emission 112.8.6 Temperature, humidity, and handling 112.8.7 PMD labeling requirements |
| 202 | 112.9 Fiber optic cabling model 112.10 Characteristics of the fiber optic cabling (channel) 112.10.1 Optical fiber cable 112.10.2 Optical fiber connection |
| 203 | 112.10.2.1 Connection insertion loss 112.10.2.2 Maximum discrete reflectance 112.10.3 Medium Dependent Interface (MDI) |
| 204 | 112.11 Protocol implementation conformance statement (PICS) proforma for Clause 112, Physical Medium Dependent (PMD) sublayer and medium, type 25GBASE-SR 112.11.1 Introduction 112.11.2 Identification 112.11.2.1 Implementation identification 112.11.2.2 Protocol summary |
| 205 | 112.11.3 Major capabilities/options 112.11.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and medium, type 25GBASE-SR 112.11.4.1 PMD functional specifications |
| 206 | 112.11.4.2 Management functions 112.11.4.3 PMD to MDI optical specifications for 25GBASE-SR |
| 207 | 112.11.4.4 Optical measurement methods 112.11.4.5 Environmental specifications 112.11.4.6 Characteristics of the fiber optic cabling and MDI |
| 208 | Annex 4A (normative) Simplified full duplex media access control 4A.4 Specific implementations 4A.4.2 MAC parameters |
| 209 | Annex 31B (normative) MAC Control PAUSE operation |
| 211 | Annex 93A (normative) Specification methods for electrical channels 93A.1 Channel Operating Margin |
| 212 | 93A.1.4 Filters 93A.2 Test channel calibration using COM |
| 213 | Annex 109A (normative) Chip-to-chip 25 Gigabit Attachment Unit Interface (25GAUI C2C) 109A.1 Overview |
| 214 | 109A.2 25GAUI C2C compliance point definition 109A.3 25GAUI C2C electrical characteristics 109A.3.1 25GAUI C2C transmitter characteristics 109A.3.2 25GAUI C2C receiver characteristics 109A.3.3 Optional EEE operation 109A.4 25GAUI C2C channel characteristics |
| 215 | 109A.5 Protocol implementation conformance statement (PICS) proforma for Annex 109A, Chip-to-chip 25 Gigabit Attachment Unit Interface (25GAUI C2C) 109A.5.1 Introduction 109A.5.2 Identification 109A.5.2.1 Implementation identification 109A.5.2.2 Protocol summary |
| 216 | 109A.5.3 Major capabilities/options 109A.5.4 PICS proforma tables for chip-to-chip 25 Gigabit Attachment Unit Interface (25GAUI C2C) 109A.5.4.1 Transmitter |
| 217 | 109A.5.4.2 Receiver 109A.5.4.3 Channel |
| 218 | Annex 109B (normative) Chip-to-module 25 Gigabit Attachment Unit Interface (25GAUI C2M) 109B.1 Overview |
| 219 | 109B.1.1 Bit error ratio 109B.2 25GAUI C2M compliance point definitions 109B.3 25GAUI C2M electrical characteristics 109B.3.1 25GAUI C2M host output characteristics 109B.3.2 25GAUI C2M module output characteristics |
| 220 | 109B.3.2.1 25GAUI C2M module output eye opening 109B.3.2.1.1 Eye opening using measurement method A 109B.3.2.1.2 Eye opening using measurement method B 109B.3.3 25GAUI C2M host input characteristics 109B.3.4 25GAUI C2M module input characteristics |
| 221 | 109B.3.4.1 Module stressed input test using measurement method A 109B.3.4.2 Module stressed input test using measurement method B 109B.4 25GAUI C2M measurement methodology 109B.4.1 Eye width, eye height, and eye closure measurement method B |
| 223 | 109B.5 Protocol implementation conformance statement (PICS) proforma for Annex 109B, Chip-to-module 25 Gigabit Attachment Unit Interface (25GAUI C2M) 109B.5.1 Introduction 109B.5.2 Identification 109B.5.2.1 Implementation identification 109B.5.2.2 Protocol summary |
| 224 | 109B.5.3 Major capabilities/options 109B.5.4 PICS proforma tables for chip-to-module 25 Gigabit Attachment Unit Interface (25GAUI C2M) 109B.5.3.1 Host output |
| 225 | 109B.5.4.2 Module output 109B.5.4.3 Host input |
| 226 | 109B.5.4.4 Module input |
| 227 | Annex 109C (informative) 25GBASE-R PMA sublayer partitioning examples |
| 231 | Annex 110A (informative) TP0 and TP5 test point parameters and channel characteristics for 25GBASE-CR and 25GBASE-CR-S 110A.1 Overview 110A.2 Transmitter characteristics at TP0 110A.3 Receiver characteristics at TP5 110A.4 Transmitter and receiver differential printed circuit board trace loss 110A.5 Channel insertion loss |
| 233 | 110A.6 Channel return loss 110A.7 Channel Operating Margin (COM) |
| 234 | Annex 110B (normative) Test fixtures for 25GBASE-CR, 25GBASE-CR-S, and 25GAUI C2M 110B.1 Test fixtures 110B.1.1 SFP28 TP2 or TP3 test fixture 110B.1.2 SFP28 Cable assembly test fixture |
| 235 | 110B.1.3 SFP28 Mated test fixtures 110B.1.3.1 Mated test fixtures differential insertion loss 110B.1.3.2 Mated test fixtures differential return loss 110B.1.3.3 Mated test fixtures common-mode conversion insertion loss 110B.1.3.4 Mated test fixtures common-mode return loss 110B.1.3.5 Mated test fixtures common-mode to differential mode return loss 110B.1.3.7 Mated test fixtures integrated near-end crosstalk noise |
| 237 | 110B.2 Protocol implementation conformance statement (PICS) proforma for Annex 110B, Test fixtures for 25GBASE-CR, 25GBASE-CR-S, and 25GAUI C2M 110B.2.1 Introduction 110B.2.2 Identification 110B.2.2.1 Implementation identification 110B.2.2.2 Protocol summary |
| 238 | 110B.2.3 Major capabilities/options 110B.2.4 PICS proforma tables for test fixtures for 25GBASE-CR, 25GBASE-CR-S, and 25GAUI C2M |
| 239 | Annex 110C (informative) Host and cable assembly form factors for 25GBASE-CR and 25GBASE-CR-S PHYs 110C.1 Overview |
| 240 | 110C.2 Host form factors 110C.2.1 SFP28 host form factor 110C.2.2 QSFP28 host form factor |
| 241 | 110C.3 Cable assembly form factors 110C.3.1 SFP28 to SFP28 cable assembly form factor |
| 242 | 110C.3.2 QSFP28 to QSFP28 cable assembly form factor |
| 243 | 110C.3.3 QSFP28 to 4×SFP28 cable assembly form factor |
| 244 | Back cover |
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