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IEEE 802.3ck-2022

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IEEE Standard for Ethernet Amendment 4: Physical Layer Specifications and Management Parameters for 100 Gb/s, 200 Gb/s, and 400 Gb/s Electrical Interfaces Based on 100 Gb/s Signaling (Approved Draft)

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IEEE 2022 316
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Amendment Standard – Active. This amendment to IEEE Std 802.3-202x adds Clause 161 through Clause 163, Annex 120F, Annex 120G, and Annex 162A through Annex 162D, Annex 163A, and Annex 163B. This amendment includes Physical Layer specifications and management parameters for 100 Gb/s, 200 Gb/s, and 400 Gb/s electrical interfaces based on 100 Gb/s signaling.

PDF Catalog

PDF Pages PDF Title
1 Front Cover
2 Title page
4 Important Notices and Disclaimers Concerning IEEE Standards Documents
8 Participants
11 Introduction
14 Contents
30 1. Introduction
1.1 Overview
1.1.3 Architectural perspectives
1.1.3.2 Compatibility interfaces
31 1.3 Normative references
1.4 Definitions
32 1.5 Abbreviations
33 30. Management
30.5 Layer management for medium attachment units (MAUs)
30.5.1 MAU managed object class
30.5.1.1 MAU attributes
30.5.1.1.2 aMAUType
30.5.1.1.16 aFECmode
34 30.5.1.1.17 aFECCorrectedBlocks
30.5.1.1.18 aFECUncorrectedBlocks
35 30.6 Management for link Auto-Negotiation
30.6.1 Auto-Negotiation managed object class
30.6.1.1 Auto-Negotiation attributes
30.6.1.1.5 aAutoNegLocalTechnologyAbility
36 45. Management Data Input/Output (MDIO) Interface
45.2 MDIO Interface Registers
45.2.1 PMA/PMD registers
45.2.1.6 PMA/PMD control 2 register (Register 1.7)
37 45.2.1.7 PMA/PMD status 2 register (Register 1.8)
45.2.1.7.4 Transmit fault (1.8.11)
45.2.1.7.5 Receive fault (1.8.10)
38 45.2.1.8 PMD transmit disable register (Register 1.9)
45.2.1.21 200G PMA/PMD extended ability (Register 1.23)
45.2.1.21.1c 200GBASE-CR2 ability (1.23.8)
39 45.2.1.21.1d 200GBASE-KR2 ability (1.23.7)
45.2.1.22 400G PMA/PMD extended ability register (Register 1.24)
45.2.1.22.11 400GBASE-CR4 ability (1.24.1)
45.2.1.22.12 400GBASE-KR4 ability (1.24.0)
40 45.2.1.24 40G/100G PMA/PMD extended ability 2 (Register 1.26)
45.2.1.24.9 100GBASE-CR1 ability (1.26.1)
45.2.1.24.10 100GBASE-KR1 ability (1.26.0)
45.2.1.95 BASE-R PMD control register (Register 1.150)
45.2.1.96 BASE-R PMD status register (Register 1.151)
41 45.2.1.116 RS-FEC control register (Register 1.200)
45.2.1.116.a 100G RS-FEC enable (1.200.6)
45.2.1.116.b 100G RS-FEC-Int enable (1.200.5)
45.2.1.116.1 FEC degraded SER enable (1.200.4)
45.2.1.116.4 FEC bypass indication enable (1.200.1)
42 45.2.1.117 RS-FEC status register (Register 1.201)
45.2.1.117.1 PCS align status (1.201.15)
45.2.1.117.2 RS-FEC align status (1.201.14)
45.2.1.117.3 FEC AM lock 3 (1.201.11)
45.2.1.117.4 FEC AM lock 2 (1.201.10)
45.2.1.117.5 FEC AM lock 1 (1.201.9)
45.2.1.117.6 FEC AM lock 0 (1.201.8)
43 45.2.1.117.8 FEC degraded SER (1.201.4)
45.2.1.117.9 FEC degraded SER ability (1.201.3)
45.2.1.117.10 RS-FEC high SER (1.201.2)
45.2.1.117.11 FEC bypass indication ability (1.201.1)
45.2.1.118 RS-FEC corrected codewords counter (Register 1.202, 1.203)
45.2.1.119 RS-FEC uncorrected codewords counter (Register 1.204, 1.205)
45.2.1.120a RS-FEC codeword counter register (Register 1.207, 1.208, 1.209)
44 45.2.1.121 RS-FEC symbol error counter lane 0 (Register 1.210, 1.211)
45.2.1.123 RS-FEC BIP error counter lane 0 (Register 1.230)
45.2.1.127 RS-FEC PCS alignment status 1 register (Register 1.280)
45.2.1.127.1 Block lock 7 (1.280.7)
45.2.1.127.2 Block lock 6 (1.280.6)
45.2.1.127.3 Block lock 5 (1.280.5)
45.2.1.127.4 Block lock 4 (1.280.4)
45 45.2.1.127.5 Block lock 3 (1.280.3)
45.2.1.127.6 Block lock 2 (1.280.2)
45.2.1.127.7 Block lock 1 (1.280.1)
45.2.1.127.8 Block lock 0 (1.280.0)
45.2.1.128 RS-FEC PCS alignment status 2 register (Register 1.281)
45.2.1.128.1 Block lock 19 (1.281.11)
45.2.1.128.2 Block lock 18 (1.281.10)
45.2.1.128.3 Block lock 17 (1.281.9)
45.2.1.128.4 Block lock 16 (1.281.8)
46 45.2.1.128.5 Block lock 15 (1.281.7)
45.2.1.128.6 Block lock 14 (1.281.6)
45.2.1.128.7 Block lock 13 (1.281.5)
45.2.1.128.8 Block lock 12 (1.281.4)
45.2.1.128.9 Block lock 11 (1.281.3)
45.2.1.128.10 Block lock 10 (1.281.2)
45.2.1.128.11 Block lock 9 (1.281.1)
45.2.1.128.12 Block lock 8 (1.281.0)
47 45.2.1.129 RS-FEC PCS alignment status 3 register (Register 1.282)
45.2.1.129.1 Lane 7 aligned (1.282.7)
45.2.1.129.2 Lane 6 aligned (1.282.6)
45.2.1.129.3 Lane 5 aligned (1.282.5)
45.2.1.129.4 Lane 4 aligned (1.282.4)
45.2.1.129.5 Lane 3 aligned (1.282.3)
45.2.1.129.6 Lane 2 aligned (1.282.2)
45.2.1.129.7 Lane 1 aligned (1.282.1)
45.2.1.129.8 Lane 0 aligned (1.282.0)
48 45.2.1.130 RS-FEC PCS alignment status 4 register (Register 1.283)
45.2.1.130.1 Lane 19 aligned (1.283.11)
45.2.1.130.2 Lane 18 aligned (1.283.10)
45.2.1.130.3 Lane 17 aligned (1.283.9)
45.2.1.130.4 Lane 16 aligned (1.283.8)
45.2.1.130.5 Lane 15 aligned (1.283.7)
45.2.1.130.6 Lane 14 aligned (1.283.6)
45.2.1.130.7 Lane 13 aligned (1.283.5)
45.2.1.130.8 Lane 12 aligned (1.283.4)
49 45.2.1.130.9 Lane 11 aligned (1.283.3)
45.2.1.130.10 Lane 10 aligned (1.283.2)
45.2.1.130.11 Lane 9 aligned (1.283.1)
45.2.1.130.12 Lane 8 aligned (1.283.0)
45.2.1.131a RS-FEC codeword error bin registers 1 through 15 (Registers 1.340 through 1.369)
50 45.2.1.146 RS-FEC degraded SER activate threshold register (Register 1.650, 1.651)
45.2.1.147 RS-FEC degraded SER deactivate threshold register (Register 1.652, 1.653)
45.2.1.148 RS-FEC degraded SER interval register (Register 1.654, 1.655)
45.2.1.161 BASE-R PAM4 PMD training LP control, lane 0 through lane 3 registers (Register 1.1120 through 1.1123)
51 45.2.1.163 BASE-R PAM4 PMD training LP status, lane 0 through lane 3 registers (Register 1.1220 through 1.1223)
52 45.2.1.165 BASE-R PAM4 PMD training LD control, lane 0 through lane 3 registers (Register 1.1320 through 1.1323)
53 45.2.1.167 BASE-R PAM4 PMD training LD status, lane 0 through lane 3 registers (Register 1.420 through 1.423)
54 45.2.1.169 Test-pattern ability (Register 1.1500)
55 45.2.1.171a PRBS9Q testing control (Register 1.1511)
56 45.2.1.216 IFEC control register (Register 1.2200)
45.2.1.216.a IFEC enable (1.2200.2)
57 45.2.7 Auto-Negotiation registers
45.2.7.12 Backplane Ethernet, BASE-R copper status (Register 7.48)
45.2.7.12.3 Negotiated Port Type (7.48.1, 7.48.2, 7.48.3, 7.48.5, 7.48.6, 7.48.8, 7.48.9, 7.48.10, 7.48.11, 7.48.12, 7.48.13, 7.48.14, 7.48.15, 7.49.0, 7.49.1, 7.49.2, 7.49.3, 7.49.4, 7.49.5)
45.2.7.13 Backplane Ethernet, BASE-R copper status 2 (Register 7.49)
58 45.2.7.13.a RS-FEC-Int negotiated (7.49.6)
45.2.7.13.1 Negotiated Port Type
59 69. Introduction to Ethernet operation over electrical backplanes
69.1 Overview
69.1.1 Scope
60 69.1.2 Relationship of Backplane Ethernet to the ISO OSI reference model
69.2 Summary of Backplane Ethernet Sublayers
69.2.1 Reconciliation sublayer and media independent interfaces
61 69.2.3 Physical Layer signaling systems
69.2.6 Low-Power Idle
69.3 Delay constraints
69.5 Protocol implementation conformance statement (PICS) proforma
62 73. Auto-Negotiation for backplane and copper cable assembly
73.2 Relationship to the ISO/IEC Open Systems Interconnection (OSI) reference model
73.5 DME transmission
73.5.1 DME electrical specifications
63 73.6 Link codeword encoding
73.6.4 Technology Ability Field
64 73.6.5 FEC capability
73.6.5.a FEC resolution for 100GBASE-P PHYs that include RS-FEC-Int
73.6.5.3 FEC control variables
65 73.7 Receive function requirements
73.7.6 Priority Resolution function
66 73.8 Management register requirements
73.10 State diagrams and variable definitions
73.10.1 State diagram variables
67 73.10.2 State diagram timers
73.11 Protocol implementation conformance statement (PICS) proforma for Clause 73, Auto-Negotiation for backplane and copper cable assembly
73.11.4 PICS proforma tables for Auto-Negotiation for backplane and copper cable assembly
73.11.4.3 Link codeword encoding
68 80. Introduction to 40 Gb/s and 100 Gb/s networks
80.1 Overview
80.1.3 Relationship of 40 Gigabit and 100 Gigabit Ethernet to the ISO OSI reference model
69 80.1.4 Nomenclature
70 80.1.5 Physical Layer signaling systems
73 80.2 Summary of 40 Gigabit and 100 Gigabit Ethernet sublayers
80.2.3 Forward error correction (FEC) sublayers
80.2.5 Physical Medium Dependent (PMD) sublayer
80.2.6 Auto-Negotiation
74 80.4 Delay constraints
75 80.5 Skew constraints
77 80.7 Protocol implementation conformance statement (PICS) proforma
78 82. Physical Coding Sublayer (PCS) for 64B/66B, type 40GBASE-R and 100GBASE-R
82.1 Overview
82.1.4 Inter-sublayer interfaces
82.2 Physical Coding Sublayer (PCS)
82.2.13 PCS lane deskew
82.6 Auto-Negotiation
79 82.7 Protocol implementation conformance statement (PICS) proforma for Clause 82, Physical Coding Sublayer (PCS) for 64B/66B, type 40GBASE-R and 100GBASE-R
82.7.4 PICS proforma tables for PCS, type 40GBASE-R and 100GBASE-R
82.7.4.11 Auto-Negotiation for Backplane Ethernet functions
80 83. Physical Medium Attachment (PMA) sublayer, type 40GBASE-R and 100GBASE-R
83.1 Overview
83.1.1 Scope
81 91. Reed-Solomon forward error correction (RS-FEC) sublayer for 100GBASE-R PHYs
91.5 Functions within the RS-FEC sublayer
91.5.2 Transmit function
91.5.2.7 Reed-Solomon encoder
91.5.3 Receive function
91.5.3.3 Reed-Solomon decoder
82 91.5.3.3.1 FEC Degraded SER (optional)
91.6 RS-FEC MDIO function mapping
91.6.3 four_lane_pmd
91.6.7a 100G_RS_FEC_enable
83 91.7 Protocol implementation conformance statement (PICS) proforma for Clause 91, Reed-Solomon forward error correction (RS-FEC) sublayer for 100GBASE-R PHYs
91.7.3 Major capabilities/options
84 91.7.4 PICS proforma tables for Reed-Solomon forward error correction (RS-FEC) sublayer for 100GBASE-R PHYs
91.7.4.1 Transmit function
91.7.4.2 Receive function
86 116. Introduction to 200 Gb/s and 400 Gb/s networks
116.1 Overview
116.1.2 Relationship of 200 Gigabit and 400 Gigabit Ethernet to the ISO OSI reference model
87 116.1.3 Nomenclature
88 116.1.4 Physical Layer signaling systems
90 116.2 Summary of 200 Gigabit and 400 Gigabit Ethernet sublayers
116.2.5 Physical Medium Dependent (PMD) sublayer
116.2.5a Auto-Negotiation
91 116.4 Delay constraints
93 116.5 Skew constraints
95 118. 200GMII Extender, 400GMII Extender, 200GMII Extender Sublayer (200GXS), and 400GMII Extender Sublayer (400GXS)
118.1 Overview
118.1.3 200GAUI-n/400GAUI-n
96 119. Physical Coding Sublayer (PCS) for 64B/66B, type 200GBASE-R and 400GBASE-R
119.6 Auto-Negotiation
119.7 Protocol implementation conformance statement (PICS) proforma for Clause 119, Physical Coding Sublayer (PCS) for 64B/66B, type 200GBASE-R and 400GBASE-R
119.7.4 PICS proforma tables for Physical Coding Sublayer (PCS) 64B/66B, type 200GBASE-R and 400GBASE-R
119.7.4.12 Auto-Negotiation for Backplane Ethernet functions
97 120. Physical Medium Attachment (PMA) sublayer, type 200GBASE-R and 400GBASE-R
120.1 Overview
120.1.1 Scope
120.1.3 Summary of functions
120.1.4 PMA sublayer positioning
98 120.3 PMA service interface
120.5 Functions within the PMA
120.5.1 Per input-lane clock and data recovery
120.5.2 Bit-level multiplexing
120.5.5 Clocking architecture
99 120.5.6 Signal drivers
120.5.7 PAM4 Encoding
120.5.7.1 Gray mapping for PAM4 encoded lanes
120.5.7.2 Precoding for PAM4 encoded lanes
100 120.5.11 PMA test patterns (optional)
120.5.11.2 Test patterns for PAM4 encoded signals
120.5.11.2.a PRBS9Q test pattern
101 120.5.11.2.4 Square wave (quaternary) test pattern
120.6 PMA MDIO function mapping
103 120.7 Protocol implementation conformance statement (PICS) proforma for Clause 120, Physical Medium Attachment (PMA) sublayer, type 200GBASE-R and 400GBASE-R
120.7.3 Major capabilities/options
105 121. Physical Medium Dependent (PMD) sublayer and medium, type 200GBASE-DR4
121.1 Overview
106 122. Physical Medium Dependent (PMD) sublayer and medium, type 200GBASE-FR4, 200GBASE-LR4, 200GBASE-ER4, 400GBASE-FR8, 400GBASE-LR8, and 400GBASE-ER8
122.1 Overview
107 123. Physical Medium Dependent (PMD) sublayer and medium, type 400GBASE-SR16
123.1 Overview
108 124. Physical Medium Dependent (PMD) sublayer and medium, type 400GBASE-DR4
124.1 Overview
109 135. Physical Medium Attachment (PMA) sublayer, type 50GBASE-R and 100GBASE-P
135.1 Overview
135.1.1 Scope
110 135.1.4 PMA sublayer positioning
111 135.5 Functions within the PMA
135.5.1 Per input-lane clock and data recovery
135.5.2 Bit-level multiplexing
112 135.5.6 Signal drivers
135.5.7 PAM4 encoding
135.5.7.2 Precoding for PAM4 encoded lanes
113 135.5.10 PMA test patterns (optional)
135.5.10.2 Test patterns for PAM4 encoded signals
135.5.10.2.4 Square wave (quaternary) test pattern
114 135.7 Protocol implementation conformance statement (PICS) proforma for Clause 135, Physical Medium Attachment (PMA) sublayer, type 50GBASE-R and 100GBASE-P
135.7.3 Major capabilities/options
115 135.7.4 PICS proforma tables for Physical Medium Attachment (PMA) sublayer, type 50GBASE-R and 100GBASE-P
135.7.4.3 Electrical
116 138. Physical Medium Dependent (PMD) sublayer and medium, type 50GBASE-SR, 100GBASE-SR2, 200GBASE-SR4, 400GBASE-SR8
138.1 Overview
117 140. Physical Medium Dependent (PMD) sublayer and medium, type 100GBASE-DR, 100GBASE-FR1, and 100GBASE-LR1
140.1 Overview
118 150. Physical Medium Dependent (PMD) sublayer and medium, type 400GBASE-SR4.2
150.1 Overview
119 151. Physical Medium Dependent (PMD) sublayer and medium, type 400GBASE-FR4 and 400GBASE-LR4-6
151.1 Overview
120 152. Inverse RS-FEC sublayer
152.6 Inverse RS-FEC MDIO function mapping
152.6.2a IFEC_enable
121 154. Physical Medium Dependent (PMD) sublayer and medium, type 100GBASE-ZR
154.1 Overview
122 161. Reed-Solomon forward error correction codeword-interleaved (RS-FEC-Int) sublayer for 100GBASE-P PHYs
161.1 Overview
161.1.1 Scope
161.1.2 Position of RS-FEC-Int in the 100GBASE-P sublayers
161.2 FEC service interface
123 161.3 PMA compatibility
161.4 Delay constraints
161.5 Functions within the RS-FEC-Int sublayer
161.5.1 Functional block diagram
161.5.2 Transmit function
161.5.2.1 Lane block synchronization
161.5.2.2 Alignment lock and deskew
161.5.2.3 Lane reorder
161.5.2.4 Alignment marker removal
161.5.2.5 64B/66B to 256B/257B transcoder
161.5.2.6 Alignment marker mapping and insertion
125 161.5.2.6.1 Alignment marker mapping
126 161.5.2.6.2 Alignment marker insertion
127 161.5.2.7 Pre-FEC distribution
161.5.2.8 Reed-Solomon encoder
161.5.2.9 Symbol distribution
128 161.5.2.10 Transmit bit ordering
129 161.5.3 Receive function
161.5.3.1 Alignment lock and deskew
161.5.3.2 Lane reorder and de-interleave
161.5.3.3 Reed-Solomon decoder
161.5.3.3.1 Bypass error indication (optional)
130 161.5.3.3.2 FEC Degraded SER (optional)
161.5.3.4 Post FEC Interleave
161.5.3.5 Alignment marker removal
161.5.3.6 256B/257B to 64B/66B transcoder
161.5.3.7 Block distribution
161.5.3.8 Alignment marker mapping and insertion
131 161.5.4 Detailed functions and state diagrams
161.5.4.1 State diagram conventions
161.5.4.2 State variables
161.5.4.2.1 Variables
132 161.5.4.2.2 Functions
161.5.4.2.3 Counters
161.5.4.3 State diagrams
134 161.6 RS-FEC-Int MDIO function mapping
135 161.6.1 FEC_bypass_indication_enable
161.6.2 FEC_degraded_SER_enable
161.6.3 100G_RS_FEC_Int_enable
161.6.4 FEC_degraded_SER_activate_threshold
136 161.6.5 FEC_degraded_SER_deactivate_threshold
161.6.6 FEC_degraded_SER_interval
161.6.7 FEC_bypass_indication_ability
161.6.8 hi_ser
161.6.9 FEC_degraded_SER_ability
161.6.10 FEC_degraded_SER
161.6.11 amps_lock
161.6.12 fec_align_status
161.6.13 FEC_corrected_cw_counter
161.6.14 FEC_uncorrected_cw_counter
161.6.15 FEC_lane_mapping
161.6.16 FEC_symbol_error_counter_i
161.6.17 FEC_codeword_error_bin_i
137 161.6.18 align_status
161.6.19 BIP_error_counter_i
161.6.20 lane_mapping
161.6.21 FEC_cw_counter
161.6.22 block_lock
161.6.23 am_lock
138 161.7 Protocol implementation conformance statement (PICS) proforma for Clause 161, Reed-Solomon forward error correction codeword-interleaved (RS-FEC-Int) sublayer for 100GBASE-P PHYs
161.7.1 Introduction
161.7.2 Identification
161.7.2.1 Implementation identification
161.7.2.2 Protocol summary
139 161.7.3 Major capabilities/options
161.7.4 PICS proforma tables for Reed-Solomon forward error correction codeword-interleaved (RS-FEC-Int) sublayer for 100GBASE-P PHYs
161.7.4.1 Transmit function
140 161.7.4.2 Receive function
141 161.7.4.3 State diagrams
142 162. Physical Medium Dependent (PMD) sublayer and baseband medium, type 100GBASE-CR1, 200GBASE-CR2, and 400GBASE-CR4
162.1 Overview
144 162.2 Conventions
145 162.3 PMD service interfaces
146 162.4 PCS requirements for Auto-Negotiation (AN) service interface
162.5 Delay constraints
162.6 Skew constraints
162.6.1 Skew Constraints for 100GBASE-CR1
147 162.6.2 Skew Constraints for 200GBASE-CR2 and 400GBASE-CR4
162.7 PMD MDIO function mapping
149 162.8 PMD functional specifications
162.8.1 Link block diagram
151 162.8.2 PMD transmit function
162.8.3 PMD receive function
152 162.8.4 PMD global signal detect function
162.8.5 PMD lane-by-lane signal detect function
162.8.6 PMD global transmit disable function (optional)
162.8.7 PMD lane-by-lane transmit disable function (optional)
162.8.8 PMD fault function
162.8.9 PMD transmit fault function (optional)
153 162.8.10 PMD receive fault function (optional)
162.8.11 PMD control function
155 162.9 PMD electrical characteristics
162.9.1 AC-coupling
162.9.2 Signal paths
156 162.9.3 Reference impedance
162.9.4 Transmitter characteristics
157 162.9.4.1 Transmitter output waveform
158 162.9.4.1.1 Linear fit to the measured waveform
159 162.9.4.1.2 Steady-state voltage and linear fit pulse peak ratio
162.9.4.1.3 Coefficient initialization
162.9.4.1.4 Coefficient step size
160 162.9.4.1.5 Coefficient range
162.9.4.2 Transmitter linearity
161 162.9.4.3 Signal-to-residual-intersymbol-interference ratio
162.9.4.4 Peak-to-peak AC common-mode voltage
162.9.4.5 Insertion loss, TP0 to TP2 or TP3 to TP5
162.9.4.6 Output SNDR
162.9.4.7 Output jitter
163 162.9.4.8 Transmitter effective return loss (ERL)
162.9.4.9 Common-mode to common-mode return loss
164 162.9.4.10 Common-mode to differential-mode return loss
165 162.9.5 Receiver characteristics
162.9.5.1 Receiver signaling rate
166 162.9.5.2 Receiver amplitude tolerance
162.9.5.3 Receiver interference tolerance
162.9.5.3.1 Test setup
167 162.9.5.3.2 Test channel
162.9.5.3.3 Test channel calibration
169 162.9.5.3.4 Pattern generator and noise injection
170 162.9.5.3.5 Test procedure
162.9.5.4 Receiver jitter tolerance
162.9.5.4.1 Test setup
162.9.5.4.2 Test procedure
171 162.9.5.5 Receiver ERL
162.9.5.6 Differential-mode to common-mode return loss
172 162.10 Channel characteristics
162.11 Cable assembly characteristics
162.11.1 Characteristic impedance and reference impedance
162.11.2 Cable assembly insertion loss
174 162.11.3 Cable assembly ERL
162.11.4 Differential-mode to common-mode return loss
175 162.11.5 Differential-mode to common-mode insertion loss
176 162.11.6 Common-mode to common-mode return loss
177 162.11.7 Cable assembly Channel Operating Margin
179 162.11.7.1 Channel signal and crosstalk path calculations
180 162.11.7.1.1 Channel signal path
162.11.7.1.2 Channel crosstalk paths
181 162.11.7.2 Signal and crosstalk paths used in calculation of COM
182 162.12 MDI specifications
162.13 Environmental specifications
183 162.14 Protocol implementation conformance statement (PICS) proforma for Clause 162, Physical Medium Dependent (PMD) sublayer and baseband medium, type 100GBASE-CR1, 200GBASE-CR2, and 400GBASE-CR4
162.14.1 Introduction
162.14.2 Identification
162.14.2.1 Implementation identification
162.14.2.2 Protocol summary
184 162.14.3 Major capabilities/options
185 162.14.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and baseband medium, type 100GBASE-CR1, 200GBASE-CR2, and 400GBASE-CR4
162.14.4.1 PMD functional specifications
186 162.14.4.2 PMD control function
162.14.4.3 Transmitter specifications
187 162.14.4.4 Receiver specifications
162.14.4.5 Cable assembly specifications
188 162.14.4.6 Environmental specifications
189 163. Physical Medium Dependent (PMD) sublayer and baseband medium, type 100GBASE-KR1, 200GBASE-KR2, and 400GBASE-KR4
163.1 Overview
192 163.2 Conventions
163.3 PMD service interfaces
163.4 PCS requirements for Auto-Negotiation (AN) service interface
163.5 Delay constraints
193 163.6 Skew constraints
163.6.1 Skew Constraints for 100GBASE-KR1
163.6.2 Skew Constraints for 200GBASE-KR2 and 400GBASE-KR4
163.7 PMD MDIO function mapping
194 163.8 PMD functional specifications
163.8.1 Link block diagram
163.8.2 PMD transmit function
163.8.3 PMD receive function
163.8.4 PMD global signal detect function
163.8.5 PMD lane-by-lane signal detect function
163.8.6 PMD global transmit disable function (optional)
163.8.7 PMD lane-by-lane transmit disable function (optional)
195 163.8.8 PMD fault function
163.8.9 PMD transmit fault function (optional)
163.8.10 PMD receive fault function (optional)
163.8.11 PMD control function
163.9 Electrical characteristics
163.9.1 Reference impedance
163.9.2 Transmitter characteristics
196 163.9.2.1 Transmitter test fixture
163.9.2.1.1 Test fixture insertion loss
197 163.9.2.1.2 Test fixture effective return loss (ERL)
163.9.2.1.3 Test fixture common-mode to common-mode return loss
163.9.2.2 Transmitter difference ERL
198 163.9.2.3 Transmitter common-mode to common-mode return loss
163.9.2.4 Difference steady-state voltage
163.9.2.5 Difference linear fit pulse peak ratio
163.9.2.6 Signal to AC common-mode noise ratio
163.9.3 Receiver characteristics
199 163.9.3.1 Receiver signaling rate
163.9.3.2 Receiver test fixture
163.9.3.3 Receiver difference ERL
163.9.3.4 Receiver differential-mode to common-mode return loss
200 163.9.3.5 Receiver interference tolerance
202 163.9.3.6 Receiver jitter tolerance
163.10 Channel characteristics
163.10.1 Channel operating margin
205 163.10.2 Channel insertion loss (recommended)
163.10.3 Channel ERL
206 163.10.4 Channel differential-mode to common-mode return loss
207 163.10.5 Channel differential-mode to common-mode insertion loss
208 163.10.6 Channel common-mode to differential-mode insertion loss
163.10.7 AC-coupling
209 163.11 MDI specifications
163.12 Environmental specifications
210 163.13 Protocol implementation conformance statement (PICS) proforma for Clause 163, Physical Medium Dependent (PMD) sublayer and baseband medium, type 100GBASE-KR1, 200GBASE-KR2, and 400GBASE-KR4
163.13.1 Introduction
163.13.2 Identification
163.13.2.1 Implementation identification
163.13.2.2 Protocol summary
211 163.13.3 Major capabilities/options
212 163.13.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and baseband medium, type 100GBASE-KR1, 200GBASE-KR2, and 400GBASE-KR4
163.13.4.1 Functional specifications
213 163.13.4.2 PMD control function
163.13.4.3 Transmitter characteristics
214 163.13.4.4 Receiver characteristics
163.13.4.5 Channel characteristics
215 163.13.4.6 Environmental specifications
216 167. Physical Medium Dependent (PMD) sublayer and medium, type 100GBASE-VR1, 200GBASE-VR2, 400GBASE-VR4, 100GBASE-SR1, 200GBASE-SR2, and 400GBASE-SR4
167.1 Overview
217 Annex 93A (normative) Specification methods for electrical channels
93A.1 Channel Operating Margin
220 93A.1.2 Transmitter and receiver device package models
93A.1.2.1 Cascade connection of two-port networks
93A.1.2.2 Two-port network for a shunt capacitance
93A.1.2.2a Two-port network for a series inductance
93A.1.2.3 Two-port network for the package transmission line
221 93A.1.2.4 Assembly of transmitter and receiver device package models
222 93A.1.6 Determination of variable equalizer parameters
223 93A.1.6.1 Determination of DFE floating tap locations and magnitudes
224 93A.5 Effective Return Loss (ERL)
93A.5.1 Pulse time-domain reflection signal
225 93A.5.2 Effective reflection waveform
226 Annex 120A (informative) 200 Gb/s and 400 Gb/s PMA sublayer partitioning examples
120A.5 Partitioning examples supporting 200GBASE-CR2/KR2 and 400GBASE-CR4/KR4
227 Annex 120F (normative) Chip-to-chip 100 Gb/s one-lane Attachment Unit Interface (100GAUI-1 C2C), 200 Gb/s two-lane Attachment Unit Interface (200GAUI-2 C2C), and 400 Gb/s four-lane Attachment Unit Interface (400GAUI-4 C2C)
120F.1 Overview
229 120F.2 Compliance points
120F.2.1 Reference impedance
120F.3 Electrical characteristics
120F.3.1 Transmitter electrical characteristics
230 120F.3.1.1 Peak-to-peak AC common-mode voltage
120F.3.1.2 Signal to AC common-mode noise ratio
231 120F.3.1.3 Signal-to-residual-intersymbol-interference ratio
120F.3.1.4 Transmitter difference effective return loss (ERL)
120F.3.1.5 Transmitter equalization settings
232 120F.3.1.6 Output jitter
233 120F.3.1.7 Transmitter control
120F.3.2 Receiver characteristics
234 120F.3.2.1 Receiver signaling rate
120F.3.2.2 Receiver difference ERL
120F.3.2.3 Receiver differential-mode to common-mode return loss
120F.3.2.4 Receiver interference tolerance
236 120F.3.2.5 Receiver jitter tolerance
120F.3.2.6 Transmitter equalization feedback (optional)
237 120F.4 Channel characteristics
120F.4.1 Channel operating margin
239 120F.4.2 Channel insertion loss (recommended)
240 120F.4.3 Channel ERL
120F.4.4 Channel differential-mode to common-mode return loss
120F.4.5 Channel AC-Coupling
241 120F.5 Protocol implementation conformance statement (PICS) proforma for Annex 120F, Chip-to-chip 100 Gb/s one-lane Attachment Unit Interface (100GAUI-1 C2C), 200 Gb/s two-lane Attachment Unit Interface (200GAUI-2 C2C), and 400 Gb/s four-lane Attachm…
120F.5.1 Introduction
120F.5.2 Identification
120F.5.2.1 Implementation identification
120F.5.2.2 Protocol summary
242 120F.5.3 Major capabilities/options
120F.5.4 PICS proforma tables for Chip-to-chip 100 Gb/s one-lane Attachment Unit Interface (100GAUI-1 C2C), 200 Gb/s two-lane Attachment Unit Interface (200GAUI-2 C2C), and 400 Gb/s four-lane Attachment Unit Interface (400GAUI-4 C2C)
120F.5.4.1 Transmitter
243 120F.5.4.2 Receiver
244 Annex 120G (normative) Chip-to-module 100 Gb/s one-lane Attachment Unit Interface (100GAUI-1 C2M), 200 Gb/s two-lane Attachment Unit Interface (200GAUI-2 C2M), and 400 Gb/s four-lane Attachment Unit Interface (400GAUI-4 C2M)
120G.1 Overview
245 120G.1.1 Bit error ratio
120G.2 Compliance point definitions
246 120G.3 Electrical characteristics
120G.3.1 Host output characteristics
247 120G.3.1.1 Host output common-mode to differential-mode return loss
248 120G.3.1.2 Host output effective return loss (ERL)
120G.3.1.3 Differential termination mismatch
120G.3.1.4 Transition time
249 120G.3.1.5 Host output eye height and vertical eye closure (VEC)
120G.3.2 Module output characteristics
250 120G.3.2.1 Module output modes
251 120G.3.2.2 Module output eye height and VEC
252 120G.3.2.2.1 Near-end and far-end eye measurement methodology
120G.3.2.3 Module output ERL
120G.3.2.4 Module output common-mode voltage tolerance
253 120G.3.3 Host input characteristics
120G.3.3.1 Host input signaling rate
120G.3.3.2 Host input AC common-mode voltage tolerance
120G.3.3.3 Host input differential-mode to common-mode return loss
254 120G.3.3.4 Host input ERL
120G.3.3.5 Host stressed input tolerance
120G.3.3.5.1 Host stressed input test setup
256 120G.3.3.5.2 Host stressed input test calibration
257 120G.3.3.5.3 Host stressed input test procedure
258 120G.3.4 Module input characteristics
120G.3.4.1 Module input signaling rate
120G.3.4.2 Module input AC common-mode voltage tolerance
120G.3.4.3 Module stressed input tolerance
259 120G.3.4.3.1 Module stressed input test setup
260 120G.3.4.3.2 Module stressed input test calibration
262 120G.3.4.3.3 Module stressed input test procedure
263 120G.3.4.4 Module input ERL
120G.3.4.5 Module input common-mode voltage tolerance
120G.4 Channel insertion loss (recommended)
264 120G.5 Measurement methodology
120G.5.1 Signal levels
120G.5.2 Eye opening measurement method
266 120G.5.3 Steady-state voltage
120G.5.4 HCB/MCB characteristics
268 120G.6 Protocol implementation conformance statement (PICS) proforma for Annex 120G, Chip-to-module 100 Gb/s one-lane Attachment Unit Interface (100GAUI-1 C2M), 200 Gb/s two-lane Attachment Unit Interface (200GAUI-2 C2M), and 400 Gb/s four-lane Attac…
120G.6.1 Introduction
120G.6.2 Identification
120G.6.2.1 Implementation identification
120G.6.2.2 Protocol summary
269 120G.6.3 Major capabilities/options
120G.6.4 PICS proforma tables for Chip-to-module 100 Gb/s one-lane Attachment Unit Interface (100GAUI-1 C2M), 200 Gb/s two-lane Attachment Unit Interface (200GAUI-2 C2M), and 400 Gb/s four-lane Attachment Unit Interface (400GAUI-4 C2M)
120G.6.4.1 Host output
270 120G.6.4.2 Module output
120G.6.4.3 Host input
271 120G.6.4.4 Module input
272 Annex 135A (informative) 50 Gb/s and 100 Gb/s PMA sublayer partitioning examples
135A.2 Partitioning examples of 100GBASE-P PHYs
274 Annex 162A (informative) Transmitter, receiver and channel parameters associated with test points TP0 and TP5 for 100GBASE-CR1, 200GBASE-CR2, and 400GBASE-CR4
162A.1 Overview
162A.2 Transmitter characteristics at TP0
162A.3 Receiver characteristics at TP5
162A.4 Transmitter and receiver differential printed circuit board (PCB) trace insertion loss
276 162A.5 Channel insertion loss
279 162A.6 Channel effective return loss (ERL)
162A.7 Channel Operating Margin (COM)
280 Annex 162B (normative) Test fixtures for 100GBASE-CR1, 200GBASE-CR2, 400GBASE-CR4, 100GAUI-1 C2M, 200GAUI-2 C2M, and 400GAUI-4 C2M
162B.1 Test fixtures
162B.2 TP2 or TP3 test fixture
162B.2.1 TP2 or TP3 test fixture insertion loss
281 162B.3 Cable assembly test fixture
162B.3.1 Cable assembly test fixture insertion loss
282 162B.4 Mated test fixtures
162B.4.1 Mated test fixtures insertion loss
283 162B.4.2 Mated test fixtures effective return loss (ERL)
284 162B.4.3 Mated test fixtures common-mode to differential-mode insertion loss
162B.4.4 Mated test fixtures common-mode to common-mode return loss
285 162B.4.5 Mated test fixtures common-mode to differential-mode return loss
286 162B.4.6 Mated test fixtures integrated crosstalk noise
288 162B.5 Protocol implementation conformance statement (PICS) proforma for Annex 162B, Test fixtures for 100GBASE-CR1, 200GBASE-CR2, 400GBASE-CR4, 100GAUI-1 C2M, 200GAUI-2 C2M, and 400GAUI-4 C2M
162B.5.1 Introduction
162B.5.2 Identification
162B.5.2.1 Implementation identification
162B.5.2.2 Protocol summary
289 162B.5.3 Major capabilities/options
162B.5.4 PICS proforma tables for test fixtures for Test fixtures for 100GBASE-CR1, 200GBASE-CR2, 400GBASE-CR4, 100GAUI-1 C2M, 200GAUI-2 C2M, and 400GAUI-4 C2M
290 Annex 162C (normative) MDIs for 100GBASE-CR1, 200GBASE-CR2, and 400GBASE-CR4
162C.1 Overview
296 162C.2 MDI connector types
162C.2.1 SFP112
297 162C.2.2 SFP-DD112
298 162C.2.3 DSFP
299 162C.2.4 QSFP112
300 162C.2.5 QSFP-DD800
301 162C.2.6 OSFP
303 162C.3 Protocol implementation conformance statement (PICS) proforma for Annex 162C, MDIs for 100GBASE-CR1, 200GBASE-CR2, and 400GBASE-CR4
162C.3.1 Introduction
162C.3.2 Identification
162C.3.2.1 Implementation identification
162C.3.2.2 Protocol summary
304 162C.3.3 Major capabilities/options
162C.3.4 PICS proforma tables for MDIs for 100GBASE-CR1, 200GBASE-CR2, and 400GBASE-CR4
162C.3.4.1 Contact Mapping
305 Annex 162D (informative) Cable assemblies and hosts for 100GBASE-CR1, 200GBASE-CR2, and 400GBASE-CR4
162D.1 Overview
162D.1.1 Cable assembly types
308 Annex 163A (normative) Specification methods for electrical interfaces
163A.1 Overview
309 163A.2 Test fixture
163A.3 Test methods for transmitters
163A.3.1 Reference parameter determination
163A.3.1.1 Steady-state voltage and pulse peak reference values
310 163A.3.1.2 ERL reference value
163A.3.1.3 Transition time reference value
311 163A.3.2 Difference parameter determination
163A.3.2.1 Steady-state voltage and pulse peak ratio
312 163A.3.2.2 Difference ERL
163A.4 Test methods for receivers
313 163A.4.1 Reference parameter determination
163A.4.1.1 ERL reference value
163A.4.1.2 Difference ERL
314 Annex 163B (informative) Example test fixture
163B.1 Overview
163B.2 Characteristics
315 163B.3 Reference Values
316 Back Cover
IEEE 802.3ck-2022
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