IEEE 802.3cx-2023

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IEEE Standard for Ethernet Amendment 6: Media Access Control (MAC) Service Interface and Management Parameters to Support Improved Precision Time Protocol (PTP) Timestamping Accuracy (Published)

Published By	Publication Date	Number of Pages
IEEE	2023	79

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Amendment Standard – Active. This amendment to IEEE Std 802.3-2022 modifies Clause 30, Clause 45, and Clause 90, and adds Annex 90A to enhance support for time synchronization protocols by providing options for sub-nanosecond reporting of the transmit and receive path data delays, selection of the data delay measurement point, and dynamic reporting of path data delay variation.

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PDF Pages	PDF Title
1	Front Cover
2	Title page
4	Important Notices and Disclaimers Concerning IEEE Standards Documents
8	Participants
11	Introduction
14	Contents
18	1. Introduction 1.5 Abbreviations
19	30. Management 30.2 Managed objects 30.2.5 Capabilities
20	30.13 Management for oTimeSync entity 30.13.1 TimeSync entity managed object class 30.13.1.1 aTimeSyncCapabilityNsTX 30.13.1.2 aTimeSyncCapabilityNsRX
21	30.13.1.3 aTimeSyncDelayNsTXmax 30.13.1.4 aTimeSyncDelayNsTXmin
22	30.13.1.5 aTimeSyncDelayNsRXmax 30.13.1.6 aTimeSyncDelayNsRXmin
23	30.13.1.7 aTimeSyncCapabilitySubNsTX 30.13.1.8 aTimeSyncCapabilitySubNsRX 30.13.1.9 aTimeSyncDelaySubNsTXmax
24	30.13.1.10 aTimeSyncDelaySubNsTXmin 30.13.1.11 aTimeSyncDelaySubNsRXmax
25	30.13.1.12 aTimeSyncDelaySubNsRXmin 30.13.1.13 aTimeSyncCapabilityDdmp 30.13.1.14 aTimeSyncSelectionDdmp
26	30.13.1.15 aTimeSyncCapabilityMultiplePcsLane 30.13.1.16 aTimeSyncCapabilityDynamicPathDataDelay
27	45. Management Data Input/Output (MDIO) Interface 45.2 MDIO Interface registers 45.2.1 PMA/PMD registers 45.2.1.175 TimeSync PMA/PMD capability (Register 1.1800)
28	45.2.1.176 TimeSync PMA/PMD transmit path data delay (Registers 1.1801, 1.1802, 1.1803, 1.1804, 1.1809, and 1.1810)
29	45.2.1.177 TimeSync PMA/PMD receive path data delay (Registers 1.1805, 1.1806, 1.1807, 1.1808, 1.1811, and 1.1812)
30	45.2.2 WIS registers
31	45.2.2.20 TimeSync WIS capability (Register 2.1800) 45.2.2.21 TimeSync WIS transmit path data delay (Registers 2.1801, 2.1802, 2.1803, 2.1804, 2.1809, and 2.1810)
32	45.2.2.22 TimeSync WIS receive path data delay (Registers 2.1805, 2.1806, 2.1807, 2.1808, 2.1811, and 2.1812)
34	45.2.3 PCS registers 45.2.3.67 TimeSync PCS capability (Register 3.1800)
35	45.2.3.67.1 Data delay measurement point ability (3.1800.13:12) 45.2.3.67.2 Multilane ability (3.1800.11)
36	45.2.3.67.3 PCS dynamic path data delay ability (3.1800.10) 45.2.3.67.4 TimeSync transmit path data delay ability, in sub-ns (3.1800.3) 45.2.3.67.5 TimeSync receive path data delay ability, in sub-ns (3.1800.2) 45.2.3.67.6 TimeSync transmit path data delay ability, in ns (3.1800.1) 45.2.3.67.7 TimeSync receive path data delay ability, in ns (3.1800.0) 45.2.3.68 TimeSync PCS transmit path data delay (Registers 3.1801, 3.1802, 3.1803, 3.1804, 3.1809, and 3.1810)
37	45.2.3.69 TimeSync PCS receive path data delay (Registers 3.1805, 3.1806, 3.1807, 3.1808, 3.1811, and 3.1812)
38	45.2.3.69a TimeSync PCS configuration (Register 3.1813)
39	45.2.3.69a.1 Data delay measurement point (3.1813.13) 45.2.4 PHY XS registers 45.2.4.28 TimeSync PHY XS capability (Register 4.1800)
40	45.2.4.29 TimeSync PHY XS transmit path data delay (Registers 4.1801, 4.1802, 4.1803, 4.1804, 4.1809, and 4.1810)
41	45.2.4.30 TimeSync PHY XS receive path data delay (Registers 4.1805, 4.1806, 4.1807, 4.1808, 4.1811, and 4.1812)
42	45.2.5 DTE XS registers
43	45.2.5.28 TimeSync DTE XS capability (Register 5.1800) 45.2.5.28.1 Data delay measurement point ability (5.1800.13:12)
44	45.2.5.28.2 TimeSync transmit path data delay ability, in sub-ns (5.1800.3) 45.2.5.28.3 TimeSync receive path data delay ability, in sub-ns (5.1800.2) 45.2.5.28.4 TimeSync transmit path data delay ability, in ns (5.1800.1) 45.2.5.28.5 TimeSync receive path data delay ability, in ns (5.1800.0) 45.2.5.29 TimeSync DTE XS transmit path data delay (Registers 5.1801, 5.1802, 5.1803, 5.1804, 5.1809, and 5.1810)
45	45.2.5.30 TimeSync DTE XS receive path data delay (Registers 5.1805, 5.1806, 5.1807, 5.1808, 5.1811, and 5.1812)
46	45.2.5.31 TimeSync DTE XS configuration (Register 5.1813)
47	45.2.5.31.1 Data delay measurement point (5.1813.13) 45.2.6 TC registers 45.2.6.14 TimeSync TC capability (Register 6.1800)
48	45.2.6.15 TimeSync TC transmit path data delay (Registers 6.1801, 6.1802, 6.1803, 6.1804, 6.1809, and 6.1810)
49	45.2.6.16 TimeSync TC receive path data delay (Registers 6.1805, 6.1806, 6.1807, 6.1808, 6.1811, and 6.1812)
51	90. Ethernet support for time synchronization protocols 90.2 Overview 90.3 Relationship with other IEEE standards
52	90.4 Time Synchronization Service Interface (TSSI) 90.4.1 Introduction 90.4.1.1 Interlayer service interfaces
53	90.4.1.2 Responsibilities of TimeSync Client 90.4.2 TSSI 90.4.3 Detailed service specification 90.4.3.1 TS_TX.indication primitive
54	90.4.3.1.1 Semantics 90.4.3.1.2 Condition for generation
55	90.4.3.1.3 Effect of receipt 90.4.3.2 TS_RX.indication primitive 90.4.3.2.1 Semantics
56	90.4.3.2.2 Condition for generation 90.4.3.2.3 Effect of receipt 90.5 generic Reconciliation Sublayer (gRS)
57	90.5.1 TS_SFD_Detect_TX TS_DDMP_Detect_TX function
58	90.5.2 TS_SFD_Detect_RX TS_DDMP_Detect_RX function 90.5.3 Dynamic transmit path data delay
59	90.5.4 Dynamic receive path data delay
60	90.6 Overview of management features
62	90.7 Path dData delay measurement
64	90.7.1 FEC and PCS lane distribution functions
65	90.7.2 Alignment marker, codeword marker, and idle insertion/removal functions 90.7.3 Lane skew
66	90.8 Protocol implementation conformance statement (PICS) proforma for Clause 90, Ethernet support for time synchronization protocols 90.8.3 TSSI indication
68	90.8.4 DDMP selectionData delay reporting
69	Annex A (informative) Bibliography
70	Annex 90A (informative) Timestamping accuracy considerations 90A.1 Sub-nanosecond timestamping introduction 90A.2 Sub-nanosecond timestamping background 90A.3 Considerations for use of different data delay measurement points
72	90A.4 Considerations for multiple PCS lane functions 90A.5 Considerations for alignment marker/codeword marker and idle functions 90A.5.1 Example use of TX_NUM_BIT_CHANGE and PDPDD
73	90A.5.2 Example use of RX_NUM_BIT_CHANGE and PDPDD 90A.5.3 Considerations for implementations without TX_NUM_BIT_CHANGE and RX_NUM_BIT_CHANGE
74	90A.6 Considerations for transmit skew
75	90A.7 General method for dealing with repeating delay variation patterns
79	Back Cover

Additional information

Standard Title	IEEE Standard for Ethernet Amendment 6: Media Access Control (MAC) Service Interface and Management Parameters to Support Improved Precision Time Protocol (PTP) Timestamping Accuracy (Published)
Published Code	IEEE
Publication Date	2023
Pages Count	79

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