IEEE 896.1 1992
$62.29
IEEE Standard for Futurebus+(R) — Logical Protocol Specification
Published By | Publication Date | Number of Pages |
IEEE | 1992 | 208 |
Revision Standard – Inactive – Withdrawn. IEEE Std 896.1-1991 provides a set of tools with which to implement a Futurebus+architecture with performance and cost scalability over time, for multiple generations of single- and multiple-bus multiprocessor systems. Although this specification is principally intended for 64-bit address and data operation, a fully compatible 32-bit subset is provided, along with compatible extensions to support 128- and 256-bit data highways. Allocation of bus bandwidth to competing modules is provided by either a fast centralized arbiter, or a fully distributed, one or two pass, parallel contention arbiter. Bus allocation rules are provided to suit the needs of both real-time (priority based) and fairness (equal opportunity access based) configurations. Transmission of data over the multiplexed address/data highway is governed by one of two intercompatible transmission methods: (1) a technology-independent, compelled-protocol, supporting broadcast, broadcall, and transfer intervention (the minimum requirement for all Futurebus+systems), and (2) a configurable transfer-rate, source-synchronized protocol supporting only block transfers and source-synchronized broadcast for systems requiring the highest possible performance.
PDF Catalog
PDF Pages | PDF Title |
---|---|
12 | OUAD15 I aumu I QUAD13 I QUAD |
19 | 1 Introduction 1.1 Scope |
21 | Definitions and Structure Special Word Usage 2.2 Definitions |
26 | 2.3 Signal Conventions 2.4 Document Structure |
27 | 2.5 Futurebus+ Logo Bus Line Description Information Lines AddressEeturn Address |
28 | D[255 641* Data Lines CM[7 01* Command 2.6.1.4 CP* Command Parity ST[7 01* Status List of Bus Lines |
29 | CN2 01* Capability 2.6.1.7 BPI31 01* Bus Parity TGE7 01* Tag 2.6.1.9 TP* Tag Parity Synchronization Lines AS* Address Synchronization AK* Address Acknowledge AI* Address Acknowledge Inverse DS* Data Synchronization DK* Data Acknowledge 2.6.2.6 DI* Data Acknowledge Inverse 2.6.2.7 ET* End of Tenure Distributed Arbitration and Arbitrated Message Lines 2.6.3.1 AB17 01* Arbitration Bus 2.6.3.2 ABP* Arbitration Parity |
30 | A AR* Control Acquisition Synchronization ACCl 01* Arbitration Condition RE* Resenus Initialize Central Arbiter 2.6.5.1 PE* Preemption 2.6.5.2 GR* Grant 2.6.5.3 RQ[l 01* Request GA[4 Ol* Geographical Address Reference |
38 | Mnemonics |
39 | Bus Signaling Environment 3.1 Description Incident Wave Switching 3.1.2 Skew |
40 | 3.2 Specification 3.2.1 Skew 3.2.2 Glitch Filters Centralized Arbitration 4.1 Description |
41 | 4.1.1 Bus Lines Used for Centralized Arbitration 4.1.1.1 RQO* Request 4.1.1.2 RQ1* Request 4.1.1.3 GR* Grant 4.1.1.4 PE* Preempt Centralized Arbitration Operation |
42 | Central Arbiter Description 4.2 Specification Bus Arbitration Attributes Two-Competitor Centralized Arbitration |
43 | Bus Arbitration Signals 4.2.2.1 RQO* 4.2.2.2 RQ1* 4.2.2.3 GR* 4.2.2.4 PE* Distributed Arbitration and Arbitrated Messages 5.1 Description Arbitrated Messages-Central Arbiter |
44 | General Arbitrated Messages 5.1.1.2 Central Arbitrated Messages and Messages-Distributed Arbiter General Arbitrated Message Fields Central Arbitrated Message Fields |
45 | Distributed Arbitration Messages Distributed Arbitration Message Fields Distributed Arbitration Request Fields |
46 | 5.1.2.2.2 Round-Robin Field Geographical Address Field Deposing the Master Elect 5.1.2.4 Transaction Preemption |
47 | 5.1.2.5 Parking Bus Lines AP A AR* Control Acquisition Synchronization AC[1 01* Arbitration Condition 5.1.3.3 ABC7 03* Arbitration Bus 5.1.3.4 ABP* Arbitration Parity Arbitration Competition Logic |
48 | Arbitration Competition Settling Time Fig 5(a) Serial Implementation of Parallel Contention Logic Parallel Implementation of Parallel Contention Logic |
49 | Arbitration States Arbitration Competition Example |
50 | Arbitration Phases Control Acquisition States |
51 | Phase 0: Idle Phase Phase 1: Decision Phase Control Acquisition Sequence |
52 | Phase 2: Competition Phase Phase 3: Error Check Phase 4: Master Release |
53 | Phase 5: Tenurehlessage Transfer |
54 | Arbitration Examples Single-Pass Competition (Central or Distributed) Single-Pass Competition |
55 | Single-Pass Deposed (Distributed) Competition Single-Pass Deposed Competition |
56 | Distributed Arbitration Message Arbitration Message |
57 | Two-Pass Competition (Central or Distributed) C om p e ti ti on |
58 | Single-Pass Competition with Error Arbitrated Message Attributes-Central Arbiter Arbitrated Message Attributes-Distributed Arbiter Single-Pass Competition with Error |
59 | 5.2 Specification |
60 | Arbitration AttributecDistributed Arbiter |
61 | General Arbitration and Message Attributes |
63 | Arbitration Error Attributes Signal Definition 5.2.7.1 Arbitration Synchronization 5.2.7.1.1 AP* |
64 | 5.2.7.1.2 AQ* 5.2.7.1.3 AR* 5.2.7.2 Arbitration Condition 5.2.7.2.1 ACO* 5.2.7.2.2 AC1* 5.2.7.3 Arbitration Bus 5.2.7.3.1 AB7* 5.2.7.3.2 AB6* 5.2.7.3.3 AB5* 5.2.7.3.4 AB4* 5.2.7.3.5 AB3* 5.2.7.3.6 AB2* 5.2.7.3.7 AB1* 5.2.7.3.8 ABO* 5.2.7.3.9 ABP* Protocol Definition-Distributed Arbitration and Messages 5.2.8.1 Phase &Idle |
65 | 5.2.8.2 Phase 1-Decision 5.2.8.3 Phase Uompetition Phase 3-Error Check |
66 | Phase &Release Mastership Phase &Transfer Tenure Protocol Definition-central Arbiter Messages 5.2.9.1 Phase “Idle |
67 | 5.2.9.2 Phase 1-Decision 5.2.9.3 Phase Mompetition Phase &Error Check Phase &Release Mastership Phase &Transfer Tenure |
69 | Parallel Protocol 6.1 Description 6.1.1 Mastership 6.1.2 Transactions Bus Transaction Phases |
70 | Data Transfer Protocols 6.1.5 Broadcast Handshake |
71 | 6.1.8 Split Transactions 6.1.9 Locked Operations |
72 | 6.1.10 Lock Commands Mask and Swap Lock Command |
73 | Fetch and Add Lock Command Mask and Swap Lock Command |
74 | Compare and Swap Lock Command Fetch and Add Lock Command |
75 | Compare and Swap Lock Command |
76 | Busy Wait Extended Bus Width Extended Address |
78 | 6.1.16.4 Read Locked 6.1.16.5 Write Locked Address Only Locked 6.1.16.7 Read Partial 6.1.16.8 Write Partial Read Partial Locked 6.1.16.10 Write Partial Locked 6.1.16.11 Write Response 6.1.16.12 Read Response |
79 | 6.1.16.13 Write No Acknowledge 6.1.1 6.14 Read Invalid 6.1.16.15 Write Invalid 6.1.16.16 Copyback 6.1.16.17 Read Shared 6.1.1 6.1 8 Read Modified 6.1.16.19 Invalidate 6.1.1 6.20 Shared Response |
80 | 6.1.16.21 Modified Response Bus Signal Descriptions AS* Address Sync AK* Address Acknowledge AI* Address Acknowledge Inverse DS* Data Sync DK* Data Acknowledge |
81 | 6.1.17.6 DI* Data Acknowledge Inverse CM[7 01* Command Field CM7* Command 6.1.17.10.3 CAO* Capability Command Field Encoding |
82 | 6.1.17.7.2 CM6* Command CM5* Command Data Path Width |
83 | CM4* Command CM3* Command Transaction Command Encoding |
84 | CM2* Command CM1* Command CMO* Command 6.1.17.8 CP* Command Parity ST[7 01* Status Table 10 Locked Command Encoding |
85 | m’7* Status 6.1.17.9.2 ST6*Status6 ST5* Status 6.1.17.9.4 ST4*Status4 6.1.17.9.5 ST3*Status3 Table 11 Status Encoding |
86 | 6.1.17.9.6 ST2*Status2 6.1.17.9.7 ST1* Status1 6.1.17.9.8 STO*StatusO CAC2 Ol* Capability Table 12 Capability Encoding |
87 | 6.1.17.10.1 CA2* Capability 6.1.17.10.2 CAl* Capability 6.1.17.11 AD131 01* Address/Data/Lane DeselectIReturn Address |
88 | 6.1.17.12 AD[63 321* Address/Data Data 6.1.17.14 BFT31 01* Byte Parity |
89 | 6.1.17.15 TG[7 01* Tag 6.1.17.16 TP* Tag Parity 6.1.17.17 ET* End of Tenure 6.1.18 Bus Beats Single Slave Bus Beat |
90 | Multiple Slave Bus Beat Single Slave Bus Beat |
91 | 6.1.19 Transaction Examples 6.1.19.1 Address Only Transaction Multiple Slave Bus Beat |
92 | Address Only Transaction |
93 | 6.1.19.2 Compelled Read Compelled Read Transaction |
94 | Compelled Read BroadcastlBroadcall Compelled Read Transaction with Broadcall |
95 | Compelled Read Intervention Compelled Read Transaction with Intervention |
96 | Compelled Read Partial Compelled Read Partial Transaction |
97 | 6.1.19.6 Compelled Write Compelled Write Transaction |
98 | Compelled Write Broadcast Compelled Write Transaction with Broadcast |
99 | Compelled Write Partial Compelled Write Partial Transaction |
100 | 6.1.19.9 Transaction Error Transaction Error Timing |
101 | 6.1.19.10 Packet Data Phase Packet Data Phase Timing |
102 | 6.1.19.11 Single Packet Read Single Packet Read Transaction |
103 | 6.1.19.12 Single Packet Read Broadcast Single Packet Read Transaction with Broadcast |
104 | 6.1.19.13 Single Packet Read Intervention Single Packet Read Transaction with Intervention |
105 | 6.1.19.14 Single Packet Write Single Packet Write Transaction |
106 | 6.1.19.15 Multiple Packet Read Intervention Multiple Packet Read Transaction with Intervention |
107 | 6.1.19.16 Multiple Packet Read Intervention Queued Multiple Packet Read Transaction with Intervention and Queueing |
108 | 6.2 Specification 6.2.1 Attribute Definition Transfer Protocol Attributes Split Transaction Attributes |
109 | Address/Data Width Attributes Transaction Attributes |
113 | Locked OperationdAttributes |
114 | Data Transfer Length |
115 | Transaction Status Master Transaction Status |
116 | 6.2.1.7.2 Module Transaction Status |
118 | Transaction Timing Attributes |
121 | Definition |
122 | Inverse) (Command) 6.2.2.2 CM[7 01* CMO* (Command CM1* (Command CM2* (Command CM3* (Command CM4* (Command CM5* (Command CM6* (Command CM7* (Command CP* (Command Parity) 6.2.2.3 CN2 Ol* (Capability) CAO* (TS*) cAl* (CO*) |
123 | CA2* (SR*) 6.2.2.4 ST[7 01* (Status) STO* (TE*) ST1* (BS*/ED*) ST2* (SL*) ST3* (BC*) ST4* (TF*) ST5* (IV*) ST6* (BE*) |
124 | Synchronization Signals AS* (Address Sync) AK* (Address Acknowledge) AI* (Address Acknowledge Inverse) DS* (Data Sync) DK* (Data Acknowledge) ST7* (WT*) 6.2.2.5 Information Fields AD163 01* (AddresslData) |
127 | 6.2.2.5.3 BPI31 01* (Bus Parity) |
129 | TG[7 01* (Tag) TP* (Tag Parity) 6.2.2.5.6 ET* 6.2.3 Protocol Definition Master Connection Phase |
130 | Slave Connection Phase |
131 | Master Compelled Data Phase-First Odd Beat Slave Compelled Data Phase-First Odd Beat |
132 | Master Compelled Data Phase-First Even Beat Slave Compelled Data Phase-First Even Beat |
133 | Master Compelled Data Phase-Second Odd Beat Slave Compelled Data Phase-Second Odd Beat |
134 | Odd Beats Odd Beats Even Beats |
135 | Even Beats Master Packet Data Phase-Single Packet Mode |
136 | Slave Packet Data Phasedingle Packet Mode Odd Packet Queueing Odd Packet Queueing Even Packet Queueing |
137 | Even Packet Queueing Packet Transmission Tr an sm i s s i o n |
138 | Packet Data Protocol Master Disconnection Phase |
139 | Slave Disconnection Phase Transaction Timeout Recovery |
140 | 7 BusISystem Management 7.1 Description 7.1.1 Bus Control Power-up 7.1.1.2 System Reset Power-up Sequence Table 13 Event and RE* Relationships |
141 | Bus Initialize 7.1.1.4 Live Insertion 7.1.1.5 Live Withdrawal System Reset Sequence |
142 | Futurebus+ Control and Status Registers Module Capability Registers |
143 | Module Logical Capability Register |
144 | 7.1.2.2 Module Control Registers Competition Internal Delay Register Message Frame Size Register Packet Speed Register |
145 | Logical Common Control Register |
146 | Logical Module Control Register Bus Propogation Delay Register Competition Settling Time Register Transaction Time-out Register |
147 | 7.2 Specification Bus Control Attributes Message Passing Select Mask |
148 | RE* Reset Signal 7.2.3 Protocol Definition 7.2.3.1 Powerup 7.2.3.2 System Reset 7.2.3.3 Bus Initialize 7.2.3.4 Live Insertion |
149 | 7.2.3.5 Live Withdrawal Futurebus+ Control and Status Registers Module Capability Registers |
151 | 7.2.4.2 Module Control Registers |
153 | Logical Module Control Register Bus Propagation Delay Register Competition Settling Time Register |
154 | Transaction Timeout Register Message Passing Select Mask |
155 | Cache Coherence 8.1 Description Shared Memory Architecture |
156 | 8.1.1 Cache Attributes 8.1.2 Bus Snooping |
157 | Cache Coherence Using Connected Transactions 8.1.3.1 State Changes Invalid State Shared Unmodified State |
158 | 8.1.3.2 Read Miss Process Exclusive Unmodified State Exclusive Modified State |
159 | 8.1.3.3 Write Miss Process 8.1.3.4 Copyback Process 8.1.3.5 I/O Controller Optimization |
160 | 8.1.3.6 Examples Connected Cache Coherence Model |
161 | Location Write a Location |
162 | Cache Resident Fetch and Add |
163 | 8.1.4.1 Split Transactions 8.1.4.1.1 Shared Response 8.1.4.1.2 Modified Response |
164 | Single Outstanding Transaction Per Cache Line Requester and Responder Attributes 8.1.4.4 I/O Controller Optimization 8.1.4.5 Examples Location |
165 | Write a Location |
166 | Using Split Transactions to Delay Invalidation Completions |
167 | 8.1.5.1 Cache Agents 8.1.5.2 Memory Agents Split Response Architecture |
168 | 8.1.5.3 Split Transactions 8.1.5.3.1 Read Modified 8.1.5.3.2 Invalidate |
169 | 8.1.5.3.3 Write Invalid 8.1.5.3.4 Modified Response Requester and Responder Attributes Multiple Outstanding Transactions per Cache Line |
170 | 8.1.5.6 Examples |
171 | Multiple Bus Segment Split Transaction Example Model |
173 | Write a Location |
178 | Summary of Cache Coherence Commands and Status Illegal Attribute Combinations 8.1.7.1 Shared Unmodified 8.1.7.2 Exclusive Unmodified 8.1.7.3 Exclusive Modified Memory Line Modified 8.2 Specification 8.2.1 Module Attributes 8.2.2 Status Attributes |
181 | Cache Module Attributes Per Cache Line |
182 | Requester Attributes Per Cache Line Responder Attributes Per Cache Line |
183 | 8.2.6 Protocol Definition Cache Line Size 8.2.6.2 Cache Line Transfers |
184 | 9 Message Passing 9.1 Description Futurebus+ Message Passing |
185 | 9.1.1 Frame Level 9.1.1.1 Frame Structure Frame Notation |
186 | 64-Byte Frame Format |
187 | 9.1.1.2 Mailbox Structure 9.1.1.2.1 Request Mailbox 9.1.1.2.2 Response Mailbox |
188 | 9.1.1.2.3 Broadcast Transactions Message-Passing Mailboxes |
189 | Frame Level Protocol Broadcast Mailbox Select Attribute |
190 | 9.1.1.4 Message Priority Frame Level Example Linked List Message Passer |
191 | 9.1.2 Message Level Message Level Frame Structure Frame Type |
192 | Futurebus+ Message Level Frame Structure |
193 | Frame Size Message Identification Extended Header Message Size Frame Interval Sequence Number Exception Type Unacknowledged Event Frame |
194 | Acknowledged Event Frame Event Positive Acknowledge Frame Event Negative Acknowledge Frame Multiple Frame Message Request Frame Response Frame Response Frame Frame |
195 | Frame Frame Frame Multiple Frame Message Positive Acknowledge Frame |
196 | 9.1.2.2 Message Protocols Unacknowledged Single Frame Protocol Acknowledged Single Frame Protocol Ordered Multiple Frame Protocol Unacknowledged Single Frame Message Acknowledged Single Frame Message |
197 | Sequenced Multiple Frame Protocol Ordered Multiple Frame Message |
198 | 9.1.2.3 Request/Response Timeout Multiple Frame Message Timeout 9.1.2.5 Frame Ordering Sequenced Multiple Frame Message |
199 | Bus Tenure Time 9.2 Specification 9.2.1 Attribute Definition |
200 | Frame Format Specification Frame FormadNon-Futurebus+ Message Level Frame FormatiUnacknowledged Event Frame |
201 | Frame Format-Event Positive Acknowledge Frame |
203 | Response Frame Data Frame Data Frame |
204 | Ordered Frame Sequenced Frame |
205 | Acknowledge Frame Acknowledge Frame 9.2.3 Message Size 9.2.4 Frame Interval 9.2.5 Sequence Number |
206 | Exception Type Field 9.2.7 Protocol Definition Master Unacknowledged Single Frame Message Protocol Slave Unacknowledged Single Frame Message Protocol Slave Acknowledged Single Frame Message Protocol Master Ordered Multiple Frame Message Protocol |
207 | Master Sequenced Multiple Frame Message Protocol 9.2.7.7 Slave Multiple Frame Message Protocol |