IEEE 896.10 1997

$88.29

Standard for Futurebus+(R) Spaceborne Systems – Profile S

Published By	Publication Date	Number of Pages
IEEE	1997	217

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Description

New IEEE Standard – Inactive – Withdrawn. In the Futurebus+ series of standards, tools with which high-performance bus-based systems may be developed are provided. This architecture provides a wide range of performance scalability over both cost and time for multiple generations of single- and multiple-bus multiprocessor systems. This document, a companion standard to the ISO/IEC 10857: 1994 (ANSI/IEEE Std 896.1, 1994 Edition) Futurebus+(R) Logical Layer Specification, builds on the logical layer by adding requirements for a spaceborne profile. It is to this profile that products will claim conformance. Other specifications may be required in conjunction with this standard.

PDF Catalog

PDF Pages	PDF Title
1	Title Page
3	Introduction
4	Participants
7	CONTENTS
10	1. Overview 1.1 Scope 1.2 Applicability 1.3 Background to the standard
11	1.4 Structure of the standard 1.5 How to use this standard
12	1.6 Why use this standard
13	2. References 2.1 Referenced documents
14	2.2 Conflicting standards
15	3. Definitions 3.1 Special word usage 3.2 Bus line and signal conditions
16	3.3 Futurebus+ terminology
19	3.4 Conventions 3.5 Syntax
20	3.6 Futurebus+ logo
21	4. Profile S reference specification 4.1 Introduction
23	4.2 Target applications 4.3 Reference tables
27	4.4 Profile S interoperability
29	4.5 Conformance testing
30	5. Detailed specification, Futurebus+ logical layer 5.1 Arbitration 5.2 Parallel protocol
33	6. Utility Signals 6.1 Trigger 0 (TR0) and Trigger 1 (TR1) 6.2 Run (RUN) 6.3 Nuclear Event Detect (NED)
34	6.4 Power Failure Imminent (PFI*)
35	6.5 Power Normal (PN) 6.6 System Reset (SR) 6.7 Utility Spares (UPSP and UWSP)
36	7. Fault tolerance aspects of the parallel protocol and utility signals 7.1 Error detection
45	7.2 Error isolation, logging, and diagnostics
46	7.3 Error removal and recovery
52	7.4 Pinout summary
54	8. Serial Bus 8.1 Serial Bus physical layer
55	8.2 Serial Bus link layer 8.3 Serial Bus transaction layer
57	9. Bus/Node management and CSRs 9.1 Addressing 9.2 Byte-Lane wiring and byte ordering 9.3 CSRs
58	9.4 Futurebus+ CSRs
90	9.5 Unit space CSRs
98	9.6 Serial Bus management
99	9.7 Private space
100	9.8 Interrupts 9.9 Diagnostics and test 9.10 Monarch selection
101	10. Detailed specification, physical layer—SEM-E Stretch 10.1 Mechanical 10.2 Input/Output 10.3 Profile connector, power, and signal pin assignments
131	11. Detailed specification, Physical layer—10 SU 11.1 Mechanical 11.2 Input/Output 11.3 Profile connector, power, and signal pin assignments
168	12. Profile S electrical 12.1 Backplane characteristics and design requirements
169	12.2 Module electrical characteristics and design requirements
175	13. Profile S power 13.1 Module power
176	13.2 Host system power supplies
179	14. Profile S environmental specifications 14.1 System environmental requirements 14.2 Module environmental requirements
180	15. Recommended practices 15.1 Thermal considerations 15.2 Power consumption
181	15.3 Pinouts 15.4 Bus performance analysis
182	15.5 Bandwidth considerations
185	16. Profile S module selection criteria 16.1 Introduction 16.2 Profile S modules
186	16.3 Profile S systems
187	17. Alternate profile S module connector 17.1 Mechanical 17.2 Input/Output 17.3 Profile connector, power, and signal pin assignments
217	Annex A—Bibliography