IEEE 896.2 1992

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IEEE Standard Backplane Bus Specification for Multiprocessor Architectures: Futurebus+(R)

Published By	Publication Date	Number of Pages
IEEE	1992	222

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Description

New IEEE Standard – Inactive – Withdrawn. Futurebus+ standards provide systems developers a set of tools with which high-performance bus-based systems may be developed. This architecture provides a wide range of performance scalability over both cost and time for multiple generations of single- and multiple-bus multiprocessor systems. This document, a companion standard to IEEE Std. 896.1-1991, builds on the logical layer by adding requirements for physical layer instantiation. Material in this document includes specifications for node management, live insertion, and profiles. It is to these profiles that products will claim conformance. Other specifications that may be required in conjunction with this standard are the following: IEEE Std 896.1-1991; P896.3, Futurebus+ Recommended Practices; P1212.x, Control and Status Register Architectures; IEEE Std 1194.1-1991, Electrical Characteristics of Backplane Transceiver Logic (BTL) Interface Circuits; and IEEE Std 1301.x, Metric Equipment Practices for Microcomputers.

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PDF Pages	PDF Title
5	U BOU N D-H
7	I BIT FIELD I REQ I ACCESS IPOWER-UP1 SYSTEM I BUS
16	Table
17	In tr o ducti on 1.1 Scope Fig
18	1.2 References 1.2.1 Protocol Stack Specifications Control Fig
19	Definitions and Structure 2.1 Special Word Usage
20	2.2 Definitions
24	2.3 Signal Conventions 2.4 Numbering Conventions Signal Conventions
25	2.5 Futurebus+ Logo Numbering Conventions IEEE 896 Logo
26	Address Space 3.1.1.1 Memory Addresses
27	Futurebus+ Boards Modules and Nodes 32-bit CSR Addressing
28	3.1.1.3 Hybrid Addressing 32-bit CSR Addressing First CSR Address of Local Bus Node One
29	Byte Lane Mapping Hybrid Addressing
30	Base Functional Character Native Big Endian Node to Futurebus+ CSR Byte Lane Mapping Native Little Endian Node to Futurebus+ CSR Byte Lane Mapping
31	3.1.2.1 Resets 3.1.2.2 ROM Identification Reset (RE*) Operations Basic Node ROM Structure
32	3.1.2.3 Capability and Setup 3.1.2.4 Bus Control
33	3.1.2.5 Distributed Arbitration Timeout and Setup
34	3.1.2.7 Retry Node State Control
35	3.1.2.9 Standard Diagnostic Interface Table
36	Table
37	Optional Functional Character 3.1.3.1 Messages
38	3.1.3.2 Arbitrated Messages
39	3.1.3.3 Interrupts Comparison of Interrupt Registers
40	3.1.3.4 Packet Management 3.1.3.5 Clock Synchronization
44	3.1.3.6 Unit Access
45	Clock Synchronization
46	Futurebus+ CSR Specification 3.2.1 CSR Memory Space Specification
47	3.2.2 Core CSRs CSR Address Space Allocation
48	STATE-CLEAR and STATE-SET CSRs Core CSRs and Addresses
49	STATE-CLEAR and STATE-SET CSR Bit Descriptions
50	3.2.2.2 NODE-IDS CSR Fields in the STATE-CLEAR and STATE-SET CSRs Used by Futurebus+ NODE-IDS CSR Bit Descriptions
51	3.2.2.3 RESET-START CSR Format of the NODE-IDS CSR
52	Internal Indirect Address Space CSRs Format of the RESET-START CSR Format of the Internal INDIRECT-ADDRESS CSR Internal INDIRECT-ADDRESS CSR Bit Description
53	3.2.2.5 SPLIT-TIMEOUT CSR Format of the Internal INDIRECT-DATA CSR Internal INDIRECT-DATA CSR Bit Description SPLIT-TIMEOUT CSR Bit Description
54	Format of the SPLIT-TIMEOUT CSRs ARGUMENT CSRs Bit Description
55	3.2.2.7 TEST-START CSR Fig 14 (a) General Format of the ARGUMENT CSRs Extended Test Category Format of the Argument CSRs
56	TEST-START CSR Bit Descriptions
57	Format of the TEST-START CSR
58	TEST-STATUS CSR Bit Descriptions
60	Extended Units Address Space CSRs Format of the TEST-STATUS CSR
61	Format of the UNITS-BASE CSR Format of the UNITS-BOUND CSR UNITS-BASE CSR Bit Description UNITS-BOUND CSR Bit Description
62	Memory Unit Address Space CSRs Format of the MEMORY-BASE CSR MEMORY-BASE CSR Bit Description
63	INTERRUPT-TARGET and INTERRUPT-MASK CSRs Format of the MEMORY-BOUND CSR MEMORY-BOUND CSR Bit Description INTERRUPT-TARGET CSR Bit Description
64	CSRs for Clock Synchronization INTERRUPT-MASK CSR Bit Description CLOCK-VALUE CSR Bit Description
65	CLOCK-TICK-PERIOD CSR Bit Description CLOCK-STROBE-ARRIVED CSR Bit Description
67	Message Target CSRs 3.2.2.14 Error Symptom CSRs CLOCK-REFERENCE CSR Bit Description MESSAGE-REQUEST CSR Bit Description MESSAGE-RESPONSE CSR Bit Description
68	ERROR-HI CSR Bit Descriptions
70	ERROR-HI CSR Format (Most Significant Half) ERROR-HI CSR Format (Least Significant Half)
71	ERROR-LO CSR Bit Descriptions
72	Format of the ERROR-LO CSR
73	FAILING-ADDRESS CSR BYTE-LANE-IN-ERROR CSR DATA-HOLD CSR TAG-HOLD CSR
74	Futurebus+ Dependent CSR Area Fig 24 Format of the TAG-HOLD Register TIME-STAMP CSR
75	3.2.3.1 LOGICAL-COMMON-CONTROL CSR Futurebus+ Specific CSRs LOGICAL-COMMON-CONTROL CSR Bit Descriptions
76	Format of the LOGICAL-COMMON-CONTROL CSR
77	3.2.3.2 LOGICAL-MODULE-CONTROL CSR LOGICAL-MODULE-CONTROL CSR Bit Descriptions
79	3.2.3.3 BUS-PROPAGATION-DELAY CSR Format ofthe LOGICAL-MODULE-CONTROL CSR
80	3.2.3.4 COMPETITION-SETTLING-TIME CSR BUS-PROPAGATION-DELAY CSR Bit Descriptions Table 39 COMPETITION-SETTLING-TIME CSR Bit Descriptions
81	3.2.3.6 MESSAGE-PASSING-SELECT-MASK CSR Busy Retry CSRs MESSAGE-PASSING-SELECT-MASK CSR Bit Descriptions Table
82	Fig 27 BUSY-RETRY-COUNTER CSR BUSY-RETRY-COUNTER CSR Bit Descriptions Table
83	Error Retry CSRs BUSY-RETRY-DELAY CSR
84	ERROR-RETRY-COUNTER CSR ERROR-RETRY-COUNTER CSR Bit Descriptions Table ERROR-RETRY-DELAY CSR Bit Descriptions Table
85	Bus Specific ROM Entries ERROR-RETRY-DELAY CSR
86	Table 46 Node ROM Specified Locations
87	3.2.4.1 Bus Information Block 3.2.4.2 MODULE-LOGICAL-CAPABILITY Futurebus+ Required BUS INFORMATION BLOCK ROM Entries Table
88	MODULE-LOGICAL-CAPABILITY CSR Bit Descriptions Table
90	Fig 31 (a) MODULE-LOGICAL-CAPABILITY (Most Significant Half) MODULE-LOGICAL-CAPABILITY (Least Significant Half)
91	3.2.4.3 NODE-CAPABILITIES-EXT NODE-CAPABILITIES-EXT CSR Bit Descriptions Table
92	3.2.4.4 COMPETITION-INTERNAL-DELAY CSR Format of the NODE-CAPABILITIES-EXT CSR
93	3.2.4.5 PACKET-SPEED CSR 3.2.4.6 MESSAGE-FRAME-SIZE CSR Format of the COMPETITION-INTERNAL-DELAY CSR Format of the PACKET-SPEED CSR
94	Busy Retry Capability CSRs Error Retry Capability CSRs Format of the MESSAGE-FRAME-SIZE CSR
95	Core CSR Root Directory Table 50 (a) ROM Directory Entry Format Table 50 (b) Directory ï¬Key Typeï¬‚ Definitions Table 50 (c) Directory Entry Keys
97	3.2.5.1 MODULE-VENDOR-ID ROM Entry MODULE-SPEC-ID ROM Entry NODE-CAPABILITIES ROM Entry
98	NODE-CAPABILITIES CSR Bit Descriptions
99	MODULE-HW-VERSION ROM Entry Bus Visible Address RAM Format of the NODE-CAPABILITIES Entry
100	Format of the NODE-MEMORY-EXTENT Entry MEMORY-EXTENT Bit Descriptions
101	Vendor-Defined ROM Entries MODULE-VENDOR-DEPENDENT-INFO ROM Entry Initial Units Space Interrupts Format of the NODE-UNITS-EXTENT Entry UNITS-EXTENT Bit Descriptions
102	Distributed Arbitration Messages and General Arbitrated Messages
103	Live Insertion 4.1 Description 4.1.1 Introduction 4.1.2 General Considerations 4.1.3 Levels of Live Insertion
104	Level 1 Live Insertion and Withdrawal Level 2 Live Insertion and Withdrawal Level 3 Live Insertion and Withdrawal
105	4.1.4 Operator Facilities Live Insertion State Diagram
106	Live Insertion Module State Diagram Node Indicator Relationship to State
107	Conceptual Module Design
109	4.2 Specification 4.2.1 Definitions System Operation Requirements Functional Design of a Live Insertion Module
110	Live Insertion Power Requirements 4.2.4 Module Activation and Deactivation Live Insertion ESD Requirements 4.2.6 Live Insertion Electrical Requirements Level 1 Requirements Level 2 Requirements
111	Level 3 Requirements Futurebus+ Live Insertion Glyph Definition of SWAP Indicator Futurebus+ Live Insertion Glyph
112	5 Introduction to Application Environment Profiles Application Environment Profile (AEP) Description Futurebus+ Open Systems Protocol Stack
113	Minimum Requirements for AEPs (AEP Specification) AEP Terminology and Definitions Organization
114	Profile Content 5.2.3.1 Arbitration 5.2.3.2 Parallel Protocol
115	Timing Specification Global Timing Specifications Timing Specifications for (Arbitration Type) Arbitration Timing Specifications for the Arbitrated Message Bus Used for Messages Timing Specifications for the Parallel Protocol
116	CSRs Cache Coherence Message Passing Systems Configurations Physical Layer 5.2.4.1 Power Supply Specifications
117	Profile Electrical and Signaling Environment
118	5.2.4.3 Live Insertion 5.2.4.4 Mechanical
119	5.2.4.5 InpuVOutput 5.2.4.6 Connector and Pinout Assignment Environmental Standards Requirements
120	Application Environment Profile A 6.1 Reference Specification 6.1.1 Introduction Target Market and Applications 6.1.3 Terminology 6.1.4 Referenced Documents 6.1.5 Reference Tables 6.1.6 Profiles Interoperability
121	Profile A Logical Layer Referenced Specifications
123	Profile A Physical Layer Referenced Specifications
125	6.2 Detailed Specification Arbitration
126	Parallel Protocol 6.2.2.1 Transaction Types
127	6.2.2.2 Tag Bits 6.2.2.3 Serial Bus Busmode Management and CSRs 6.2.3.1 Addressing Byte-Lane Wiring and Byte Ordering 6.2.3.3 Interrupts 6.2.3.4 Diagnostics and Test
128	6.2.3.5 CSRs CSR Address Space Profile A Core CSRs
130	Profile A Specific CSRs
131	Cache Coherence Message Passing System Configuration Profile A ROM Registers
132	6.2.6.1 Monarch Selection Profile A Power 6.2.7.1 Module Power
134	6.2.8 Profile A Electrical 6.2.8.1 Signal Integrity Profile A Power Rails
135	Functional Electrical Requirements Live Insertion and Withdrawal
136	6.2.9.1 Alignment Live Insertion Power Live Insertion and Withdrawal Safety
137	6.2.10 Mechanical Specifications
138	View of Subrack/Backplane Relationship
139	Connector
140	View of Plug-in Module
141	Detail ï¬C ï¬‚ Alignment Pin Position on Front Panel and Subrack
142	Detail ï¬B ï¬‚ Front Panel Section
143	and Alignment Pin Position
144	Design Features
146	Heights X-Z View
147	Calculation of Maximum Component Heights
148	Profile A Front Panel Organization
150	EM1 Considerations Module Status State Diagram
151	EMI/RFI Shielding Locations and Interfacing Surfaces-Preferred
152	6.2.10.4 Injector/Ejector Mechanism EMI/RFI Shielding Locations and Interfacing Surfaces Alternative
153	Bus Connector Mechanical 6.2.11 Inputloutput Profile A Connector Power and Signal Pin Assignment Assignment
154	Signal Pin Assignment Connector Naming Conventions
155	Power Pin Assignment 6.2.12.4 Connector Keying Environmental Specifications and Other Standards Compliance
156	Connector B and X Pinouts for 64/32-Bit Address and Data Paths
157	Connector E Pinout for 128-Bit Data Path Extension
158	Connector E Pinout for 192 I/O
159	Connector E Pinout for 128-Bit Extension and 80 I/O
160	Subrack Air Flow and Thermal Considerations Profile A Power Connector Pin Assignment
161	6.2.13.2 Safety and EM1 Standards
162	Application Environment Profile B 7.1 Reference Specification 7.1.1 Introduction Target Market and Applications 7.1.3 Profile B Terminology 7.1.4 Referenced Documents 7.1.5 Reference Tables Profile B Logical Layer Referenced Specifications
164	Profile B Physical Layer Referenced Specifications
166	Multiple Profile Interoperability 7.2 Detailed Specification Arbitration 7.2.1.1 Central Arbitration
167	7.2.1.2 Distributed Arbitration Parallel Protocol 7.2.2.1 Transaction Types
168	7.2.2.2 Prohibited Operations
169	7.2.2.3 Timing Specifications Global Timing Specifications Timing Specifications for Central Arbitration
170	7.2.2.4 Tag Bits the Power Fail Timing Specifications for the Parallel Protocol
171	7.2.2.5 Serial Bus Busmode Management and CSRs 7.2.3.1 Addressing Byte Ordering 7.2.3.3 Interrupts 7.2.3.4 DMA and Test CSRs CSR Address Space
172	Profile B Core CSRs
173	Profile B Futurebus+ Specific CSRs
174	Caching and Cache Coherence Message Passing Profile B ROM Registers
175	System Configuration Profile B Power 7.2.7.1 Module Power 7.2.7.2 System Power Supplies
177	Profile B Power Rails Profile B Power Supply Sequencing
179	Profile B Electrical 7.2.8.1 Signal Integrity
180	Backplane Characteristics
181	Functional Electrical Requirements Module Signal Line Characteristics
183	Live Insertion and Withdrawal Level 1 Live Insertion
184	Level 2 Live Insertion 7.2.9.3 Alignment Live Insertion Power Live Insertion and Withdrawal Safety Mechanical
185	7.2.10.1 Subrack Mechanical Specifications
186	X-Y View of Subrack and Module Relationship
187	Design Features Installed Connector
188	Calculation of Maximum Component Heights
189	Y-Z View of Plug-in Unit
190	X-Y View of Plug-in Unit
191	Recommended Injector/Ejector Lever for Profile B
192	Heights X-Z View
194	Profile B Front Panel Organization Fig
195	Module Status State Diagram Fig
196	7.2.10.3 EM1 Considerations
197	EMI/RFI Shielding Locations and Interfacing Surfaces-Preferred Fig
198	7.2.10.4 Injector/Ejector Mechanism EMI/RFI Shielding Locations and Interfacing Surfaces-Alternative Fig
199	Bus Connector Mechanical Inputloutput Profile B Connector Power and Signal Pin Assignment Assignment
200	Signal Pin Assignment Connector Naming Conventions Fig
201	Connectors B and X Pinouts for 64/32-Bit Address and Data Paths Fig
202	Connector E Pinout for 128-Bit Extension and 80 1/0 Fig
203	Power Pin Assignment Profile B Power Connector Pin Assignment Fig
204	Environmental Specifications and Other Standards Compliance Subrack Air Flow and Thermal Considerations 7.2.13.2 Safety and EM1 Standards
205	Application Environment Profile F 8.1 Reference Specifications 8.1.1 Introduction Target Market and Applications 8.1.3 Profile F Terminology 8.1.4 IEEE Standards Referenced 8.1.5 Reference Tables
206	Profile F Logical Layer Referenced Specifications
207	Multiple Profile Interoperability 8.1.6.1 Profile A Interoperability Profile B Interoperability
208	8.2 Detailed Specification 8.2.1 Arbitration 8.2.2 Parallel Protocol
209	8.2.2.1 Transaction Types 8.2.2.2 Split Transactions 8.2.2.3 Locked Operations 8.2.2.4 Packet Data Transfers
210	8.2.2.5 Busy 8.2.2.6 Tag Bits 8.2.2.7 Serial Bus Retry Delay Times
211	8.2.3 Timing Specifications Global Timing Specifications
212	Timing Specifications for Central Arbitration Timing Specifications for Arbited Messages Timing Specifications for the Parallel Protocol
214	Budsystem Management and CSRs 8.2.4.1 Addressing 8.2.4.2 Byte-Lane Wiring and Byte Ordering 8.2.4.3 Interrupts 8.2.4.4 Diagnostics and Test 8.2.4.5 CSRs Profile F Core CSRs
216	Profile F Futurebus+ Specific CSRs Profile F ROM CSRs
217	Caching and Cache Coherence Message Passing System Configuration Monarch Selection Description
218	Monarch Selection Attribute Specification Power Supply Electrical Wire-OR Glitch Filters Live Insertion and Withdrawal Mechanical InputlOutput Connector Power and Signal Pin Assignment Non-Central Arbiter Slot 8.2.13.2 Central Arbiter Slot
219	Connector E Pinout for Central Arbiter Slot Fig
220	Environmental Specification for a Module-Based Central Arbiter 8.3.1 Backplane Requirements 8.3.1.1 Wiring Geographical Address Assignment Backplane Delay Encoding on BD[2 01*

Additional information

Standard Title	IEEE Standard Backplane Bus Specification for Multiprocessor Architectures: Futurebus+(R)
Published Code	IEEE
Publication Date	1992
Pages Count	222

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IEEE 896.2 1992

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