IEEE 960 1986:1985 Edition

$23.29

Standard for FASTBUS Modular High-Speed Data Acquisition and Control System

Published By	Publication Date	Number of Pages
IEEE	1985	217

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Description

New IEEE Standard – Inactive – Superseded. Mechanical, signal, electrical, and protocol specifications are given for a modular data bus system, which, while allowing equipment designers a wide choice of solutions, ensure compatibility of all designs that obey the mandatory parts of the specification. This standard applies to systems consisting of modular electronic instrument units that process or transfer data or signals, normally in association with computers or other automatic data processors.

PDF Catalog

PDF Pages	PDF Title
20	Introduction and General Information I Typical Power Supplies I Typical Power Supplies 1.1 High Efficiency Power Supply 1.1.1 General 1.1.2 Efficiency 1.1.3 Ambient Temperature Range 1.1.4 Input
21	1.1.5 Output 1.1.6 Remote Sense 1.1.7 Regulation and Stability 1.1.8 Temperature Coefficient Basic FASTBUS Elements
22	1.1.9 Noise and Ripple 1.1.10 Recovery Time and Turn-on and Turn-off Transients 1.1.1 1 Conducted and Radiated Noise 1.1.12 Output Terminals 1.1.13 Voltage Adjustment Controls
23	1.1.14 Protection 1.1.15 Monitoring 1.1.16 Margining 1.1.17 External Breaker Trip Control Example of FASTBUS System Topology
24	1.1.18 Switched ac Outlet 1.1.19 Front Panel 1.1.20 Rack Mounting I 1.2 1 Cooling 1.2 Low-Noise Power Supply 1.2.1 General 1.2.2 Efficiency 1.2.3 Ambient Temperature Range 1.2.4 Input 1.2.5 Output 1.2.6 Remote Sense 1.2.7 Regulation and Stability
25	1.2.8 Temperature Coefficient 1.2.9 Noise and Ripple 1.2.10 Recovery Time and Turn-on and Turn-off Transients 1.2.11 Conducted and Radiated Noise 1.2.12 Output Terminals 1.2.13 Voltage Aaustment Controls 1.2.14 Protection 1.2.15 Monitoring 1.2.16 Margining 1.2.17 External Breaker Trip Control 1.2.18 Switched ac Outlet 1.2.19 Front Panel 1.2.20 Rack Mounting 1.2.21 Cooling FASTBUS Signals
26	Basic Handshake Read Operation (as seen by Master)
29	Write Block Transfer (as seen by Master)
30	Address-Locked Operation Read-Modify-Write (as seen by Master)
35	Conventions Definitions Abbreviations and Symbols Signal Characteristics 12.1 Signal Levels l
47	Signals Signal Lines and Pins Modules l 13 Modules l Module Circuit Board l
49	3.3.17 AI Arbitration Request Inhibit CA. ANC)
50	3.3.18 SR Service Request A. Master or Slave) 3.3.19 RB Reset Bus A. Master or Master via SIs) 3.3.20 BH Bus Halted C. ANC) 3.3.21 GA Geographical Address F. Hardwired) 3.3.22 TP T Pins I. Slave) 3.3.23 DL DR Daisy Chain I. Master or Slave) 3.3.24 TX RX Serial Network Lines A. Master or Slave)
51	3.3.25 TR Terminated Restricted Use Lines 3.3.26 UR Unterminated Restricted Use Lines Other Lines and Pins 3.4 Bus Loading Voltage and Current Limits for Signal Lines and F Pins 13.2 Connectors l
52	Crates l
53	4.1 Logical Addressing
55	Geographical Address Formats
59	Other Backplane Items
62	Sparse Data Scan and Pattern Select Operation
63	FASTBUS Operations: Timing Sequences and Responses Power l FASTBUS Operations: Timing Sequences and Responses 5.1 General Master/Slave Timing Requirements Handshaked Cycle Timing Sequence
64	Master Signal Timing Requirements Tracing the Route Taken by an Operation 5.1.8 SS=4 at Address Time – Reserved SS=5 at Address Time – Reserved 5.1.11 SS=7 at Address Time – Invalid IA Accepted Time-out at Data Time
65	Slave Status Responses 5.3.1 SS=O-Valid Action 5.3.2 SS=l-Busy SS=2 -End of Block 5.3.4 SS=3 – User Defined 5.3.5 SS = 4 – Reserved 5.3.6 SS=5 -Resewed SS=6 -Data Error (Reject) SS=7 -Data Error (Accept)
66	Use of Wait (WT) Host Response to Error Messages Errors in Transfers to or from FIFOs and 1/0 Ports 5.5.1 Introduction
67	5.2 Primary Address Cycles Protective Buffers for Read Operations Protective Buffers for Write Operations
68	Logical Address Cycle
71	Master Sequence for Asserting AS Slave Response to AS(u) Address Type Specification
72	Master Response to AK(u)
73	Address Time SS Response with AK(u)
76	Master Sequence for Asserting DS Block Transfer Write
77	MS Interpretation for Data Cycles
78	Discussion of Slave Status Responses Slave Data Time SS Responses With DK(t) Slave SS Responses and Actions at DK(t)
80	Master Response to DK(t) Use of Reset Bus (RB)
81	5.4.2 Device Response to RB Device Response to POWER ON
82	Bus Arbitration Cable Segment l 6 Bus Arbitration 16.2 Cable Segment Connectors and Contact Assignments
83	Bus Line Usage for the Arbitration Process FASTBUS Arbitration Lines
84	6.2 The Arbitration Process
85	Arbitration Control Logic in a Master Arbitration Logic in a Master
86	Arbitration for Two Masters Showing Worst-case Delays
87	Arbitration for Three Masters Showing Worst-case Delays
88	6.3 Arbitration Rules AR 6.3.2 ATC Assertion and Release of AI
89	ATC Assertion and Release of AG Master Assertion and Release of AL
90	Master Assertion and Release of GK 6.4 System-Wide Arbitration
92	Ancillary Logic on a Segment Ancillary Logic on a Segment Arbitration Timing Control (ATC) 7.1.1 ATC Generation of AI 7.1.2 ATC Generation of AG
93	7.2 Geographical Address Control
94	System Handshake Generation (Broadcast)
95	7.4 Run/Halt Control and Bus Halted
96	7.5 Terminators 7.6 Ancillary Logic for Crate Segments
97	7.7 Ancillary Logic for Cable Segments
98	Control and Status Register Space Control and Status Register Space
99	Selective Set and Clear Functions
100	8.2 Normal CSR Space Allocation 8.3 CSR Register
102	8.3.1 Device IDS and Their Allocation 8.3.2 Control and Status Bit Allocation CSR Register 0 Bit Assignments
104	8.4 CSR Register 8.5 CSR Register
106	8.6 CSR Register
107	CSR Register CSR Register CSR Register
108	CSR Register CSR Register CSR Register 9 and CSR Registers ICh to 1Fh
109	CSR Registers Ah to Fh CSR Registers 20h to 3Fh 8.15 CSR Registers 70h to 81h
110	CSR Registers AOh to AFh BOh to BFh and COh to CFh CSR Registers 8000 OOOOh to BFFF FFFFh Parameter Space
112	Clearing of CSR Bits
113	Interrupts 9 Interrupts 9.1 Interrupt Operation
114	9.2 The Service Request Line
117	Near- and Far-side Concept for the SI
119	10.3 Contention for Use of an SI
123	10.5.2 CSR#l Far-side Arbitration Level 10.5.3 CSR#8 Near-side Arbitration Level 10.5.4 CSR#9 Timer Control Register
124	10.5.5 CSR#40h Route Table Address Register 10.5.6 CSR#4lh Route Table Data Register 10.5.7 CSR#42h Near-side Geographical Address
128	10.7.4 Negative Responses
129	Modification of Geographical and Broadcast Addresses
134	Block and Pipelined Transfers
140	13 Module Outline
141	13.l(a Module Circuit Board Outline
142	13.1 Module Circuit Board Details
143	Grounding Area For Static Charge Discharge 13.2.1 Segment Connector
145	Two-Row Module Auxiliary Connector Connector
147	13.2.3 Other Connectors Segment and Auxiliary Connector Contact Designations 13.3 Temperature Considerations and Power Dissipation 13.3.1 Die and Module Temperatures
148	Corresponding Circuit Board Footprints
149	13.4 Front Panel Module Front Panel in Relation to Module Circuit Board
150	13.7 Transients
152	14.2(a Backplane Pin Details
154	14.2(c Connector Guides
156	14.2.l(a Backplane Daisy Chain Wiring (viewed from front of crate) crate)
162	Cable Segment
165	Requirements for Various Implementations Requirements for Various Implementations A.l ECL Implementation A.l.l ECL Connections and Signal Level Details
167	ECL Timing Details A.1.3 Retry Period A.1.4 Response Times A.1.5 Terminators A.l.l Typical ECL Driver-Receiver Layout
169	GA Logic Generating Circuit Requirements A.1.7 Differential Die Temperatures A.1.8 Module Distribution in Crate Segments
173	Electrical Specification for Cable Segment C.l C.2 ECL Cable Segment Implementation
174	C Cable Segment Logic States
175	C.l(a Schematic Diagram of Cable Segment Driver C.l(b Example of Cable Segment Driver
176	Implementation Examples of Master Requirements Implementation Examples of Master Requirements Master Arbitration Circuitry D.1 D.l Example of Arbitration Logic
177	FASTBUS Segment Interconnect TypeS-1 FASTBUS Segment Interconnect TypeS-1 General Features of Segment Interconnect TypeS-1 E.lS-1 E.l.l Type
178	E.1.2 Format E.1.3 Cable Segment E.1.4 Group Address Field E.1.5 Route Table Implementation
179	CSR#O ID, Status and Control E.1.6 E.1.7 NTA Register Front Panel Features