IEEE IEC 61523 4 2015
$146.25
IEEE/IEC International Standard – Design and Verification of Low-Power Integrated Circuits
| Published By | Publication Date | Number of Pages |
| IEEE | 2015 | 351 |
Adoption Standard – Active. A method is provided for specifying power intent for an electronic design, for use in verification of the structure and behavior of the design in the context of a given power management architecture, and for driving implementation of that power management architecture. The method supports incremental refinement of power intent specifications required for IP-based design flows.
PDF Catalog
| PDF Pages | PDF Title |
|---|---|
| 1 | IEC 61523-4 (IEEE Std 1801-2013) Front Cover |
| 4 | Contents |
| 12 | Introduction |
| 16 | Important Notice 1. Overview |
| 18 | 1.4 Use of color in this standard 1.5 Contents of this standard |
| 19 | 2. Normative references 3. Definitions, acronyms, and abbreviations 3.1 Definitions |
| 24 | 3.2 Acronyms and abbreviations |
| 26 | 4. UPF concepts 4.1 Design structure 4.1.1 Transistors 4.1.2 Standard cells 4.1.3 Hard macros 4.2 Design representation 4.2.1 Models |
| 27 | 4.2.2 Netlist 4.2.3 Behavioral models 4.2.4 HDL scopes 4.2.5 Design hierarchy |
| 28 | 4.2.6 Logic hierarchy 4.2.7 Hierarchy navigation |
| 29 | 4.2.8 Ports and nets 4.2.9 Connecting nets to ports 4.3 Power architecture |
| 30 | 4.3.1 Power domains 4.3.2 Drivers, receivers, sources, and sinks |
| 31 | 4.3.3 Isolation and level-shifting |
| 32 | 4.3.4 State retention 4.4 Power distribution |
| 33 | 4.4.1 Supply network elements |
| 34 | 4.4.2 Supply network construction |
| 36 | 4.4.3 Supply equivalence |
| 38 | 4.5 Power management 4.5.1 Related supplies 4.5.2 Driver and receiver supplies |
| 39 | 4.5.3 Logic sources and sinks 4.5.4 Power-management requirements |
| 40 | 4.5.5 Power-management strategies 4.5.6 Power-management implementation |
| 41 | 4.5.7 Power control logic 4.6 Power states 4.6.1 Power state of a supply port or supply net 4.6.2 Power state of a supply set |
| 42 | 4.6.3 Predefined supply set power states 4.6.4 Power states of power domains |
| 43 | 4.6.5 Power states of systems and subsystems 4.6.6 Incremental refinement of power states |
| 44 | 4.7 Simstates |
| 45 | 4.8 Successive refinement |
| 46 | 4.9 Tool flow |
| 47 | 4.10 File structure |
| 48 | 5. Language basics 5.1 UPF is Tcl 5.2 Conventions used |
| 49 | 5.3 Lexical elements |
| 50 | 5.3.1 Identifiers 5.3.2 Keywords and reserved words 5.3.3 Names |
| 52 | 5.3.4 Lists and strings 5.3.5 Special characters 5.4 Boolean expressions |
| 54 | 5.5 Object declaration |
| 55 | 5.6 Attributes of objects |
| 58 | 5.7 Power state name spaces |
| 59 | 5.8 Precedence |
| 60 | 5.9 Generic UPF command semantics 5.10 effective_element_list semantics |
| 61 | 5.10.1 Transitive TRUE |
| 62 | 5.10.2 Result |
| 63 | 5.11 Command refinement |
| 64 | 5.12 Error handling |
| 65 | 5.12.1 errorCode 5.12.2 errorInfo 5.13 Units |
| 66 | 6. Power intent commands 6.1 Categories 6.2 add_domain_elements [deprecated] |
| 67 | 6.3 add_port_state [legacy] 6.4 add_power_state |
| 72 | 6.5 add_pst_state [legacy] |
| 73 | 6.6 apply_power_model |
| 74 | 6.7 associate_supply_set |
| 75 | 6.8 begin_power_model |
| 76 | 6.9 bind_checker |
| 78 | 6.10 connect_logic_net |
| 79 | 6.11 connect_supply_net |
| 80 | 6.12 connect_supply_set |
| 82 | 6.13 create_composite_domain |
| 83 | 6.14 create_hdl2upf_vct |
| 84 | 6.15 create_logic_net |
| 85 | 6.16 create_logic_port |
| 86 | 6.17 create_power_domain |
| 89 | 6.18 create_power_switch |
| 95 | 6.19 create_pst [legacy] 6.20 create_supply_net |
| 96 | 6.20.1 Supply net resolution 6.20.2 Resolutions methods |
| 97 | 6.20.3 Supply nets defined in HDL |
| 98 | 6.21 create_supply_port |
| 99 | 6.22 create_supply_set |
| 100 | 6.22.1 Referencing supply set functions 6.22.2 Implicit supply net 6.23 create_upf2hdl_vct |
| 101 | 6.24 describe_state_transition |
| 102 | 6.25 end_power_model |
| 103 | 6.26 find_objects |
| 104 | 6.26.1 Pattern matching and wildcarding 6.26.2 Wildcarding examples |
| 105 | 6.27 load_simstate_behavior |
| 106 | 6.28 load_upf |
| 107 | 6.29 load_upf_protected |
| 108 | 6.30 map_isolation_cell [deprecated] 6.31 map_level_shifter_cell [deprecated] 6.32 map_power_switch |
| 109 | 6.33 map_retention_cell |
| 112 | 6.34 merge_power_domains [deprecated] |
| 113 | 6.35 name_format |
| 114 | 6.36 save_upf |
| 115 | 6.37 set_design_attributes |
| 116 | 6.38 set_design_top 6.39 set_domain_supply_net [legacy] |
| 117 | 6.40 set_equivalent |
| 119 | 6.41 set_isolation |
| 125 | 6.42 set_isolation_control [deprecated] |
| 126 | 6.43 set_level_shifter |
| 131 | 6.44 set_partial_on_translation 6.45 set_pin_related_supply [deprecated] |
| 132 | 6.46 set_port_attributes |
| 136 | 6.47 set_power_switch [deprecated] 6.48 set_repeater |
| 139 | 6.49 set_retention |
| 143 | 6.50 set_retention_control [deprecated] 6.51 set_retention_elements |
| 144 | 6.52 set_scope |
| 145 | 6.53 set_simstate_behavior |
| 146 | 6.54 upf_version |
| 147 | 6.55 use_interface_cell |
| 150 | 7. Power management cell commands 7.1 Introduction |
| 151 | 7.2 define_always_on_cell |
| 152 | 7.3 define_diode_clamp |
| 153 | 7.4 define_isolation_cell |
| 156 | 7.5 define_level_shifter_cell |
| 160 | 7.6 define_power_switch_cell |
| 162 | 7.7 define_retention_cell |
| 165 | 8. UPF processing 8.1 Overview 8.2 Data requirements 8.3 Processing phases |
| 166 | 8.3.1 Phase 1—read and resolve UPF specification 8.3.2 Phase 2—build power intent model |
| 167 | 8.3.3 Phase 3—recognize implemented power intent |
| 168 | 8.3.4 Phase 4—apply power intent model to design 8.4 Error checking |
| 169 | 9. Simulation semantics 9.1 Supply network creation |
| 170 | 9.2 Supply network simulation 9.2.1 Supply network initialization |
| 171 | 9.2.2 Power-switch evaluation |
| 172 | 9.2.3 Supply network evaluation 9.3 Power state simulation 9.3.1 Power state control |
| 173 | 9.3.2 Power state determination |
| 174 | 9.4 Simstate simulation |
| 175 | 9.4.1 NORMAL 9.4.2 CORRUPT 9.4.3 CORRUPT_ON_ACTIVITY 9.4.4 CORRUPT_ON_CHANGE |
| 176 | 9.4.5 CORRUPT_STATE_ON_CHANGE 9.4.6 CORRUPT_STATE_ON_ACTIVITY 9.4.7 NOT_NORMAL 9.5 Transitioning from one simstate state to another 9.5.1 Any state transition to CORRUPT |
| 177 | 9.5.2 Any state transition to CORRUPT_ON_ACTIVITY 9.5.3 Any state transition to CORRUPT_ON_CHANGE 9.5.4 Any state transition to CORRUPT_STATE_ON_CHANGE 9.5.5 Any state transition to CORRUPT_STATE_ON_ACTIVITY 9.5.6 Any state transition to NORMAL 9.5.7 Any state transition to NOT_NORMAL 9.6 Simulation of retention |
| 178 | 9.6.1 Retention corruption summary |
| 179 | 9.6.2 Retention modeling for different retention styles |
| 183 | 9.7 Simulation of isolation 9.8 Simulation of level-shifting 9.9 Simulation of repeater |
| 184 | Annex A (informative) Bibliography |
| 185 | Annex B (normative) HDL package UPF B.1 Supply net logic type values B.2 Path names B.3 VHDL UPF package |
| 190 | B.4 SystemVerilog UPF package |
| 197 | Annex C (normative) Queries |
| 198 | C.1 query_upf |
| 200 | C.2 query_associate_supply_set |
| 201 | C.3 query_bind_checker |
| 202 | C.4 query_cell_instances C.5 query_cell_mapped |
| 203 | C.6 query_composite_domain |
| 204 | C.7 query_design_attributes |
| 205 | C.8 query_hdl2upf_vct |
| 206 | C.9 query_isolation |
| 207 | C.10 query_isolation_control [deprecated] |
| 208 | C.11 query_level_shifter |
| 209 | C.12 query_map_isolation_cell [deprecated] C.13 query_map_level_shifter_cell [deprecated] |
| 210 | C.14 query_map_power_switch |
| 211 | C.15 query_map_retention_cell |
| 212 | C.16 query_name_format |
| 213 | C.17 query_net_ports C.18 query_partial_on_translation |
| 214 | C.19 query_pin_related_supply [deprecated] C.20 query_port_attributes |
| 215 | C.21 query_port_direction C.22 query_port_net |
| 216 | C.23 query_port_state |
| 217 | C.24 query_power_domain |
| 218 | C.25 query_power_domain_element C.26 query_power_state |
| 219 | C.27 query_power_switch |
| 221 | C.28 query_pst [legacy] |
| 222 | C.29 query_pst_state [legacy] |
| 223 | C.30 query_retention |
| 224 | C.31 query_retention_control [deprecated] C.32 query_retention_elements |
| 225 | C.33 query_simstate_behavior |
| 227 | C.34 query_state_transition |
| 228 | C.35 query_supply_net |
| 229 | C.36 query_supply_port |
| 230 | C.37 query_supply_set |
| 231 | C.38 query_upf2hdl_vct |
| 232 | C.39 query_use_interface_cell |
| 234 | Annex D (informative) Replacing deprecated and legacy commands and options D.1 Deprecated and legacy constructs |
| 237 | D.2 Recommendations for replacing deprecated and legacy constructs |
| 242 | Annex E (informative) Low-power design methodology E.1 Design, implementation, and verification flow for a soft IP |
| 244 | E.2 RTL design stage |
| 254 | E.3 Logic implementation |
| 258 | E.4 Physical implementation |
| 262 | E.5 SoC integration flow E.6 How to create a configuration UPF |
| 267 | Annex F (normative) Value conversion tables F.1 VHDL_SL2UPF F.2 UPF2VHDL_SL F.3 VHDL_SL2UPF_GNDZERO |
| 268 | F.4 UPF_GNDZERO2VHDL_SL F.5 SV_LOGIC2UPF F.6 UPF2SV_LOGIC F.7 SV_LOGIC2UPF_GNDZERO F.8 UPF_GNDZERO2SV_LOGIC |
| 269 | F.9 VHDL_TIED_HI F.10 SV_TIED_HI F.11 VHDL_TIED_LO F.12 SV_TIED_LO |
| 270 | Annex G (normative) Supporting hard IP G.1 Attributing feedthrough ports of hard IP |
| 271 | G.2 Attributing unconnected ports of hard IP |
| 273 | Annex H (normative) UPF power-management commands semantics and Liberty mappings H.1 Introduction H.2 define_always_on_cell |
| 275 | H.3 define_diode_clamp |
| 276 | H.4 define_isolation_cell |
| 279 | H.5 define_level_shifter_cell |
| 282 | H.6 define_power_switch_cell |
| 284 | H.7 define_retention_cell |
| 288 | Annex I (informative) Power-management cell modeling examples I.1 Modeling always-on cells |
| 291 | I.2 Modeling cells with internal diodes |
| 292 | I.3 Modeling isolation cells |
| 300 | I.4 Modeling level-shifters |
| 308 | I.5 Modeling power-switch cells |
| 312 | I.6 Modeling state retention cells |
| 318 | Annex J (normative) Switching Activity Interchange Format |
| 319 | J.1 Syntactic conventions |
| 320 | J.2 Lexical conventions |
| 322 | J.3 Backward SAIF file |
| 337 | J.4 Library forward SAIF file |
| 344 | J.5 RTL forward SAIF file |
| 348 | Annex K (informative) IEEE List of Participants |
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