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IEEE IEC 61691 1 1 2004

$166.29

IEC 61691-1-1 Ed.1 (IEEE Std 1076(TM)-2002): Behavioural Languages – Part 1-1: VHDL Language Reference Manual

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IEEE 2004 300
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New IEEE Standard – Active. Adoption of IEEE Std 1076-2002. VHSIC Hardware Description Language (VHDL) is defined. VHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. Its primary audiences are the implementors of tools supporting the language and the advanced users of the language.

PDF Catalog

PDF Pages PDF Title
4 Contents
7 Foreword
11 IEEE Introduction
12 0. Overview of this standard
0.1 Intent and scope of this standard
0.2 Structure and terminology of this standard
15 1. Design entities and configurations
1.1 Entity declarations
19 1.2 Architecture bodies
22 1.3 Configuration declarations
28 2. Subprograms and packages
2.1 Subprogram declarations
31 2.2 Subprogram bodies
34 2.3 Subprogram overloading
36 2.4 Resolution functions
37 2.5 Package declarations
38 2.6 Package bodies
40 2.7 Conformance rules
41 3. Types
42 3.1 Scalar types
48 3.2 Composite types
53 3.3 Access types
56 3.4 File types
58 3.5 Protected types
62 4. Declarations
4.1 Type declarations
63 4.2 Subtype declarations
64 4.3 Objects
78 4.4 Attribute declarations
79 4.5 Component declarations
4.6 Group template declarations
80 4.7 Group declarations
82 5. Specifications
5.1 Attribute specification
84 5.2 Configuration specification
92 5.3 Disconnection specification
95 6. Names
6.1 Names
96 6.2 Simple names
97 6.3 Selected names
99 6.4 Indexed names
100 6.5 Slice names
6.6 Attribute names
102 7. Expressions
7.1 Expressions
103 7.2 Operators
111 7.3 Operands
118 7.4 Static expressions
120 7.5 Universal expressions
122 8. Sequential statements
8.1 Wait statement
124 8.2 Assertion statement
125 8.3 Report statement
8.4 Signal assignment statement
130 8.5 Variable assignment statement
131 8.6 Procedure call statement
132 8.7 If statement
8.8 Case statement
133 8.9 Loop statement
134 8.10 Next statement
135 8.11 Exit statement
8.12 Return statement
8.13 Null statement
137 9. Concurrent statements
9.1 Block statement
138 9.2 Process statement
139 9.3 Concurrent procedure call statements
140 9.4 Concurrent assertion statements
141 9.5 Concurrent signal assignment statements
146 9.6 Component instantiation statements
152 9.7 Generate statements
153 10. Scope and visibility
10.1 Declarative region
154 10.2 Scope of declarations
155 10.3 Visibility
158 10.4 Use clauses
159 10.5 The context of overload resolution
160 11. Design units and their analysis
11.1 Design units
11.2 Design libraries
161 11.3 Context clauses
162 11.4 Order of analysis
163 12. Elaboration and execution
12.1 Elaboration of a design hierarchy
165 12.2 Elaboration of a block header
166 12.3 Elaboration of a declarative part
170 12.4 Elaboration of a statement part
173 12.5 Dynamic elaboration
12.6 Execution of a model
180 13. Lexical elements
13.1 Character set
183 13.2 Lexical elements, separators, and delimiters
184 13.3 Identifiers
13.4 Abstract literals
186 13.5 Character literals
13.6 String literals
187 13.7 Bit string literals
188 13.8 Comments
189 13.9 Reserved words
190 13.10 Allowable replacements of characters
191 14. Predefined language environment
14.1 Predefined attributes
205 14.2 Package STANDARD
212 14.3 Package TEXTIO
217 Annex A (informative)
Syntax summary
236 Annex B (informative)
Glossary
255 Annex C (informative) Potentially nonportable constructs
256 Annex D (informative)
Changes from IEEE Std 1076,2000 Edition
257 Annex E (informative)
Features under consideration for removal
258 Annex F (informative)
Bibliography
259 Annex G (informative) List of participants
IEEE IEC 61691 1 1 2004
$166.29