IEEE IEC 62142 2005:2002 Edition

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IEC 62142 Ed. 1 (IEEE Std 1364.1(TM)-2002): Standard for Verilog(R) Register Transfer Level Synthesis

Published By	Publication Date	Number of Pages
IEEE	2002	116

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Description

New IEEE Standard – Active. Replaces IEEE Std 1364.1-2002/ Dual logo standard To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364.

PDF Catalog

PDF Pages	PDF Title
1	Front Cover
4	CONTENTS
6	FOREWORD
9	IEEE Introduction
10	1. Overview 1.1 Scope 1.2 Compliance to this standard
11	1.3 Terminology 1.4 Conventions 1.5 Contents of this standard
12	1.6 Examples 2. References 3. Definitions
13	4. Verification methodology
14	4.1 Combinational logic verification 4.2 Sequential logic verification
15	5. Modeling hardware elements 5.1 Modeling combinational logic
16	5.2 Modeling edge-sensitive sequential logic
19	5.3 Modeling level-sensitive storage devices
20	5.4 Modeling three-state drivers
22	5.5 Support for values x and z 5.6 Modeling read-only memories (ROM)
24	5.7 Modeling random access memories (RAM)
25	6. Pragmas 6.1 Synthesis attributes
36	6.2 Compiler directives and implicit-synthesis defined macros
37	6.3 Deprecated features
38	7. Syntax 7.1 Lexical conventions
43	7.2 Data types
48	7.3 Expressions
50	7.4 Assignments
51	7.5 Gate and switch level modeling
54	7.6 User-defined primitives (UDPs)
55	7.7 Behavioral modeling
61	7.8 Tasks and functions
64	7.9 Disabling of named blocks and tasks 7.10 Hierarchical structures
70	7.11 Configuring the contents of a design
72	7.12 Specify blocks 7.13 Timing checks 7.14 Backannotation using the standard delay format 7.15 System tasks and functions 7.16 Value change dump (VCD) files 7.17 Compiler directives
73	7.18 PLI
74	Annex A (informative) Syntax summary A.1 Source text
76	A.2 Declarations
81	A.3 Primitive instances
83	A.4 Module and generated instantiation
84	A.5 UDP declaration and instantiation
85	A.6 Behavioral statements
89	A.7 Specify section
94	A.8 Expressions
98	A.9 General
102	Annex B (informative) Functional mismatches B.1 Non-deterministic behavior B.2 Pragmas
103	B.3 Using `ifdef
104	B.4 Incomplete sensitivity list
105	B.5 Assignment statements mis-ordered
106	B.6 Flip-flop with both asynchronous reset and asynchronous set B.7 Functions
107	B.8 Casex B.9 Casez
108	B.10 Making x assignments
109	B.11 Assignments in variable declarations B.12 Timing delays
110	Annex C (informative) List of Participants

Additional information

Standard Title	IEC 62142 Ed. 1 (IEEE Std 1364.1(TM)-2002): Standard for Verilog(R) Register Transfer Level Synthesis
Published Code	IEEE
Publication Date	2002
Pages Count	116

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IEEE IEC 62142 2005:2002 Edition

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