IEEE IEC 62530 2007

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IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog – Unified Hardware Design, Specification, and Verification Language

Published By	Publication Date	Number of Pages
IEEE	2007	668

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Description

New IEEE Standard – Active. This standard provides a set of extensions to the IEEE 1364 Verilog hardware description language (HDL) to aid in the creation and verification of abstract architectural level models. It also includes design specification methods, embedded assertions language, testbench language including coverage and an assertions application programming interface (API), and a direct programming interface (DPI). This standard enables a productivity boost in design and validation and covers design, simulation, validation, and formal assertion-based verification flows.

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PDF Pages	PDF Title
4	CONTENTS
12	FOREWORD
14	Title page
15	IEEE Introduction
16	1. Overview 1.1 Scope 1.2 Purpose
18	1.3 Conventions used in this standard 1.4 Syntactic description
19	1.5 Use of color in this standard 1.6 Contents of this standard
22	1.7 Examples 1.8 Prerequisites
24	2. Normative references
26	3. Literal values 3.1 Introduction 3.2 Literal value syntax
27	3.3 Integer and logic literals 3.4 Real literals 3.5 Time literals 3.6 String literals
28	3.7 Array literals 3.8 Structure literals
30	4. Data types 4.1 Introduction
31	4.2 Data type syntax
32	4.3 Integer data types
33	4.4 Real and shortreal data types 4.5 Void data type 4.6 Chandle data type
34	4.7 String data type
39	4.8 Event data type 4.9 User-defined types
41	4.10 Enumerations
46	4.11 Structures and unions
51	4.12 Class
52	4.13 Singular and aggregate types 4.14 Casting
53	4.15 $cast dynamic casting
54	4.16 Bit-stream casting
57	4.17 Default attribute type
58	5. Arrays 5.1 Introduction 5.2 Packed and unpacked arrays
59	5.3 Multiple dimensions
60	5.4 Indexing and slicing of arrays
61	5.5 Array querying functions 5.6 Dynamic arrays
63	5.7 Array assignment
64	5.8 Arrays as arguments
65	5.9 Associative arrays
68	5.10 Associative array methods
70	5.11 Associative array assignment
71	5.12 Associative array arguments 5.13 Associative array literals 5.14 Queues
74	5.15 Array manipulation methods
80	6. Data declarations 6.1 Introduction 6.2 Data declaration syntax
81	6.3 Constants
85	6.4 Variables
86	6.5 Nets
87	6.6 Scope and lifetime
88	6.7 Nets, regs, and logic
89	6.8 Signal aliasing
91	6.9 Type compatibility
94	6.10 Type operator
96	7. Classes 7.1 Introduction 7.2 Syntax
97	7.3 Overview
98	7.4 Objects (class instance) 7.5 Object properties
99	7.6 Object methods 7.7 Constructors
100	7.8 Static class properties
101	7.9 Static methods 7.10 This
102	7.11 Assignment, renaming, and copying
103	7.12 Inheritance and subclasses 7.13 Overridden members
104	7.14 Super
105	7.15 Casting 7.16 Chaining constructors
106	7.17 Data hiding and encapsulation 7.18 Constant class properties
107	7.19 Abstract classes and virtual methods
108	7.20 Polymorphism: dynamic method lookup 7.21 Class scope resolution operator ::
109	7.22 Out-of-block declarations
110	7.23 Parameterized classes
111	7.24 Typedef class
112	7.25 Classes and structures 7.26 Memory management
114	8. Operators and expressions 8.1 Introduction 8.2 Operator syntax
116	8.3 Assignment operators 8.4 Operations on logic and bit types
117	8.5 Wild equality and wild inequality 8.6 Real operators
118	8.7 Size 8.8 Sign 8.9 Operator precedence and associativity 8.10 Built-in methods
119	8.11 Static prefixes
120	8.12 Concatenation
121	8.13 Assignment patterns
126	8.14 Tagged union expressions and member access
127	8.15 Aggregate expressions 8.16 Operator overloading
129	8.17 Streaming operators (pack/unpack)
133	8.18 Conditional operator 8.19 Set membership
136	9. Scheduling semantics 9.1 Execution of a hardware model and its verification environment 9.2 Event simulation 9.3 The stratified event scheduler
140	9.4 The PLI callback control points
142	10. Procedural statements and control flow 10.1 Introduction 10.2 Statements
143	10.3 Blocking and nonblocking assignments
144	10.4 Selection statements
151	10.5 Loop statements
153	10.6 Jump statements 10.7 Final blocks
154	10.8 Named blocks and statement labels
155	10.9 Disable
156	10.10 Event control
158	10.11 Level-sensitive sequence controls 10.12 Procedural assign and deassign removal
160	11. Processes 11.1 Introduction 11.2 Combinational logic
161	11.3 Latched logic 11.4 Sequential logic 11.5 Continuous assignments
162	11.6 fork…join
163	11.7 Process execution threads 11.8 Process control
165	11.9 Fine-grain process control
168	12. Tasks and functions 12.1 Introduction 12.2 Tasks
170	12.3 Functions
172	12.4 Task and function argument passing
175	12.5 Import and export functions
178	13. Random constraints 13.1 Introduction 13.2 Overview
181	13.3 Random variables
183	13.4 Constraint blocks
196	13.5 Randomization methods
198	13.6 In-line constraints-randomize() with
199	13.7 Disabling random variables with rand_mode()
200	13.8 Controlling constraints with constraint_mode()
201	13.9 Dynamic constraint modification
202	13.10 In-line random variable control
203	13.11 Randomization of scope variables-std::randomize()
204	13.12 Random number system functions and methods
206	13.13 Random stability
208	13.14 Manually seeding randomize
209	13.15 Random weighted case-randcase
210	13.16 Random sequence generation-randsequence
218	14. Interprocess synchronization and communication 14.1 Introduction 14.2 Semaphores
219	14.3 Mailboxes
222	14.4 Parameterized mailboxes
223	14.5 Event
225	14.6 Event sequencing: wait_order()
226	14.7 Event variables
228	15. Clocking blocks 15.1 Introduction 15.2 Clocking block declaration
230	15.3 Input and output skews
231	15.4 Hierarchical expressions 15.5 Signals in multiple clocking blocks 15.6 Clocking block scope and lifetime
232	15.7 Multiple clocking blocks example 15.8 Interfaces and clocking blocks
234	15.9 Clocking block events 15.10 Cycle delay: ##
235	15.11 Default clocking
236	15.12 Input sampling 15.13 Synchronous events
237	15.14 Synchronous drives
240	16. Program block 16.1 Introduction 16.2 The program construct
242	16.3 Eliminating testbench races
243	16.4 Blocking tasks in cycle/event mode 16.5 Programwide space and anonymous programs
244	16.6 Program control tasks
246	17. Assertions 17.1 Introduction 17.2 Immediate assertions
248	17.3 Concurrent assertions overview
249	17.4 Boolean expressions
251	17.5 Sequences
254	17.6 Declaring sequences
257	17.7 Sequence operations
274	17.8 Manipulating data in a sequence
278	17.9 Calling subroutines on match of a sequence
279	17.10 System functions 17.11 Declaring properties
292	17.12 Multiclock support
300	17.13 Concurrent assertions
306	17.14 Clock resolution
312	17.15 Binding properties to scopes or instances
314	17.16 Expect statement
315	17.17 Clocking blocks and concurrent assertions
318	18. Coverage 18.1 Introduction 18.2 Defining the coverage model: covergroup
321	18.3 Using covergroup in classes
323	18.4 Defining coverage points
329	18.5 Defining cross coverage
333	18.6 Specifying coverage options
338	18.7 Predefined coverage methods
339	18.8 Predefined coverage system tasks and functions 18.9 Organization of option and type_option members
340	18.10 Coverage computation
342	19. Hierarchy 19.1 Introduction 19.2 Packages
347	19.3 Compilation unit support
348	19.4 Top-level instance
349	19.5 Module declarations 19.6 Nested modules
351	19.7 Extern modules
352	19.8 Port declarations
353	19.9 List of port expressions
354	19.10 Time unit and precision
355	19.11 Module instances
359	19.12 Port connection rules
361	19.13 Name spaces
362	19.14 Hierarchical names
364	20. Interfaces 20.1 Introduction
365	20.2 Interface syntax
369	20.3 Ports in interfaces
370	20.4 Modports
376	20.5 Interfaces and specify blocks
377	20.6 Tasks and functions in interfaces
383	20.7 Parameterized interfaces
385	20.8 Virtual interfaces
389	20.9 Access to interface objects
392	21. Configuration libraries 21.1 Introduction 21.2 Libraries
394	22. System tasks and system functions 22.1 Introduction 22.2 Type name function
395	22.3 Expression size system function 22.4 Range system function
396	22.5 Shortreal conversions 22.6 Array querying system functions
398	22.7 Assertion severity system tasks
399	22.8 Assertion control system tasks 22.9 Assertion system functions
400	22.10 Random number system functions 22.11 Program control 22.12 Coverage system functions 22.13 Enhancements to Verilog system tasks
402	22.14 $readmemb and $readmemh 22.15 $writememb and $writememh
403	22.16 File format considerations for multidimensional unpacked arrays
404	22.17 System task arguments for multidimensional unpacked arrays
406	23. Compiler directives 23.1 Introduction 23.2 ‘define macros
407	23.3 `include 23.4 `begin_keywords and `end_keywords
410	24. Value change dump (VCD) data 24.1 Introduction 24.2 VCD extensions
412	25. Deprecated constructs 25.1 Introduction 25.2 Defparam statements 25.3 Procedural assign and deassign statements
414	26. Direct programming interface (DPI) 26.1 Overview
415	26.2 Two layers of the DPI
416	26.3 Global name space of imported and exported functions
417	26.4 Imported tasks and functions
423	26.5 Calling imported functions
425	26.6 Exported functions 26.7 Exported tasks
426	26.8 Disabling DPI tasks and functions
428	27. SystemVerilog VPI object model 27.1 Introduction
430	27.2 Module (supersedes 26.6.1 of IEEE Std 1364)
431	27.3 Interface 27.4 Modport 27.5 Interface task and function declaration
432	27.6 Program
433	27.7 Instance
434	27.8 Instance arrays (supersedes 26.6.2 of IEEE Std 1364)
435	27.9 Scope (supersedes 26.6.3 of IEEE Std 1364)
436	27.10 IO declaration (supersedes 26.6.4 of IEEE Std 1364)
437	27.11 Ports (supersedes 26.6.5 of IEEE Std 1364)
438	27.12 Reference objects
442	27.13 Nets (supersedes 26.6.6 of IEEE Std 1364)
445	27.14 Variables (supersedes 26.6.7 and 26.6.8 of IEEE Std 1364)
448	27.15 Variable select (supersedes 26.6.8 of IEEE Std 1364) 27.16 Variable drivers and loads (supersedes 26.6.23 of IEEE Std 1364)
449	27.17 Typespec
450	27.18 Structures and unions
451	27.19 Named events (supersedes 26.6.11 of IEEE Std 1364)
452	27.20 Parameter (supersedes 26.6.12 of IEEE Std 1364)
453	27.21 Class definition
454	27.22 Class variables and class objects
456	27.23 Constraint, constraint ordering, distribution
457	27.24 Constraint expression 27.25 Module path, path term (supersedes 26.6.15 of IEEE Std 1364)
458	27.26 Task and function declaration (supersedes 26.6.18 of IEEE Std 1364)
459	27.27 Task and function call (supersedes 26.6.19 of IEEE Std 1364)
460	27.28 Frames (supersedes 26.6.20 of IEEE Std 1364)
461	27.29 Threads
462	27.30 Clocking block
463	27.31 Assertion
464	27.32 Concurrent assertions 27.33 Property declaration
465	27.34 Property specification
466	27.35 Sequence declaration
467	27.36 Sequence expression
468	27.37 Multiclock sequence expression
469	27.38 Simple expressions (supersedes 26.6.25 of IEEE Std 1364)
470	27.39 Expressions (supersedes 26.6.26 of IEEE Std 1364)
472	27.40 Atomic statement (supersedes atomic stmt in 26.6.27 of IEEE Std 1364)
473	27.41 Event statement (supersedes event stmt in 26.6.27 of IEEE Std 1364) 27.42 Process (supersedes process in 26.6.27 of IEEE Std 1364) 27.43 Assignment (supersedes 26.6.28 of IEEE Std 1364)
474	27.44 Event control (supersedes 26.6.30 of IEEE Std 1364) 27.45 Waits (supersedes wait in 26.6.32 of IEEE Std 1364) 27.46 If, if-else (supersedes 26.6.35 of IEEE Std 1364)
475	27.47 Case, pattern (supersedes 26.6.36 of IEEE Std 1364) 27.48 Expect
476	27.49 For (supersedes 26.6.33 of IEEE Std 1364) 27.50 Do-while, foreach
477	27.51 Alias statement 27.52 Disables (supersedes 26.6.38 of IEEE Std 1364) 27.53 Return statement
478	27.54 Attribute (supersedes 26.6.42 of IEEE Std 1364)
479	27.55 Generates (supersedes 26.6.44 of IEEE Std 1364)
482	28. SystemVerilog assertion API 28.1 Requirements 28.2 Static information
483	28.3 Dynamic information
486	28.4 Control functions
488	29. SystemVerilog code coverage control and API 29.1 Requirements 29.2 SystemVerilog real-time coverage access
493	29.3 FSM recognition
496	29.4 VPI coverage extensions
500	30. SystemVerilog data read API 30.1 Introduction 30.2 Requirements
501	30.3 Extensions to VPI enumerations
502	30.4 VPI object type additions
504	30.5 Object model diagrams 30.6 Usage extensions to VPI routines
507	30.7 VPI routines added in SystemVerilog
508	30.8 Reading data
518	30.9 Optionally unloading data 30.10 Reading data from multiple databases and/or different read library providers
521	30.11 VPI routines extended in SystemVerilog
522	30.12 VPI routines added in SystemVerilog
526	Annex A (normative) Formal syntax
566	Annex B (normative) Keywords
568	Annex C (normative) Std package
570	Annex D (normative) Linked lists
578	Annex E (normative) Formal semantics of concurrent assertions
590	Annex F (normative) DPI C layer
622	Annex G (normative) Include file svdpi.h
632	Annex H (normative) Inclusion of foreign language code
636	Annex I (normative) sv_vpi_user.h
646	Annex J (informative) Glossary
650	Annex K (informative) Bibliography
651	Annex L (informative) List of participants
654	Index

Additional information

Standard Title	IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog – Unified Hardware Design, Specification, and Verification Language
Published Code	IEEE
Publication Date	2007
Pages Count	668

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