IEEE IEC 62531 2007
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IEC 62531 Ed. 1 (2007-11) (IEEE Std 1850-2005): Standard for Property Specification Language (PSL)
Published By | Publication Date | Number of Pages |
IEEE | 2007 | 156 |
New IEEE Standard – Active. The IEEE Property Specification Language (PSL) is defined in this standard. PSL is a formal notation for specification of electronic system behavior, compatible with multiple electronic system design languages, including IEEE Std 1076 (VHDL), IEEE Std 1364 (Verilog), IEEE P1666 (SystemC), and IEEE P1800 (SystemVerilog), thereby enabling a common specification and verification flow for multi-language and mixed-language designs. PSL captures design intent in a form suitable for simulation, formal verification, formal analysis, and hybrid verification tools. PSL enhances communication among architects, designers, and verification engineers to increase productivity throughout the design and verification process. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.
PDF Catalog
PDF Pages | PDF Title |
---|---|
4 | CONTENTS |
6 | FOREWORD |
9 | IEEE Introduction Title page Errata Interpretations Patents |
10 | 1. Overview 1.1 Scope 1.2 Purpose 1.2.1 Background |
11 | 1.2.2 Motivation 1.2.3 Goals 1.3 Usage 1.3.1 Functional specification |
12 | 1.3.2 Functional verification |
16 | 2. Normative references |
18 | 3. Definitions, acronyms, and abbreviations 3.1 Definitions |
21 | 3.2 Acronyms and abbreviations 3.3 Special terms |
24 | 4. Organization 4.1 Abstract structure 4.1.1 Layers 4.1.2 Flavors |
25 | 4.2 Lexical structure 4.2.1 Identifiers 4.2.2 Keywords |
26 | 4.2.3 Operators |
31 | 4.2.4 Macros |
33 | 4.2.5 Comments 4.3 Syntax 4.3.1 Conventions |
34 | 4.3.2 HDL dependencies |
38 | 4.4 Semantics 4.4.1 Clocked vs. unclocked evaluation |
39 | 4.4.2 Safety vs. liveness properties 4.4.3 Linear vs. branching logic 4.4.4 Simple subset |
40 | 4.4.5 Finite-length vs. infinite-length behavior 4.4.6 The concept of strength |
42 | 5. Boolean layer 5.1 Expression type classes 5.1.1 Bit expressions |
43 | 5.1.2 Boolean expressions |
44 | 5.1.3 BitVector expressions 5.1.4 Numeric expressions |
45 | 5.1.5 String expressions 5.2 Expression forms 5.2.1 HDL expressions |
47 | 5.2.2 PSL expressions 5.2.3 Built-in functions |
53 | 5.2.4 Union expressions 5.3 Clock expressions |
55 | 5.4 Default clock declaration |
58 | 6. Temporal layer |
59 | 6.1 Sequential expressions 6.1.1 Sequential Extended Regular Expressions (SEREs) |
66 | 6.1.2 Sequences |
72 | 6.2 Properties |
73 | 6.2.1 FL properties |
93 | 6.2.2 Optional Branching Extension (OBE) properties |
100 | 6.2.3 Replicated properties |
102 | 6.3 Property and sequence declarations |
103 | 6.3.1 Parameters |
105 | 6.3.2 Declarations |
106 | 6.3.3 Instantiation |
110 | 7. Verification layer 7.1 Verification directives 7.1.1 assert |
111 | 7.1.2 assume |
112 | 7.1.3 assume_guarantee 7.1.4 restrict |
113 | 7.1.5 restrict_guarantee |
114 | 7.1.6 cover 7.1.7 fairness and strong_fairness |
115 | 7.2 Verification units |
116 | 7.2.1 Verification unit binding |
118 | 7.2.2 Verification unit inheritance |
119 | 7.2.3 Verification unit scoping rules |
122 | 8. Modeling layer 8.1 Integer ranges |
123 | 8.2 Structures |
124 | Annex A (normative) Syntax rule summary A.1 Conventions |
125 | A.2 Tokens A.3 HDL dependencies |
126 | A.3.1 Verilog Extensions |
127 | A.3.2 Flavor macros |
129 | A.4 Syntax productions A.4.1 Verification units A.4.2 PSL declarations |
130 | A.4.3 PSL directives |
131 | A.4.4 PSL properties |
133 | A.4.5 Sequential Extended Regular Expressions (SEREs) |
134 | A.4.6 Parameterized Properties and SEREs A.4.7 Sequences |
135 | A.4.8 Forms of expression |
136 | A.4.9 Optional Branching Extension |
138 | Annex B (normative) Formal syntax and semantics of IEEE Std 1850 PSL B.1 Typed-text representation of symbols B.2 Syntax |
139 | B.3 Semantics B.3.1 Semantics of FL formulas |
142 | B.3.2 Semantics of OBE formulas |
143 | B.4 Syntactic Sugaring B.4.1 Additional SERE operators |
144 | B.4.2 Additional FL operators |
146 | B.4.3 Parameterized SEREs and formulas |
147 | B.5 Rewriting rules for clocks |
148 | Annex C (informative) Bibliography |
150 | Annex D (informative) List of participants |
152 | Index A-F |
153 | G-S |
154 | S-Z |