IEEE ISO IEC 15205 2001

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ISO/IEC 15205:2000 (IEEE Std 1496-1993) SBus — Chip and Module Interconnect Bus

Published By	Publication Date	Number of Pages
IEEE	2001	104

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Description

New IEEE Standard – Active. An input/output expansion bus with a 32-or 64-bit width is described in this standard.The SBus is designed for systems requiring a small number of expansion ports.SBus Cards may be connected to a standard SBus Connector mounted on the motherboard.SBus Devices may also be attached to the SBus directly on the system’s motherboard.The dimensions of the SBus Card are 83.8 mm by 146.7 mm,making the cards appropriate for small computer systems that make extensive use of highly integrated circuits.The SBus Cards are designed to be installed in a plane parallel to the system’s motherboard as mezzanine cards. They are designed to provide connections for devices external to the computer system through an exposed back panel.The form factor is useful in Futurebus+,VMEbus,desktop computers,and similar applications. The SBus has the capability of transferring data at rates up to 168 Mbytes/s,depending on the implementation options selected. SBus Cards may either serve as Masters on the bus,providing all virtual address information as well as the data to be transferred,or they may serve as Slaves on the bus,providing data transfer according to the require- ments of some other SBus Master.The SBus Master for a data transfer is selected by an arbitration process managed by the single SBus Controller on the SBus.The SBus Controller provides a virtual to physical ad- dress translation service.

PDF Catalog

PDF Pages	PDF Title
1	Title Page
2	IEEE Copyright
3	CONTENTS
5	FOREWORD
6	INTRODUCTION Participants
9	1. General 1.1 Scope and object 1.2 Normative references
10	2. Definitions, usage of special terms, acronyms, and editorial conventions 2.1 Definitions
14	2.2 Usage of special terms 2.3 Acronyms 2.4 Editorial conventions
15	3. Overview 3.1 System overview
17	3.2 Overview of configurations
20	3.3 General design information
22	3.4 Performance
24	4. Signal definitions 4.1 CLK signal
25	4.2 RST* signal
26	4.3 PA[27:0] signals 4.4 SEL* signal
27	4.5 AS* signal 4.6 BR* signal 4.7 BG* signal
28	4.8 D[31:0], D[63:0], and DP signals
29	4.9 SIZ[2:0] signals 4.10 RD signal
30	4.11 ACK[2:0]* signals
32	4.12 LERR* signal
33	4.13 INT[7:1]* signals
34	5. SBus cycle definitions 5.1 Arbitration Phase
35	5.2 Translation Phase
37	5.3 Extended Transfer Information Phase
41	5.4 Transfer Phase
59	5.5 Dual function SBus Devices
60	5.6 Exception conditions
61	5.7 Extended Transfer locking protocol
63	6. SBus electrical requirements 6.1 Power
64	6.2 Electronic characteristics
67	6.3 Electronic timing requirements
70	6.4 Compliance requirements 7. Environmental requirements 7.1 Operating range
71	8. Mechanical requirements 8.1 SBus Slot Connector
75	8.2 SBus Card
89	8.3 Panel installation
90	9. SBus program interface 9.1 Introduction 9.2 Program format and interpretation
91	9.3 Required FCode attributes 9.4 FCode language 9.5 Special functions of Word 0
93	Annex A (informative) Compliance checklist
98	Annex B (informative) Known implementation variations
102	Bibliography
103	Index