IEEE P1149.7:2022 Edition

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IEEE Approved Draft Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture

Published By	Publication Date	Number of Pages
IEEE	2022

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Description

Revision Standard – Active – Draft. This specification describes circuitry that may be added to an integrated circuit to provide access to on-chip Test Access Ports (TAPs) specified by IEEE Std 1149.1. The circuitry uses IEEE Std 1149.1 as its foundation, providing complete backward compatibility, while aggressively adding features to support test and applications debug. It defines six classes of 1149.7 Test Access Ports (TAP.7s), T0–T5, with each class providing incremental capability, building on that of the lower level classes. Class T0 provides the behavior specified by 1149.1 from startup when there are multiple on-chip TAPs. Class T1 adds common debug functions and features to minimize power consumption. Class T2 adds operating modes that maximize scan performance. It also provides an optional hot-connection capability to prevent system corruption when a connection is made to a powered system. Class T3 supports operation in either a four-wire Series or Star Scan Topology. Class T4 provides for communication with either a two-pin or four-pin interface. The two-pin operation serializes 1149.1 transactions and provides for higher Test Clock rates. Class T5 adds the ability to perform data transfers concurrently with scan, supports utilization of functions other than scan, and provides control of TAP.7 pins to custom debug technologies in a manner that ensures current and future interoperability.

PDF Catalog

PDF Pages	PDF Title
1	IEEE Std 1149.7-2022 Front Cover
2	Title page
4	Notice and Disclaimer of Liability Concerning the Use of IEEE Standards Documents Translations
5	Official statements Comments on standards Laws and regulations Data privacy Copyrights
6	Photocopies Updating of IEEE Standards documents Errata Patents
7	IMPORTANT NOTICE
8	Participants
9	Introduction History of the development of this standard
10	Changes introduced by this revision
11	Contents
40	Figures
51	Tables
57	1. Overview 1.1 Scope 1.2 Purpose 1.3 Word usage
58	1.4 Contrasting IEEE Std 1149.1 and this standard
59	1.5 Challenges
60	1.6 Important considerations 1.7 Nomenclature 1.7.1 References to technology and standards 1.7.2 Describing Test Access Port behaviors
61	1.7.3 Describing TAPs and TAP controllers
62	1.7.4 Describing scan exchanges 1.7.5 Describing TAP signals
63	1.8 Ensuring transparency to IEEE 1149.1 intellectual property 1.8.1 IEEE 1149.1 constraints 1.8.2 IEEE 1149.1 constraints/requirements balancing 1.8.3 IEEE 1149.1 upgrade path
64	1.9 Maximizing compatibility with 1149.1 IP 1.9.1 IEEE 1149.1 infrastructure 1.9.1.1 IEEE 1149.1 instructions 1.9.1.2 IEEE 1149.1 Scan Paths 1.9.1.3 IEEE 1149.1 boundary-scan capability 1.9.2 Test Clock treatment 1.9.2.1 Test Clock source
65	1.9.2.2 Test Clock shared or dedicated use 1.9.2.3 Unorthodox use of Test Clock
66	1.10 Scalability 1.10.1 Types of operation/capability classes
68	1.10.2 Signaling 1.11 Flexibility 1.11.1 Supporting various scan topologies
70	1.11.2 Operation with more than one scan topology/other technologies 1.12 Document content
71	1.12.1 Descriptive material 1.12.2 Specification material 1.13 Document organization 1.13.1 Partitioning
72	1.13.1.1 Foundation
73	1.13.1.2 TAP.7 Classes 1.13.1.3 Test description languages 1.13.1.4 Annexes
74	1.13.2 Pictorial view
75	1.14 Using the standard 1.14.1 User background knowledge 1.14.2 Types of users 1.14.2.1 Chip designer 1.14.2.2 Programmer 1.14.3 Use summary
76	1.15 Conventions
82	2. Normative references
83	3. Definitions, acronyms, and abbreviations 3.1 Definitions
87	3.2 Acronyms and abbreviations
92	4. TAP.7 concepts and architecture 4.1 Introduction 4.2 Concepts supporting system architecture 4.2.1 Maximizing compatibility with IEEE Std 1149.1
93	4.2.1.1 Hardware components 4.2.1.2 Software components 4.2.2 TAPC hierarchy 4.2.2.1 Overview
94	4.2.2.2 Hierarchy levels
95	4.2.3 Parking the TAPC state 4.2.3.1 Overview
96	4.2.3.2 Parking-state relationships
97	4.2.3.3 Parking-state terminology 4.2.3.3.1 ADTAPC selection states 4.2.3.3.2 CLTAPC selection states
98	4.2.3.3.3 EMTAPC selection states
99	4.2.3.3.4 Selection state summary 4.2.4 Choice of parking states 4.2.5 Parking methods 4.2.6 Operation of the TAP.7 Controller 4.2.6.1 TAP.7 Controller management
100	4.2.6.2 System and Control Paths
101	4.2.6.3 Power management
102	4.2.7 Scan topologies 4.2.7.1 Series and Star Scan Topologies
103	4.2.7.2 Scan Topology Training 4.2.7.3 Sharing of signaling with other technologies 4.2.7.4 Direct addressability for Star Scan Topologies
104	4.2.7.5 Series-Equivalent Scans for Star Scan Topologies
105	4.2.7.6 Output-drive characteristics
106	4.2.7.7 Scan formats
107	4.2.7.8 Interoperability 4.3 Concepts supporting pin efficiency 4.3.1 Signaling methods
108	4.3.2 Protocols 4.3.2.1 Protocol types
109	4.3.2.2 Standard Protocol 4.3.2.3 Advanced Protocol
110	4.3.2.3.1 Interleaving of scan and non-scan information
111	4.3.2.3.2 Serialization of scan information
112	4.3.2.4 Control Protocol 4.3.3 Advanced and Control Protocol characteristics 4.3.3.1 Packets, bit-frames, and bits
113	4.3.3.2 Data and control information
114	4.3.4 Performance 4.3.4.1 TAP operation 4.3.4.1.1 Signal timing
115	4.3.4.1.2 Registering of signals 4.3.4.2 Scan transfer efficiency 4.4 Concepts supporting capability 4.4.1 Concepts already described
116	4.4.2 Resets 4.4.3 Private commands and registers 4.5 IEEE 1149.7 architecture 4.5.1 Components
119	4.5.2 Reset types
120	4.5.3 Start-up options
121	4.6 Operating models 4.6.1 Model types 4.6.2 Standard models
123	4.6.3 Advanced models
124	5. T0–T3 TAP.7 operational overview 5.1 Introduction 5.2 T0 TAP.7 5.2.1 Overview
125	5.2.2 Operating modes and capabilities
126	5.2.3 Operation 5.2.3.1 Multi-TAPC architecture 5.2.3.2 Selection and deselection of EMTAPCs
127	5.2.4 T0 TAP.7 high-level block diagram
128	5.3 T1 TAP.7 5.3.1 Overview
129	5.3.2 Operating modes and capabilities 5.3.3 Operation 5.3.3.1 Adding TAP.7 functionality to the BYPASS and IDCODE instructions 5.3.3.2 Zero-bit DR scans
130	5.3.3.3 Utilizing ZBSs for TAP.7 Controller functionality 5.3.3.3.1 Locking the ZBS count 5.3.3.3.2 Control levels
131	5.3.3.3.3 Exiting a control level 5.3.3.3.4 Zeroing the ZBS count 5.3.3.4 EPU Operating States 5.3.3.5 Commands
134	5.3.3.6 Registers
136	5.3.3.7 Using the System and Control Paths
137	5.3.3.7.1 System Path 5.3.3.7.2 Control Path
138	5.3.3.7.3 TDO Drive Policy 5.3.3.8 EPU groups 5.3.4 T1 TAP.7 high-level block diagram 5.4 T2 TAP.7 5.4.1 Overview
140	5.4.2 Operating modes and capabilities
141	5.4.3 Operation 5.4.3.1 Overview
142	5.4.3.2 Using the System and Control Paths
143	5.4.3.3 TDO Drive Policy 5.4.3.4 STL groups 5.4.3.4.1 STL group types
144	5.4.3.4.2 STL Group Membership changes 5.4.4 T2 TAP.7 high-level block diagram
145	5.5 T3 TAP.7 5.5.1 Overview
146	5.5.2 Operating modes and capabilities
148	5.5.3 Operation 5.5.3.1 Within series and star scan topologies 5.5.3.2 T3 TAP.7 Controller addressability in a Star-4 Scan Topology 5.5.3.3 Pause-IR and Pause-DR STL groups
149	5.5.3.4 Series/star scan equivalency 5.5.3.4.1 Defining scan equivalency 5.5.3.4.2 Creating a Series-Equivalent Scan within a Star Scan Topology
150	5.5.3.5 Scan Selection Directives 5.5.3.5.1 Enabling the use of SSDs 5.5.3.5.2 Types of SSDs
151	5.5.3.5.3 SSD execution 5.5.3.5.4 SSD State Machine
152	5.5.3.6 Series-Equivalent Scan creation
153	5.5.3.6.1 Exclusivity of SSD and TAP.7 Controller commands
154	5.5.3.7 Using the System and Control Paths
155	5.5.3.8 TDO Drive Policy 5.5.4 T3 TAP.7 high-level block diagram
157	6. T4–T5 TAP.7 operational overview 6.1 Introduction
158	6.2 T4 TAP.7 6.2.1 Operating modes and capabilities
159	6.2.2 Operation 6.2.2.1 Signal behaviors 6.2.2.2 Rising and falling TMSC input sampling
160	6.2.2.3 Controller addressability in a Star-2 Scan Topology 6.2.2.4 RSU and APU functions
162	6.2.2.4.1 Bypass (BPA) 6.2.2.4.2 Check Process Active (CPA)
165	6.2.2.4.3 Scan Packet Active (SPA)
166	6.2.3 T4 TAP.7 high-level block diagram
167	6.3 T5 TAP.7 6.3.1 Overview
169	6.3.2 Operating modes and capabilities 6.3.2.1 Transport source/destinations 6.3.2.1.1 Single-client operation
170	6.3.2.1.2 Multi-client operation
171	6.3.2.1.3 Client-to-client operation
172	6.3.2.2 Transfer characteristics
173	6.3.3 Operation 6.3.3.1 Transport Control Function
174	6.3.3.2 TPA
175	6.3.4 T5 TAP.7 high-level block diagram
176	6.4 TAP.7 feature summary
178	7. System concepts 7.1 Introduction 7.2 Key system attributes 7.3 DTS/TS connectivity with a mix of technologies 7.3.1 Technology mixes
179	7.3.2 Technology branches
180	7.4 TAP.7 deployment scenarios 7.4.1 TAP.1 Series Branches 7.4.2 TAP.7 Series, Star-4, and Star-2 Branches
181	7.5 Chip TAPC hierarchy
182	7.6 Combined view of TAP connectivity and TAPC hierarchy
183	7.7 Chips, components, and boards
185	8. TAPC hierarchy 8.1 Introduction 8.2 Selection/deselection with the TAPC hierarchy 8.2.1 Selection choices
186	8.2.2 Selection/deselection/class relationships 8.2.3 TAPC parent/child relationships 8.3 TAPC selection/deselection characteristics 8.3.1 TAPC and scan path behavior
187	8.3.2 Selection/deselection mechanisms 8.3.3 Parking states and resynchronization
188	8.4 ADTAPC selection/deselection 8.4.1 Parking use cases 8.4.2 DTS/ADTAPC relationship
189	8.4.3 ADTAPC operation
190	8.5 CLTAPC selection/deselection 8.5.1 Parking use cases 8.5.2 ADTAPC/CLTAPC relationship 8.5.3 CLTAPC operation
192	8.6 EMTAPC selection/deselection 8.6.1 Parking use cases 8.6.2 CLTAPC/EMTAPC relationship 8.6.3 EMTAPC operation
193	8.7 Using a common selection/deselection protocol across technologies 8.8 RSU deployment 8.8.1 Use with new or existing IP
194	8.8.2 Using TAP pins for multiple functions 8.9 Using the TAPC hierarchy 8.9.1 Selection considerations
195	8.9.2 Start-up considerations 8.10 Test/debug applications and the TAPC hierarchy 8.10.1 Debug use of the TAPC hierarchy
196	8.10.2 Test use of the TAPC hierarchy
198	9. Registers, commands, and scan paths 9.1 Introduction 9.2 Command basics
200	9.3 Register portfolio 9.3.1 Description 9.3.1.1 Global and Local Registers 9.3.1.2 Register loads
201	9.3.1.3 Register reset values 9.3.2 Specifications
203	9.4 Command portfolio 9.4.1 Description 9.4.1.1 Command types 9.4.1.2 Store commands
204	9.4.1.3 Select commands 9.4.1.4 Scan commands 9.4.1.5 Enumerate commands 9.4.1.6 Private commands 9.4.1.7 Effects a TAP.7 Controller reset
205	9.4.2 Specifications
210	9.5 Representation of commands in examples 9.6 Global and Local Register programming with commands
211	9.7 1Scan paths 9.7.1 Conceptual and physical views 9.7.1.1 Description 9.7.1.1.1 Path characteristics 9.7.1.1.2 Conceptual path selection
212	9.7.1.1.3 Physical path selection
213	9.7.1.2 Specifications
215	9.7.2 EPU Scan Paths and their selection 9.7.2.1 Description 9.7.2.2 Specifications
216	9.7.3 EPU Scan Path characteristics 9.7.3.1 Description 9.7.3.1.1 Scan-path continuity
217	9.7.3.1.2 EPU Bypass-Path characteristics 9.7.3.1.3 EPU Bit-Path characteristics 9.7.3.1.4 EPU String-Path characteristics
220	9.7.3.1.5 Enumerate-Path characteristics 9.7.3.1.6 Auxiliary Path 9.7.3.2 Specifications
222	9.8 Two-part commands 9.9 Three-part commands 9.9.1 SCNB Command characteristics
223	9.9.2 SCNS Command characteristics
224	9.9.3 CIDA Command characteristics
226	9.10 RDBACKx and CNFGx Registers
227	9.10.1 RDBACKx Registers 9.10.1.1 Description 9.10.1.2 Specifications
228	9.10.2 CNFGx Registers 9.10.2.1 Description 9.10.2.1.1 Overview
229	9.10.2.1.2 CNFG0 mandatory configuration information 9.10.2.1.3 CNFG0 optional configuration information
230	9.10.2.1.4 CNFG1 optional configuration information 9.10.2.1.5 CNFG2 and CNFG3 Registers 9.10.2.1.6 Determining the TAP type and class using configuration information 9.10.2.2 Specifications
232	9.11 An approach to implementing command processing and scan paths
236	10. RSU ancillary services 10.1 Introduction 10.2 Resets 10.2.1 Description 10.2.1.1 Overview
237	10.2.1.2 Reset considerations 10.2.1.3 Reset effects
238	10.2.1.3.1 Type-5 Reset 10.2.1.3.2 Type-4 Reset 10.2.1.3.3 Type-3 Reset
239	10.2.1.3.4 Type-2 Reset 10.2.1.3.5 Type-1 Reset 10.2.1.3.6 Type-0 Reset 10.2.1.3.7 Type-0 versus a Type-2 Reset 10.2.1.4 144BTAP.7 Controller operation is ensured after power-up 10.2.1.5 Other effects of a TAP.7 Controller reset
240	10.2.1.6 An approach to implementing TAP.7 Controller resets
241	10.2.2 Specifications
243	10.3 Start-up options 10.3.1 Description 10.3.1.1 Overview
244	10.3.1.2 1149.1-compliant behavior start-up option 10.3.1.3 1149.1-Compatible Start-up option
245	10.3.1.4 IEEE 1149.1-Protocol Compatible 10.3.1.5 Offline-at-Start-up option
246	10.3.1.6 Start-up behavior
247	10.3.2 Specifications
251	10.4 Escape Detection 10.4.1 Description 10.4.1.1 Overview
252	10.4.1.2 Detection
253	10.4.1.2.1 Custom Escape 10.4.1.2.2 Selection and Deselection Escapes
254	10.4.1.3 Reset Escape 10.4.1.4 Timing considerations 10.4.1.5 An approach to implementing Escape Detection
256	10.4.2 Specifications
257	10.5 Selection Alert 10.5.1 Description 10.5.1.1 Overview
258	10.5.1.2 Selection Alert Bit Sequence
259	10.5.1.3 Selection Alert detection 10.5.1.4 An approach to implementing Selection Alerts
261	10.5.2 Specifications
263	10.6 Deselection Alert 10.6.1 Description 10.6.2 Specifications
264	10.7 Programming considerations 10.7.1 Resets 10.7.2 Escapes 10.7.3 Selection Alerts 10.7.4 Test and debug 10.7.5 Concurrent use of a Selection Escape and Selection Alert
265	10.8 ADTAPC State Machine 10.8.1 Need 10.8.2 An approach to implementing the ADTAPC
267	11. RSU Online/Offline capability 11.1 Introduction 11.2 Managing Online/Offline operation
268	11.3 Online/Offline operating principles 11.3.1 Conceptual view of Online/Offline operation
269	11.3.2 Events affecting Online/Offline operation
270	11.3.3 Summary of responses to selection/deselection events 11.3.4 Interoperability with other technologies
272	11.4 Initiating Offline operation 11.4.1 Description 11.4.1.1 Events initiating Offline operation 11.4.1.2 Escapes
273	11.4.1.3 Alerts 11.4.1.4 Use of an unsupported feature 11.4.1.5 Offline-at-Start-up 11.4.2 Specifications 11.5 Initiating Online operation 11.5.1 Description
274	11.5.2 Specifications 11.6 Context-sensitive response to Selection and Deselection Escapes 11.6.1 Description
275	11.6.1.1 Escape qualification criteria during Online operation 11.6.1.2 Escape qualification criteria during Offline-at-Start-up operation
276	11.6.1.3 Selection Alert during Offline-at-Start-up operation 11.6.2 Specifications
277	11.7 Selection Sequence 11.7.1 Initiation 11.7.2 Format 11.7.3 Technology-independent portion
278	11.7.4 Technology-dependent portion 11.7.5 Forms of Selection Sequence
279	11.7.6 Online Activation Code 11.7.6.1 Description
280	11.7.6.2 Specifications
281	Figure 11-9 — Selection Escape/subsequent data timing relationship
282	Figure 11-10 — Selection Alert/subsequent data timing relationship 11.7.7 TAP.7 Extension Code 11.7.7.1 Description
283	11.7.7.2 Specifications
284	11.7.8 Global Register load 11.7.8.1 Description
285	11.7.8.2 Specifications 11.7.9 Check Packet 11.7.9.1 Description 11.7.9.1.1 Format
286	11.7.9.1.2 Function
287	11.7.9.1.3 Directives 11.7.9.2 Specifications
288	11.8 Parking-state considerations 11.8.1 Description 11.8.2 Specifications
291	11.9 Control State Machine 11.9.1 Mandatory and optional behaviors 11.9.1.1 Description
292	11.9.1.2 Specifications
293	11.9.2 Standard state (STD) 11.9.2.1 Description 11.9.2.2 Specifications
294	11.9.3 Advanced state (ADV) 11.9.3.1 Description 11.9.3.2 Specifications
295	11.9.4 Offline waiting state (OLW) 11.9.4.1 Description 11.9.4.2 Specifications
296	11.9.5 Test state (TEST) 11.9.5.1 Description 11.9.5.1.1 Selection test
297	11.9.5.1.2 Factors requiring a Global Register load for placement Online 11.9.5.1.3 ADTAPC resynchronization
298	11.9.5.1.4 Priority of conditions causing state changes 11.9.5.1.5 Test state function
299	11.9.5.1.6 Selection Sequences requiring a state load
300	11.9.5.2 Specifications
303	11.9.6 Check Packet state (CHK) 11.9.6.1 Description 11.9.6.1.1 CHK substates
304	11.9.6.1.2 CP examples
306	11.9.6.2 Specifications
309	11.9.7 Offline-at-Start-up state (OLS) 11.9.7.1 Description 11.9.7.1.1 Placement Online 11.9.7.1.2 CLTAPC state initialization
310	11.9.7.1.3 Selection Escape qualification in the OLS state 11.9.7.1.4 Example of exiting the OLS state
311	11.9.7.2 Specifications
312	11.9.7.3 An approach to implementing the CSM
314	11.10 Programming considerations 11.10.1 Escapes 11.10.1.1 Selection Escape 11.10.1.2 Deselection Escape
315	11.10.1.3 Reset Escape 11.10.2 Alerts 11.10.2.1 Deselection Alert 11.10.2.2 Selection Alert 11.10.2.3 Offline-at-Start-up
316	11.10.3 Selection Sequences 11.10.3.1 DTS/TAP.7 Controller synchronization 11.10.3.2 Short Form 11.10.3.3 Long Form
317	11.10.4 Hang caused by a programming error
318	12. TAP signals 12.1 Introduction 12.2 TAP.7 Class/signal relationships 12.2.1 Description
319	12.2.2 Specifications
320	12.3 Signal function and bias 12.3.1 Description
321	12.3.2 Specifications
322	12.4 Test Reset (nTRST and nTRST_PD) signals 12.4.1 Description
323	12.4.2 Specifications 12.5 TAP.7 signal functions with corresponding IEEE 1149.1 names 12.5.1 Description 12.5.2 Specifications 12.6 Test Clock (TCK) 12.6.1 Description 12.6.2 Specifications
324	12.7 Test Mode Select (TMS/TMSC) 12.7.1 Description 12.7.1.1 Online start-up
325	12.7.1.2 Offline start-up
327	12.7.1.3 Combined view of Online and Offline-at-Start-up TMS(C) signal behaviors
330	12.7.2 Specifications
331	12.8 Test Data Input (TDI/TDIC) 12.8.1 Description
332	12.8.2 Specifications
334	12.9 Test Data Output (TDO/TDOC) 12.9.1 Description
335	12.9.2 Specifications
336	12.10 Offline-at-Start-up behavior 12.10.1 Description
337	12.10.2 Specifications 12.11 TAP connections 12.11.1 Description 12.11.2 Specifications
338	12.12 Applicability of this standard 12.12.1 Description 12.12.2 Specifications
339	12.13 Recommendations for interoperability 12.13.1 Overview 12.13.2 Power-up behavior 12.13.3 IEEE 1149.7-Non-disruptive behavior 12.13.3.1 Description
340	12.13.3.2 Specifications 12.13.4 IEEE 1149.7-Other Behavior 12.13.4.1 Description 12.13.4.2 Specifications
342	13. TDO(C) Signal Drive Policy 13.1 Introduction 13.2 TDO(C) Signal Drive Types 13.2.1 TDO(C) Signal Drive Types
343	13.2.1.1 Single Drive 13.2.1.2 Joint Drive 13.2.1.3 Voting Drive 13.2.1.4 Inhibited Drive 13.2.2 Wire-ANDed TDOC data created with a combination of drives
344	13.3 Factors affecting the TDO(C) Drive Policy
345	13.4 TDO(C) Drive Policy template 13.4.1 General characteristics 13.4.2 TDOC drive enables 13.4.3 TDO(C) Drive Policy components
346	13.4.4 TAP.7 Class/TDO(C) Drive Policy component applicability 13.4.5 Dormant TDO(C) Drive Policy 13.4.6 Transition TDO(C) Drive Policy 13.4.7 Series TDO(C) Drive Policy components 13.4.7.1 Series System
347	13.4.7.2 Series Command 13.4.7.3 Series Control Level 13.4.8 Star-4 TDO(C) Drive Policies 13.4.8.1 Star-4 System 13.4.8.2 Star-4 Command
348	13.4.8.3 Star-4 control level 13.4.9 Hierarchical and flat views of the TDO(C) Drive Policy
351	13.4.10 Conceptual diagram of the TDO(C) Drive Policy
352	13.5 T0 TAP.7 TDOC Drive Policy 13.5.1 Description 13.5.2 Specifications
353	13.6 T1 and T2 TAP.7 TDOC Drive Policy 13.6.1 Description
354	13.6.2 Specifications
355	13.7 T3 and above TAP.7 TDOC Drive Policy 13.7.1 Description
356	13.7.2 Specifications
358	13.8 STL Group Membership 13.8.1 Tracking the Group Membership of STLs 13.8.2 STL Group Membership changes 13.8.2.1 Group membership changes with the Test-Logic-Reset state 13.8.2.2 Group membership changes with the Run-Test/Idle state
359	13.8.2.3 Group membership changes with the Pause-IR state 13.8.2.4 Group membership changes with the Pause-DR state 13.8.3 Commands/SSDs affecting group Scan Group Candidacy and Membership 13.8.3.1 Commands affecting Scan Group Candidacy
360	13.8.3.2 SSDs affecting Scan Group Candidacy and Membership 13.8.3.2.1 SSDs associated with the Run-Test/Idle state 13.8.3.2.2 SSDs associated with the Pause-IR state 13.8.3.2.3 SSDs associated with the Pause-DR state
361	13.8.4 Only Scan Group Member determination 13.8.4.1 Criteria 13.8.4.2 Method and information used to make determination 13.8.4.2.1 Idle Group Membership and membership counts
362	13.8.4.2.2 Pause-xR Group Membership and membership counts 13.8.4.2.3 Scan Group Membership and membership counts
363	13.8.4.2.4 Information recorded 13.8.5 STL group candidate and membership counts 13.8.5.1 Description 13.8.5.1.1 Scan Group Candidate Count (SGCC)
365	13.8.5.1.2 Potential Scan Group Membership Count Last
366	13.8.5.1.3 Factors creating SGCC and PSGMCL ambiguity 13.8.5.2 Specifications
369	13.8.6 Scan Group Membership Count Last determination 13.8.6.1 Description 13.8.6.2 Specification
370	13.8.7 Only Scan Group Member Last determination 13.8.7.1 Description 13.8.7.2 Specification
372	13.9 EPU Group Membership 13.9.1 Description 13.9.1.1 Tracking the EPU’s Group Membership 13.9.1.2 Conditional Group Member Count
373	13.9.1.3 Only Conditional Group Member determination
374	13.9.2 Specifications
376	13.10 Drive Policy summary
377	13.11 An approach to implementing TDOC Drive Policy 13.11.1 Policy generation
378	13.11.2 Potential Scan Group Member Last 13.11.3 The SGCC and PSGMCL functions
379	13.11.4 Determining Scan Group Only Member Last/Membership Count Last
380	13.11.5 The CGMC function 13.12 Programming considerations
381	14. TMS(C) Signal Drive Policy 14.1 Introduction 14.2 TMS(C) output bit types 14.2.1 Scan Packet content
382	14.2.2 Transport Packet content
383	14.2.3 Drive relationship with TCKC
384	14.3 Drive policy by output bit type
385	14.4 TMSC Signal Drive Types 14.4.1 TMSC Signal Drive Types
386	14.4.1.1 Single Drive 14.4.1.2 Joint Drive 14.4.1.3 Voting Drive 14.4.1.4 Inhibited Drive 14.4.2 Wire-ANDed TMSC signal values
387	14.5 Dormant Bit Drive Policy 14.5.1 Description 14.5.2 Specifications 14.6 Precharge Bit Drive Policy 14.6.1 Description 14.6.2 Specifications
388	14.7 RDY Bit Drive Policy 14.7.1 Description 14.7.1.1 Characteristics 14.7.1.2 Policy details
389	14.7.1.3 Relationship to CLTAPC selection state changes 14.7.2 Specifications
391	14.8 TDO Bit Drive Policy 14.8.1 Description 14.8.1.1 Characteristics 14.8.1.1.1 Policy details for System Path
392	14.8.1.1.2 Policy details for Control Path 14.8.1.2 Correlation to TDO(C) Drive Policy
393	14.8.1.3 Combined TDO bit drive summary
394	14.8.2 Specifications
395	14.9 Transport Bit Drive Policy 14.9.1 Description
396	14.9.2 Specifications 14.10 An approach to implementing TMSC Drive Policy
400	14.11 Programming considerations
402	15. IEEE 1149.1-compliance concepts 15.1 Introduction 15.2 Background
403	15.3 Test and debug views of a system of interest
404	15.4 An approach to implementing EMTAPC selection/deselection
405	16. T0 TAP.7 16.1 Introduction 16.2 Deployment
406	16.3 Capabilities 16.4 Configurations 16.4.1 Description 16.4.2 Specifications
407	16.5 Start-up behavior 16.5.1 Description 16.5.2 Specifications 16.6 Supporting multiple on-chip TAPCs
408	16.7 Controlling the selection state of EMTAPCs 16.7.1 Description
409	16.7.2 Specifications
411	16.8 Control via the CLTAPC Instruction Register 16.8.1 Description 16.8.1.1 Exclusion of TAPCs
413	16.8.1.2 Isolation of TAPCs
414	16.8.1.3 CLTAPC output registering of MTCP and MTDP control
415	16.8.2 Specifications 16.9 Control via one or more CLTAPC Data Registers 16.9.1 Description
416	16.9.2 Specifications
417	16.10 Control via internal or external tapc_select signals 16.10.1 Description
418	16.10.2 Specifications
419	16.11 Example use cases
420	16.11.1 IR control method with exclusions of TAPCs 16.11.2 IR control method with isolation of TAPCs
421	16.11.3 DR control method with exclusion of TAPCs 16.11.4 DR control method with isolation of TAPCs
422	16.12 Identification of on-chip TAP controller(s) 16.12.1 Description
423	16.12.2 Specifications 16.13 Multiple dies in one package 16.13.1 Description
424	16.13.1.1 Exposing an IEEE 1149.1 DR for the BYPASS and IDCODE instructions 16.13.1.2 Exposing the complete boundary-scan chain for IEEE 1149.1 instructions 16.13.1.3 BSDL documentation
425	16.13.1.4 Packaging dies
426	16.13.1.5 SiP-TAP POR* functionality 16.13.1.6 DR-wire bypass
427	16.13.2 Specifications
428	16.14 Managing STL Group Membership 16.15 RSU operation 16.15.1 Description 16.15.2 Specifications
429	16.16 Programming considerations
430	17. Extended concepts 17.1 Introduction 17.2 Suitability of BYPASS and IDCODE instructions for extended control 17.3 ZBS detection 17.3.1 Description
431	17.3.2 Specifications 17.4 Incrementing, locking, and clearing the ZBS count 17.4.1 Description
432	17.4.2 Specifications
434	17.5 Shared use of ZBSs by the EPU and STL 17.5.1 Description 17.5.1.1 EPU Operating States
435	17.5.1.2 EPU Operating State characteristics
436	17.5.1.3 ZBS use that is compatible with EPU Operating States
437	17.5.1.4 An approach to implementing EPU Operating States
439	17.5.2 Specifications
440	17.6 EPU functionality associated with the ZBS count 17.6.1 Description 17.6.2 Specifications
441	17.7 Programming considerations
442	18. T1 TAP.7 18.1 Introduction
443	18.2 Deployment 18.3 Capabilities 18.3.1 Inherited
444	18.3.2 New 18.4 Register and command portfolio 18.4.1 Description 18.4.1.1 General information
445	18.4.1.2 Register acronyms
446	18.4.1.3 Global Registers 18.4.1.4 Registers already described 18.4.1.5 New register descriptions 18.4.2 Specifications
448	18.5 Configurations 18.5.1 Description 18.5.2 Specifications
449	18.6 Start-up behavior 18.6.1 Description 18.6.2 Specifications 18.7 Conditional Group Membership
450	18.8 Test Reset 18.8.1 Description
451	18.8.2 Specifications
452	18.9 Functional reset 18.9.1 Description
454	18.9.2 Specifications
456	18.10 Power control 18.10.1 Description 18.10.1.1 Overview
457	18.10.1.1.1 Use cases 18.10.1.1.2 Power-control options
458	18.10.1.1.3 Power management within a typical system
459	18.10.1.1.4 Power-control topics 18.10.1.2 Power-Control Model 18.10.1.2.1 TAP.7 Controller power-management states
460	18.10.1.2.2 Key model attributes
461	18.10.1.3 The chip-level power manager’s role in power control 18.10.1.3.1 Responsibilities 18.10.1.3.2 Interaction with TAP.7 Controller
462	18.10.1.3.3 Periods when a Type-0 Reset is asserted 18.10.1.3.4 Handling of power-up and power-down requests
463	18.10.1.3.5 Chip-Level power-up and power-down enables 18.10.1.3.6 The default Power-Control Mode
464	18.10.1.4 The DTS’ role in power control 18.10.1.4.1 Responsibilities 18.10.1.4.2 Directed power-up
465	18.10.1.4.3 Detected power-up
466	18.10.1.5 The TAP.7 Controller’s role in power control 18.10.1.5.1 Responsibilities 18.10.1.5.2 Operation
467	18.10.1.5.3 Test periods
468	18.10.1.5.4 Power-up confirmation test 18.10.1.5.5 Power-down initiation test
469	18.10.1.5.6 Power-down request summary 18.10.1.5.7 Awaiting power-down with the TAP.7 Controller operation shutdown
470	18.10.1.6 Example power-down sequences
472	18.10.1.7 An approach to implementing power control 18.10.2 Specifications
477	18.11 RSU operation 18.11.1 Description
478	18.11.2 Specifications 18.12 Programming considerations
479	19. T2 TAP.7 19.1 Introduction
481	19.2 Deployment 19.3 Capabilities 19.3.1 Inherited 19.3.2 New
482	19.4 Register and command portfolio 19.4.1 Description 19.4.1.1 General information 19.4.1.2 Register acronyms 19.4.1.3 Effects of a Long-Form Selection Sequence 19.4.1.4 New register descriptions
483	19.4.2 Specifications
484	19.5 Configurations 19.5.1 Description 19.5.2 Specifications 19.6 Start-up behavior 19.6.1 Description 19.6.2 Specifications
485	19.7 Scan formats 19.7.1 Description 19.7.2 Specifications 19.8 STL Group Membership 19.8.1 Description 19.8.1.1 Factors affecting group membership
486	19.8.1.2 Reset effects 19.8.1.3 TAPC state effects 19.8.1.4 Control Path effects
488	19.8.1.5 Parked state/selection relationships
489	19.8.1.6 Concurrent CLTAPC and EMTAPC selection changes
490	19.8.1.7 An approach to implementing CLTAPC selection with the T2 Class
492	19.8.2 Specifications
494	19.9 RSU operation 19.9.1 Description 19.9.2 Specifications
495	19.10 Programming considerations
496	20. T3 TAP.7 20.1 Introduction
498	20.2 Deployment
499	20.3 Capabilities 20.3.1 Inherited 20.3.2 New 20.4 Register and command portfolio 20.4.1 Description 20.4.1.1 General information
500	20.4.1.2 Register acronyms 20.4.1.3 Effect of a Long-Form Selection Sequence 20.4.2 Specifications
501	20.5 Configurations 20.5.1 Description
502	20.5.2 Specifications 20.6 Start-up behavior 20.6.1 Description 20.6.2 Specifications 20.7 Scan formats 20.7.1 Description
503	20.7.2 Specifications 20.8 TAP.7 Controller Address (TCA) 20.8.1 Description
504	20.8.2 Specifications
505	20.9 Aliasing the TCA to a Controller ID 20.9.1 Description 20.9.1.1 CID Allocate Command (CIDA)
506	20.9.1.1.1 CID-allocation criteria 20.9.1.1.2 CID-allocation candidates 20.9.1.1.3 CID-allocation process
507	20.9.1.1.4 Directed CID Allocation 20.9.1.1.5 Undirected CID Allocation 20.9.1.2 External AT generation with the JScan3 Scan Format
508	20.9.1.3 CID-allocation examples
509	20.9.1.4 An approach to implementing CID allocation
510	20.9.2 Specifications
513	20.10 Scan Selection Directives 20.10.1 Description 20.10.1.1 Overview
514	20.10.1.2 SSD format 20.10.1.3 SSD effects on STL Group Membership
515	20.10.1.4 Enabling SSD processing 20.10.1.5 SSD processing
518	20.10.1.6 Conditional SSD execution 20.10.1.7 SSD interaction with other controller functions 20.10.1.8 SSD State Machine
520	20.10.1.9 SSD states allowing Scan Group Membership
521	20.10.1.9.1 Using SSDs to create Series and Star-Equivalent Scans 20.10.1.9.2 Examples of SSD use
526	20.10.1.10 An approach to implementing the SSD function
528	20.10.2 Specifications
532	20.11 Scan Topology Training Sequence 20.11.1 Description 20.11.1.1 Overview 20.11.1.2 Topology Register Function
533	20.11.1.3 Use cases 20.11.1.3.1 Operation with a single TAP.7 Branch
534	20.11.1.3.2 Operation with more than one TAP.7 Branch 20.11.1.4 Scan-path characteristics used to determine the scan topology
535	20.11.1.5 Scan Topology Training Command Sequence
536	20.11.1.5.1 Connectivity test 20.11.1.5.2 Continuity test
537	20.11.2 Specifications 20.12 Managing STL Group Membership 20.12.1 Description 20.12.1.1 Factors affecting group membership 20.12.1.2 An approach to implementing CLTAPC selection with T3 and above classes
539	20.12.2 Specifications
541	20.13 RSU operation 20.13.1 Description
542	20.13.2 Specifications 20.14 Programming considerations
543	21. Advanced concepts 21.1 Architecture
544	21.2 Advanced capabilities 21.2.1 Mandatory and optional capabilities
545	21.2.2 Online and Offline operation 21.2.3 Interoperability with T0–T3 TAP.7s 21.2.4 Interoperability with T4 and above TAP.7s
546	21.3 Comparing the Standard and Advanced Protocols 21.4 APU functions 21.4.1 Conceptual view
547	21.4.2 Bypass Function
548	21.4.3 Scan Function
549	21.4.4 Transport Function
551	21.4.5 Bypass/Scan/Control Function interactions 21.5 APU interfaces 21.5.1 TAP
552	21.5.2 EPU 21.5.3 DCC
554	21.6 APU function/Operating State relationships 21.6.1 Operating State/function relationships
555	21.6.2 APU Operating State changes
556	21.6.3 Example operating state sequences
558	21.7 TAPC state/packet relationships 21.7.1 TAPC state and packet sequence relationships
560	21.7.2 Constructing packet sequences
561	21.7.3 Packet combinations/TAPC state relationships 21.7.4 Scheduling of packets
563	21.8 User’s and implementer’s views of the Advanced Protocol 21.8.1 User’s view
564	21.8.2 Implementer’s view 21.9 An approach to implementing APU Operating State scheduling
566	21.10 Structure of the clauses describing T4 and above TAP.7s
568	22. APU Scan Packets 22.1 CPs 22.2 SPs 22.2.1 Conceptual view of an SP
569	22.2.2 SP format
570	22.2.3 SP content 22.2.3.1 Header Element content 22.2.3.2 Payload Element content
571	22.2.3.3 Delay Element content
572	22.2.4 Types of output bit-frame transactions
573	22.3 SPs that advance the TAPC state
574	22.4 TPs 22.4.1 Conceptual view of a TP 22.4.2 TP format
576	22.4.3 Content 22.5 APU state diagram
578	22.6 An approach to implementing packet scheduling 22.6.1 Pipelining and its effects 22.6.2 SP Element scheduling
579	22.6.3 TP Element scheduling
580	23. T4 TAP.7 23.1 Introduction 23.2 Deployment
581	23.3 Capabilities 23.3.1 Inherited 23.3.2 New
582	23.4 Register and command portfolio 23.4.1 Description 23.4.1.1 General information 23.4.1.2 Register acronyms 23.4.1.3 Effect of a Long-Form Selection Sequence
583	23.4.1.4 New register descriptions 23.4.1.4.1 Auxiliary Pin Function Control (APFC) Register 23.4.1.4.2 Delay Control (DLYC) Register 23.4.1.4.3 Ready Control (RDYC) Register 23.4.1.4.4 Sample Using Rising Edge (SREDGE) Register 23.4.1.4.5 Scan Format (SCNFMT) Register 23.4.1.4.6 System Test Clock Duty Cycle (STCKDC) Register
584	23.4.2 Specifications
586	23.5 Configurations 23.5.1 Description 23.5.2 Specifications
587	23.6 Start-up behavior 23.6.1 Description 23.6.2 Specifications
588	23.7 Scan formats 23.7.1 Description 23.7.1.1 Overview
590	23.7.1.2 Addition of optional scan formats 23.7.1.3 Influences on scan format definition 23.7.1.4 Performance and flexibility tradeoffs
591	23.7.1.5 Comparing the scan formats 23.7.1.5.1 MScan 23.7.1.5.2 OScan
592	23.7.1.5.3 SScan
593	23.7.2 Specification 23.8 Configuration Faults 23.8.1 Description 23.8.2 Specifications
594	23.9 Increasing STL performance 23.9.1 Description
595	23.9.2 Specifications
596	23.10 Auxiliary Pin Function Control 23.10.1 Description
597	23.10.2 Specifications 23.11 Sample Using Rising Edge 23.11.1 Description
598	23.11.2 Specifications 23.12 System and EPU TMS signal values 23.12.1 Description
599	23.12.2 Specifications
600	23.13 System and EPU TDI signal values 23.13.1 Description
601	23.13.2 Specifications
602	23.14 RDY bit values 23.14.1 Description
603	23.14.2 Specifications
604	23.15 TDO bit values 23.15.1 Description
605	23.15.2 Specifications 23.16 Advanced Protocol effects on the EPU/CLTAPC relationship 23.16.1 Description 23.16.2 Specifications 23.17 SSD detection 23.17.1 Description 23.17.2 Specifications
606	23.18 Programming considerations 23.19 An approach to implementing a TAP.7 Controller with maximum performance
608	24. MScan Scan Format 24.1 Capabilities 24.1.1 Primary purpose 24.1.2 Application types supported
609	24.1.3 Important characteristics 24.2 High-level operation
610	24.3 Scan Packet content 24.3.1 Description 24.3.2 Specifications 24.4 Payload Element 24.4.1 Description 24.4.1.1 Format
611	24.4.1.2 Relationship to EPU signals
612	24.4.1.3 RDY bits
614	24.4.2 Specification 24.5 Delay Element 24.5.1 Description 24.5.1.1 Format
615	24.5.1.2 Delay Element Directives 24.5.1.3 Uses
616	24.5.2 Specifications
617	24.6 Advancing the TAPC state 24.6.1 Description
618	24.6.2 Specifications 24.7 CID allocation 24.7.1 Description
620	24.7.2 Specifications 24.8 Increasing STL performance with the MScan Scan Format 24.9 An approach to implementing the MScan Scan Format 24.9.1 Payload State Machine
622	24.9.2 Ready State Machine
623	24.9.3 Delay State Machine
624	24.10 Where to find examples
625	25. OScan Scan Formats 25.1 Capabilities 25.1.1 Primary purpose 25.1.2 Application types supported
626	25.1.3 Important characteristics 25.2 High-level operation
627	25.3 Scan Packet content 25.3.1 Description 25.3.2 Specifications
628	25.4 Payload Element 25.4.1 Description 25.4.1.1 Format
629	25.4.1.2 Optimizations
630	25.4.1.3 Relationship to EPU signals
634	25.4.1.4 Input bit-frame 25.4.1.5 Drive types
635	25.4.1.6 RDY bits
636	25.4.2 Specifications
637	25.5 Delay Element
638	25.6 Advancing the TAPC state 25.6.1 Description
640	25.6.2 Specifications
641	25.7 CID allocation 25.7.1 Description 25.7.2 Specifications 25.8 Increasing STL performance with OScan Scan Formats
642	25.9 An approach to implementing OScan Scan Formats 25.9.1 Payload State Machine
644	25.9.2 Shift Progress flag
645	25.9.3 CSM and SSM activation 25.9.4 RDY State Machine
646	25.9.5 TAP advance 25.10 Where to find examples
647	26. SScan Scan Formats 26.1 Capabilities 26.1.1 Primary purpose
648	26.1.2 Application types supported
649	26.1.3 Control Segments
650	26.1.4 Data Segments 26.1.5 Stall profiles
651	26.1.6 Important characteristics 26.2 High-level operation 26.2.1 Overview
652	26.2.2 Segments and their use 26.2.2.1 Description 26.2.2.1.1 Use with a TAP.1-like component
653	26.2.2.1.2 Use with a DMA or FIFO component
654	26.2.2.1.3 Use with a direct-access data-rate-dependent component 26.2.2.1.4 Use with a buffered TDI/TMS component
655	26.2.2.1.5 Utilizing the same scan format for two applications types
656	26.2.2.2 Specifications 26.3 Scan Packet content 26.3.1 Description
657	26.3.2 Specifications
658	26.4 Header Element 26.4.1 Description 26.4.2 Specifications
659	26.5 Payload Element 26.5.1 Description 26.5.1.1 Factors determining payload content
661	26.5.1.2 Optimizations
664	26.5.1.3 Input bit-frame
667	26.5.1.4 Output bit-frame 26.5.1.4.1 Content 26.5.1.4.2 SScan0/1 output-only segments
668	26.5.1.4.3 SScan2/3 output-only segments
672	26.5.2 Specifications
674	26.6 Delay Element
675	26.7 Packet sequences and factors influencing them 26.7.1 Description
677	26.7.2 Specifications
678	26.8 Advancing the TAPC state 26.8.1 Description 26.8.1.1 SP followed by a CP 26.8.1.2 Control Segments 26.8.1.3 Data Segments
682	26.8.2 Specifications 26.9 CID allocation 26.9.1 Description 26.9.2 Specifications
683	26.10 Increasing STL performance with SScan Scan Formats 26.11 An approach to implementing SScan Scan Formats 26.11.1 Payload State Machine
684	26.11.2 Escape Detection State Machine
685	26.11.3 Shift Progress flag
686	26.11.4 TAP advance 26.11.5 Additional entry point loads for output-only segments
687	26.11.6 Header Register
688	26.11.7 Timing diagrams
690	26.12 Where to find examples
691	27. T5 TAP.7 27.1 Introduction
692	27.2 Deployment
693	27.3 Capabilities 27.3.1 Inherited 27.3.2 New 27.4 Register and command portfolio 27.4.1 Description 27.4.1.1 General information
694	27.4.1.2 Register acronyms 27.4.1.3 Effect of a Long-Form Selection Sequence 27.4.1.4 Transport protocol revision (TPPREV) register
695	27.4.1.5 Transport states (TPST) 27.4.1.6 Data Element length (TP_DELN) 27.4.1.7 Physical Data Channel to Logical Data Channel association (PDCx_LCA) 27.4.1.8 Physical Data Channel selected (PDCx_SEL) 27.4.1.9 Physical Data Channel DCC selection (PDCx_DCC) 27.4.1.10 Physical Data Channel DCC Control Registers (PDCx_DCCy_CRz)
696	27.4.2 Specifications
700	27.5 Configurations 27.5.1 Description
701	27.5.2 Specifications
702	27.6 Start-up behavior 27.6.1 Description 27.6.2 Specifications 27.7 Configuration Faults 27.7.1 Description 27.7.2 Specifications
703	27.8 Enabling transport 27.8.1 Description 27.8.2 Specifications
704	27.9 Transport Packet composition 27.9.1 Operations
705	27.9.2 Directive, Register, and Data Elements 27.10 Directive Elements 27.10.1 Description 27.10.1.1 Overview
706	27.10.1.2 Directive Element acronyms 27.10.1.3 Surrounding context of directives
707	27.10.1.4 Directive/transport building block relationships
708	27.10.1.5 Directive encoding
709	27.10.1.6 Directive types
710	27.10.1.6.1 Unconditional Directives 27.10.1.6.2 Reset Directives 27.10.1.6.3 Selection Directives
711	27.10.1.6.4 Conditional Directives
712	27.10.1.6.5 Transfer Directives 27.10.2 Specifications
716	27.11 Register Elements 27.11.1 Description 27.11.1.1 Overview 27.11.1.2 Register Element length 27.11.1.3 Transfer direction 27.11.1.4 Summary of Register Element characteristics
717	27.11.2 Specifications 27.12 Data Elements 27.12.1 Description 27.12.1.1 Overview 27.12.1.2 Data Element length 27.12.1.3 Transfer direction
718	27.12.1.4 Utilization and generation of data 27.12.1.5 Operation with single and multiple clients
719	27.12.1.6 Summary of Data Element characteristics 27.12.2 Specifications
720	27.13 Selection of control and data targets
721	27.14 Data Channel Client functions 27.14.1 Description 27.14.1.1 Initializing a Data Channel Client 27.14.1.2 Orderly shutdown of a transfer
722	27.14.1.3 Effects of Online/Offline operation on the Transport Function
723	27.14.2 Specifications 27.15 Partitioning of the Transport Control Function 27.15.1 Building blocks
725	27.15.2 Directive/register/operational relationships
726	27.16 Programming considerations 27.16.1 Managing transport with the DTS 27.16.2 Single and multi-client data exchanges 27.16.3 Bandwidth allocation 27.16.4 Common and uncommon operations performed with directives
727	27.16.5 Dynamic source/destination changes
728	27.16.6 Transfer alignment characteristics 27.17 Aspects of transport not covered by this specification
729	28. Transport operation and interfaces 28.1 Introduction 28.2 TAP interface 28.2.1 TPA state flow
730	28.2.2 Directive Element characteristics 28.2.2.1 Description 28.2.2.2 Specifications
732	28.2.3 Register Element characteristics 28.2.3.1 Description 28.2.3.1.1 Format, timing, and TMSC signal drive characteristics 28.2.3.1.2 Register Element length
733	28.2.3.1.3 Register Element content
734	28.2.3.2 Specifications
735	28.2.4 Data Element characteristics 28.2.4.1 Description 28.2.4.1.1 Format, timing, and TMSC signal drive characteristics
736	28.2.4.1.2 Data Element length
737	28.2.4.1.3 Data Element content
738	28.2.4.1.4 Drive characteristics 28.2.4.1.5 Multi-client data transfers
739	28.2.4.1.6 Data Element alignment with the data that is transported 28.2.4.2 Specifications
740	28.3 Transport State Machine 28.3.1 Description 28.3.1.1 Conceptual view
742	28.3.1.2 TSM operation
743	28.3.1.3 Scheduling a TP
745	28.3.1.4 Starting/restarting directive processing 28.3.1.5 Completing a TP
746	28.3.2 Specifications
747	28.4 PDCx/DCC interface 28.4.1 Description
748	28.4.1.1 Signal functions 28.4.1.2 Signal descriptions
750	28.4.1.3 Signal use
754	28.4.2 Specifications 28.5 Five-bit directives 28.5.1 Description 28.5.2 Specifications
756	28.6 Eight-bit directives 28.6.1 Description
757	28.6.2 Specifications
758	28.7 12-bit directives 28.7.1 Description 28.7.2 Specifications
761	28.8 DCC interface operation 28.8.1 Basic capability
762	28.8.2 Pipelining register dcc_rdo signaling 28.8.3 Pipelining dcc_ddo and dcc_cor signaling
763	28.9 An approach to implementing the Transport Function 28.9.1 Overview
764	28.9.2 The Transport State Machine
765	28.9.3 Multi-use register bits 28.9.3.1 Input configurations
766	28.9.3.2 Transport Packet processing 28.9.3.2.1 Directive processing 28.9.3.2.2 Data Element processing
767	28.9.3.2.3 12-bit directive processing (other than TP_CRR and TP_CRW) 28.9.3.2.4 TP_CRR and TP_CRW Directive processing
768	28.9.3.3 TSM state/register value relationships
771	28.9.3.4 Transport output and DCR input selection
773	28.9.3.5 TP activity examples
778	29. Test concepts 29.1 Introduction 29.2 Interoperability
779	29.3 Construction of the unit under test 29.4 Background (IEEE 1149.1 paradigm)
780	29.4.1 Topology 29.4.2 Scan-state sequencing
781	29.5 Implications for test applications arising from this standard 29.5.1 Divergences versus IEEE Std 1149.1
782	29.5.2 Accommodation/resolution of divergences versus IEEE Std 1149.1 29.6 Test example—a narrative
783	29.7 Describing the unit under test
784	29.8 Documentation model
785	29.9 Considerations for large-system applications
787	30. Documenting IEEE 1149.7 test endpoints (BSDL.7) 30.1 Introduction
788	30.2 Conventions 30.3 Purpose of BSDL.7 30.4 Scope of BSDL.7
789	30.5 Expectations of a BSDL.7 parser 30.6 Relationship of BSDL.7 to BSDL.1 30.6.1 Description
790	30.6.2 Specifications 30.7 Lexical elements of BSDL.7 30.7.1 Description 30.7.2 Specifications 30.8 BSDL.7 reserved words 30.8.1 Description 30.8.2 Specifications
791	30.9 Components of a BSDL.7 description 30.9.1 Description 30.9.2 Specifications 30.10 The entity description (BSDL.7) 30.10.1 Overall structure of the entity description (BSDL.7) 30.10.1.1 Syntax and content 30.10.1.1.1 Description
792	30.10.1.1.2 Specifications
793	30.10.1.2 Semantic checks 30.10.1.2.1 Description 30.10.1.2.2 Specifications 30.10.2 Standard use statement (BSDL.7) 30.10.2.1 Syntax and content 30.10.2.1.1 Description
794	30.10.2.1.2 Specifications 30.10.2.2 Examples
795	30.10.3 Version control 30.10.3.1 Syntax and content 30.10.3.1.1 Description 30.10.3.1.2 Specifications 30.10.4 Component conformance statement (BSDL.7) 30.10.4.1 Syntax and content 30.10.4.1.1 Description
796	30.10.4.1.2 Specifications 30.10.4.2 Examples 30.10.4.3 Semantic checks 30.10.5 Scan port identification (BSDL.7) 30.10.5.1 Syntax and content 30.10.5.1.1 Description
797	30.10.5.1.2 Specifications 30.10.5.2 Examples
799	30.10.5.3 Semantic checks 30.10.5.3.1 Description 30.10.5.3.2 Specifications
800	30.10.6 Compliance enable description (BSDL.7) 30.10.6.1 Syntax and content 30.10.6.1.1 Description 30.10.6.1.2 Specifications 30.10.6.2 Examples
801	30.10.6.3 Semantic checks 30.10.6.3.1 Description 30.10.6.3.2 Specifications 30.10.7 Device identification register description (BSDL.7) 30.10.7.1 Syntax and content 30.10.7.1.1 Description 30.10.7.1.2 Specifications 30.10.7.2 Examples
802	30.10.7.3 Semantic checks 30.10.7.3.1 Description 30.10.7.3.2 Specifications 30.10.8 Configuration register description (BSDL.7) 30.10.8.1 Syntax and content 30.10.8.1.1 Description 30.10.8.1.2 Specifications 30.10.8.2 Examples
803	30.10.8.3 Semantic checks 30.10.8.3.1 Description 30.10.8.3.2 Specifications
804	30.11 The Standard BSDL.7 Package STD_1149_7_2009 30.11.1 Description 30.11.2 Specifications 30.12 A typical application of BSDL.7
807	31. Documenting IEEE 1149.7 test modules (HSDL.7) 31.1 Introduction 31.2 Conventions
808	31.3 Purpose of HSDL.7 31.4 Scope of HSDL.7
809	31.5 Expectations of an HSDL.7 parser 31.6 Relationship of HSDL.7 to BSDL.7 (and BSDL.1) 31.6.1 Description
810	31.6.2 Specifications 31.7 Lexical elements of HSDL.7 31.7.1 Description 31.7.2 Specifications 31.8 HSDL.7 reserved words 31.8.1 Description 31.8.2 Specifications 31.9 Components of an HSDL.7 description 31.9.1 Description
811	31.9.2 Specifications 31.10 The entity description (HSDL.7) 31.10.1 Overall structure of the entity description (HSDL.7) 31.10.1.1 Syntax and content 31.10.1.1.1 Description 31.10.1.1.2 Specifications
812	31.10.1.2 Semantic checks 31.10.1.2.1 Description 31.10.1.2.2 Specifications 31.10.2 Module standard use statement (HSDL.7) 31.10.2.1 Syntax and content 31.10.2.1.1 Description
813	31.10.2.1.2 Specifications
814	31.10.2.2 Examples 31.10.3 Version control 31.10.3.1 Syntax and content 31.10.3.1.1 Description 31.10.3.1.2 Specifications
815	31.10.4 Module component conformance statement (HSDL.7) 31.10.4.1 Syntax and content 31.10.4.1.1 Description 31.10.4.1.2 Specifications 31.10.4.2 Examples 31.10.4.3 Semantic checks
816	31.10.5 Module package pin mappings (HSDL.7) 31.10.5.1 Syntax and content 31.10.5.1.1 Description 31.10.5.1.2 Specifications 31.10.5.2 Examples 31.10.5.3 Semantic checks 31.10.5.3.1 Description 31.10.5.3.2 Specifications 31.10.6 Module scan port identification (HSDL.7) 31.10.6.1 Syntax and content 31.10.6.1.1 Description
817	31.10.6.1.2 Specifications 31.10.6.2 Examples
818	31.10.6.3 Semantic checks 31.10.6.3.1 Description 31.10.6.3.2 Specifications
819	31.10.7 Module members declaration (HSDL.7) 31.10.7.1 Syntax and content 31.10.7.1.1 Description
820	31.10.7.1.2 Specifications
821	31.10.7.2 Examples
822	31.10.7.3 Semantic checks 31.10.7.3.1 Description 31.10.7.3.2 Specifications
823	31.11 The Standard HSDL.7 Package STD_1149_7_2009_module 31.11.1 Description 31.11.2 Specifications 31.12 Applications of HSDL.7 31.12.1 HSDL.7 for IEEE 1149.1 serial connection using one TMS signal
825	31.12.2 HSDL.7 for IEEE 1149.1 connection in two paralleled serial chains
826	31.12.3 HSDL.7 for a basic Star Scan Topology
827	31.12.4 HSDL.7 for a basic hierarchical topology
829	31.12.5 A typical application of HSDL.7
831	Annex A (informative) IEEE 1149.1 reference material
835	Annex B (informative) Scan examples in timing diagram form B.1 MScan and OScan SP types
836	B.2 MScan and OScan transactions B.2.1 MScan transaction
838	B.2.2 OScan0 transaction
839	B.2.3 OScan1 transaction
840	B.2.4 OScan2 transaction
841	B.2.5 OScan3 transaction
842	B.2.6 OScan4 transaction
843	B.2.7 OScan5 transaction
844	B.2.8 OScan6 transaction
846	B.2.9 OScan7 transaction
847	B.3 SScan transactions
848	B.3.1 SScan0 transaction
851	B.3.2 SScan1 transaction
854	B.3.3 SScan2 transaction
857	B.3.4 SScan3 transaction
860	B.4 BDX and CDX Transport Packet examples
862	Annex C (informative) Scan examples in tabular form C.1 Overview C.2 MScan and OScan SP types
877	C.3 SScan SP types
904	Annex D (informative) Programming considerations D.1 Overview D.2 DTS’ view of TAPs D.2.1 Technology branches
905	D.2.2 Power-management RSU combinations
907	D.2.3 TAP.7 Controller deselection and selection
908	D.2.4 Start-up versus steady-state operation
909	D.2.5 Start-up
910	D.2.6 Initialization requirements D.2.6.1 Initial state D.2.6.2 Factors influencing initialization D.2.6.3 Initialization function
911	D.2.6.4 Reset Escape
912	D.2.6.5 Reset TAP.7 Controllers without an RSU D.2.6.6 Power-up TAP.7 Controllers that are un-powered D.2.6.7 Placing a TAP.7 Controller Online that is Offline-at-Start-up
916	D.2.7 Scan Topology Training
917	D.3 Scan topology interrogation
918	D.3.1 Series Branch interrogation D.3.1.1 Series characteristics used for interrogation
919	D.3.1.2 Interrogation process
921	D.3.1.3 Configuration Register reads
922	D.3.1.4 Determining whether a Series Branch is selectable D.3.1.5 Quick determination of TAP types in a Series Branch
923	D.3.2 Star-4 Branch interrogation D.3.2.1 Information provided D.3.2.2 Interrogation process
927	D.3.3 Star-2 Branch interrogation D.3.3.1 Information provided D.3.3.2 Interrogation process
930	D.4 Establishing TAP.7 operating conditions D.5 CID management
931	D.6 Managing simultaneous debug actions D.7 Operations to avoid with a Star-4 Scan Topology D.7.1 The use of the JScan0–JScan2 Scan Formats D.7.2 The selection of CLTAPCs of TAP.7 Controllers allocated the same CID
932	D.8 Using a T5 TAP.7 D.8.1 Setup and use of the Transport Function D.8.2 Sharing the use of a Logical Data Channel D.8.3 Transferring data with Transport Packet Data Payloads
933	Annex E (informative) Recommended electrical characteristics
934	Annex F (informative) Connectivity/electrical recommendations F.1 Overview F.1.1 General information F.1.2 Factors affecting reliable operation
935	F.1.3 Factors affecting link performance
936	F.2 Physical connection topologies considered
937	F.3 Termination schemes considered
939	F.4 Chip considerations F.4.1 SOC input conditioning
940	F.4.2 Signal driver rise and fall times
942	F.4.3 Clock-to-output delays F.4.4 Supply and buffer impedances F.4.5 Additional chip considerations related to multi-TAPC topologies F.5 Board considerations F.5.1 Signaling requiring a termination scheme
943	F.5.1.1 Lumped load F.5.1.2 Distributed load F.5.1.3 Classifying a load
944	F.5.1.4 Transmission-line impedance
945	F.5.2 Impedance discontinuities/symmetry
948	F.5.3 Transmission-line construction F.5.3.1 Uniformity of transmission-line impedance F.5.3.2 Proper construction
950	F.5.3.3 Improper construction F.5.3.4 Connector treatment F.5.4 Choosing a connection configuration
951	F.5.5 Termination schemes with simple configurations F.5.5.1 Series termination F.5.5.1.1 Overview
952	F.5.5.1.2 Challenges in series termination F.5.5.1.3 Benefits of using series termination F.5.5.2 Parallel termination F.5.5.2.1 Overview
954	F.5.5.2.2 Challenges in using parallel termination
955	F.5.5.2.3 Benefits of using parallel termination F.5.5.3 Parallel AC termination F.5.5.3.1 Overview
957	F.5.5.3.2 Challenges in using parallel AC termination
958	F.5.5.3.3 Benefits of using parallel AC termination F.5.6 Effects of transmission-line length on operating frequency
959	F.5.7 Capacitive load isolation and input pin low-pass filtering F.5.8 DTS and chip models
960	F.5.9 Additional board considerations related to multi-TAPC topologies F.6 System considerations for supporting Keeper bias (K bias) in multi-TAPC topologies F.6.1 K bias considerations at the chip and board level
962	F.6.2 K bias considerations for embedded TAPC topologies
964	F.7 DTS considerations F.7.1 Source impedance
965	F.7.2 Input capacitance isolation F.7.2.1 DTS output levels with parallel terminated target topologies F.7.2.2 DTS output edge rates
966	F.7.2.3 High-speed, high-current, low-voltage configurable edge-rate drivers F.7.2.4 Low-voltage, high-current fixed slow edge-rate drive translator
968	F.7.2.5 In-system DTS considerations F.7.2.5.1 Output buffer impedance F.7.2.5.2 Power considerations F.7.2.5.3 Signal edge rates F.8 Point-to-Point configuration F.8.1 Model
969	F.8.2 Unidirectional signaling F.8.2.1 Series termination F.8.2.2 Parallel AC termination
970	F.8.3 Bidirectional signaling
972	F.9 Line configuration of a transmission line F.9.1 Model
974	F.9.2 Unidirectional signaling
979	F.9.2.1 Parallel AC termination
981	F.9.2.2 Parallel termination F.9.2.3 Summary F.9.3 Bidirectional signaling
984	F.9.3.1 Four loads
987	F.9.3.2 Eight loads
990	F.10 T configuration of a transmission line F.10.1 Model
993	F.10.2 Unidirectional signaling
994	F.10.3 Bidirectional signaling
998	F.11 X configuration of a transmission line F.11.1 Model
1000	F.11.2 Unidirectional signaling
1003	F.11.3 Bidirectional signaling
1009	F.12 XT configuration of a transmission line F.12.1 Model
1010	F.12.2 Unidirectional signaling
1012	F.12.3 Bidirectional signaling
1018	F.13 Recommendations F.13.1 Summary
1019	F.13.2 Connectivity/termination scheme
1021	F.13.3 Termination scheme/capacitive load isolation/signal relationships
1023	F.13.4 Utilizing board design tools and simulation
1024	Annex G (informative) Utilizing SScan Scan Formats
1028	Annex H (informative) The RTCK signal
1036	Annex I (informative) Bibliography
1037	Index

Additional information

Standard Title	IEEE Approved Draft Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture
Published Code	IEEE
Publication Date	2022

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