IEEE P802.3df 2024

$106.71

IEEE Approved Draft Standard for Ethernet Amendment 9: Media Access Control Parameters for 800 Gb/s and Physical Layers and Management Parameters for 400 Gb/s and 800 Gb/s Operation

Published By	Publication Date	Number of Pages
IEEE	2024

Guaranteed Safe Checkout

Category: IEEE

If you have any questions, feel free to reach out to our online customer service team by clicking on the bottom right corner. We’re here to assist you 24/7.
Email:[email protected]

Description

Amendment Standard – Active – Draft. This amendment includes changes to IEEE Std 802.3-2022 and adds Clause 169 through Clause 173 and Annex 173A. The amendment adds MAC parameters, Physical Layers, and management parameters for the transfer of IEEE 802.3 format frames at 400 Gb/s and 800 Gb/s.

PDF Catalog

PDF Pages	PDF Title
4	Important Notices and Disclaimers Concerning IEEE Standards Documents
8	Participants
11	Introduction
15	Contents
31	1. Introduction 1.1 Overview 1.1.3 Architectural perspectives 1.1.3.2 Compatibility interfaces 1.4 Definitions
34	1.5 Abbreviations
35	4. Media Access Control 4.4 Specific implementations 4.4.2 MAC parameters
36	21. Introduction to 100 Mb/s baseband networks, type 100BASE-T 21.6 Protocol implementation conformance statement (PICS) proforma 21.6.2 Abbreviations and special symbols
37	30. Management 30.3 Layer management for DTEs 30.3.2 PHY device managed object class 30.3.2.1 PHY device attributes 30.3.2.1.2 aPhyType 30.3.2.1.3 aPhyTypeList 30.5 Layer management for medium attachment units (MAUs) 30.5.1 MAU managed object class 30.5.1.1 MAU attributes 30.5.1.1.2 aMAUType
39	30.6 Management for link Auto-Negotiation 30.6.1 Auto-Negotiation managed object class 30.6.1.1 Auto-Negotiation attributes 30.6.1.1.5 aAutoNegLocalTechnologyAbility
41	45. Management Data Input/Output (MDIO) Interface 45.2 MDIO Interface registers 45.2.1 PMA/PMD registers
42	45.2.1.1 PMA/PMD control 1 register (Register 1.0) 45.2.1.1.3 Speed selection (1.0.13, 1.0.6, 1.0.5:2)
43	45.2.1.6 PMA/PMD control 2 register (Register 1.7)
44	45.2.1.7 PMA/PMD status 2 register (Register 1.8) 45.2.1.7.4 Transmit fault (1.8.11)
45	45.2.1.7.5 Receive fault (1.8.10)
46	45.2.1.8 PMD transmit disable register (Register 1.9)
47	45.2.1.22 400G PMA/PMD extended ability register (Register 1.24) 45.2.1.22.1aa 400GBASE-DR4-2 ability (1.24.14)
48	45.2.1.23 PMA/PMD extended ability 2 (Register 1.25) 45.2.1.23.a 800G capable (1.25.1)
49	45.2.1.60b 800G PMA/PMD ability (Register 1.73) 45.2.1.60b.1 800G PMA remote loopback ability (1.73.15) 45.2.1.60b.2 800GBASE-DR8-2 ability (1.73.5) 45.2.1.60b.3 800GBASE-DR8 ability (1.73.4)
50	45.2.1.60b.4 800GBASE-SR8 ability (1.73.3) 45.2.1.60b.5 800GBASE-VR8 ability (1.73.2) 45.2.1.60b.6 800GBASE-CR8 ability (1.73.1) 45.2.1.60b.7 800GBASE-KR8 ability (1.73.0)
51	45.2.1.139 PMA precoder control Tx output (Register 1.600) 45.2.1.139.a Lane 7 Tx output precoder enable (1.600.7) 45.2.1.139.b Lane 6 Tx output precoder enable (1.600.6) 45.2.1.139.c Lane 5 Tx output precoder enable (1.600.5) 45.2.1.139.d Lane 4 Tx output precoder enable (1.600.4)
52	45.2.1.140 PMA precoder control Rx input (Register 1.601) 45.2.1.140.a Lane 7 Rx input precoder enable (1.601.7) 45.2.1.140.b Lane 6 Rx input precoder enable (1.601.6) 45.2.1.140.c Lane 5 Rx input precoder enable (1.601.5) 45.2.1.140.d Lane 4 Rx input precoder enable (1.601.4)
53	45.2.1.141 PMA precoder control Rx output (Register 1.602) 45.2.1.141.a Lane 7 Rx output precoder enable (1.602.7) 45.2.1.141.b Lane 6 Rx output precoder enable (1.602.6) 45.2.1.141.c Lane 5 Rx output precoder enable (1.602.5) 45.2.1.141.d Lane 4 Rx output precoder enable (1.602.4)
54	45.2.1.141.e Lane 3 Rx output precoder enable (1.602.3) 45.2.1.141.f Lane 2 Rx output precoder enable (1.602.2) 45.2.1.142 PMA precoder control Tx input (Register 1.603) 45.2.1.142.a Lane 7 Tx input precoder enable (1.603.7) 45.2.1.142.b Lane 6 Tx input precoder enable (1.603.6)
55	45.2.1.142.c Lane 5 Tx input precoder enable (1.603.5) 45.2.1.142.d Lane 4 Tx input precoder enable (1.603.4) 45.2.1.142.e Lane 3 Tx input precoder enable (1.603.3) 45.2.1.142.f Lane 2 Tx input precoder enable (1.603.2) 45.2.1.144 PMA precoder request Rx input status (Register 1.605)
56	45.2.1.144.a Lane 7 Rx input precoder request status (1.605.7) 45.2.1.144.b Lane 6 Rx input precoder request status (1.605.6) 45.2.1.144.c Lane 5 Rx input precoder request status (1.605.5) 45.2.1.144.d Lane 4 Rx input precoder request status (1.605.4) 45.2.1.144.e Lane 3 Rx input precoder request status (1.605.3) 45.2.1.144.f Lane 2 Rx input precoder request status (1.605.2)
57	45.2.1.145 PMA precoder request Tx input status (Register 1.606) 45.2.1.145.a Lane 7 Tx input precoder request status(1.606.7) 45.2.1.145.b Lane 6 Tx input precoder request status(1.606.6) 45.2.1.145.c Lane 5 Tx input precoder request status(1.606.5) 45.2.1.145.d Lane 4 Tx input precoder request status(1.606.4)
58	45.2.1.145.e Lane 3 Tx input precoder request status(1.606.3) 45.2.1.145.f Lane 2 Tx input precoder request status(1.606.2) 45.2.1.161 BASE-R PAM4 PMD training LP control, lane 0 through lane 73 registers (Register 1.1120 through 1.11273) 45.2.1.163 BASE-R PAM4 PMD training LP status, lane 0 through lane 73 registers (Register 1.1220 through 1.12273) 45.2.1.165 BASE-R PAM4 PMD training LD control, lane 0 through lane 73 registers (Register 1.1320 through 1.13273)
59	45.2.1.167 BASE-R PAM4 PMD training LD status, lane 0 through lane 73 registers (Register 1.1420 through 1.14273) 45.2.1.168 PMD training pattern lanes 0 through 73 (Register 1.1450 through 1.14573)
60	45.2.3 PCS registers
61	45.2.3.4 PCS speed ability (Register 3.4) 45.2.3.4.11 800G capable (3.4.10) 45.2.3.19 BASE-R PCS test-pattern control register (Register 3.42) 45.2.3.25 Multi-lane BASE-R PCS alignment status 3 registers 3 through 5 (Register 3.52, 3.53, 3.54)
62	45.2.3.25.1 Lane 0 aligned (3.52.0) 45.2.3.25.2 Lanes 1 through 31 aligned (bits 3.52.1 through 3.54.7)
63	45.2.3.48a RS-FEC codeword counter register (Register 3.300, 3.301, 3.302)
64	45.2.3.48b RS-FEC codeword error bin registers 1 through 15 (Registers 3.340 through 3.369) 45.2.3.49 Lane 0 mapping register (Register 3.400)
65	45.2.3.50 Lanes 1 through 31 19 mapping registers (Registers 3.401 through 3.431 419) 45.2.3.58 PCS FEC symbol error counter lane 0 (Register 3.600, 3.601) 45.2.3.59 PCS FEC symbol error counter lane 1 through 31 15 (Registers 3.602 through 3.663 631) 45.2.3.60 PCS FEC control register (Register 3.800) 45.2.3.60.1 PCS FEC degraded SER enable (3.800.2) 45.2.3.60.2 PCS FEC bypass indication enable (3.800.1)
66	45.2.3.61 PCS FEC status register (Register 3.801) 45.2.3.61.1 Local degraded SER received (3.801.6) 45.2.3.61.2 Remote degraded SER received (3.801.5) 45.2.3.61.3 PCS FEC degraded SER (3.801.4) 45.2.3.61.4 PCS FEC degraded SER ability (3.801.3) 45.2.3.61.5 PCS FEC high SER (3.801.2) 45.2.3.61.6 PCS FEC bypass indication ability (3.801.1) 45.2.3.62 PCS FEC corrected codewords counter (Register 3.802, 3.803)
67	45.2.3.63 PCS FEC uncorrected codewords counter (Register 3.804, 3.805) 45.2.3.64 PCS FEC degraded SER activate threshold register (Register 3.806, 3.807) 45.2.3.65 PCS FEC degraded SER deactivate threshold register (Register 3.808, 3.809) 45.2.3.66 PCS FEC degraded SER interval register (Register 3.810, 3.811)
68	45.2.4 PHY XS registers
69	45.2.4.4 PHY XS speed ability (Register 4.4) 45.2.4.4.a 800G capable (4.4.10) 45.2.4.15 Multi-lane BASE-R PHY XS alignment status 3 registers 3 through 5 (Register 4.52, 4.53, 4.54)
70	45.2.4.15.1 Lane 0 aligned (4.52.0) 45.2.4.15.2 Lanes 1 through 31 aligned (bits 4.52.1 through 4.54.7)
72	45.2.4.16a PHY XS RS-FEC codeword counter register (Register 4.300, 4.301, 4.302)
73	45.2.4.16b PHY XS RS-FEC codeword error bin registers 1 through 15 (Registers 4.340 through 4.369) 45.2.4.17 PHY XS lane mapping, lane 0 register (Register 4.400)
74	45.2.4.18 PHY XS lane mapping, lane 1 through lane 31 15 registers (Registers 4.401 through 4.431 415) 45.2.4.19 PHY XS FEC symbol error counter lane 0 (Register 4.600, 4.601) 45.2.4.20 PHY XS FEC symbol error counter lane 1 through 31 15 (Registers 4.602 through 4.663 631) 45.2.4.21 PHY XS FEC control register (Register 4.800) 45.2.4.21.1 PHY XS FEC degraded SER enable (4.800.2)
75	45.2.4.21.2 PHY XS FEC bypass indication enable (4.800.1) 45.2.4.22 PHY XS FEC status register (Register 4.801) 45.2.4.22.a Local degraded SER received (4.801.6) 45.2.4.22.1 Remote degraded SER received (4.801.5)
76	45.2.4.22.2 PHY XS FEC degraded SER (4.801.4) 45.2.4.22.3 PHY XS FEC degraded SER ability (4.801.3) 45.2.4.22.4 PHY XS FEC high SER (4.801.2) 45.2.4.22.5 PHY XS FEC bypass indication ability (4.801.1) 45.2.4.23 PHY XS FEC corrected codewords counter (Register 4.802, 4.803) 45.2.4.24 PHY XS FEC uncorrected codewords counter (Register 4.804, 4.805)
77	45.2.4.25 PHY XS FEC degraded SER activate threshold register (Register 4.806, 4.807) 45.2.4.26 PHY XS FEC degraded SER deactivate threshold register (Register 4.808, 4.809) 45.2.4.27 PHY XS FEC degraded SER interval register (Register 4.810, 4.811)
78	45.2.5 DTE XS registers
79	45.2.5.4 DTE XS speed ability (Register 5.4) 45.2.5.4.a 800G capable (5.4.10) 45.2.5.15 Multi-lane BASE-R PHY DTE alignment status 3 registers 3 through 5 (Register 5.52, 5.53, 5.54)
80	45.2.5.15.1 Lane 0 aligned (5.52.0) 45.2.5.15.2 Lanes 1 through 31 aligned (bits 4.52.1 through 4.54.7)
82	45.2.5.16a DTE XS RS-FEC codeword counter register (Register 5.300, 5.301, 5.302)
83	45.2.5.16b DTE XS RS-FEC codeword error bin registers 1 through 15 (Registers 5.340 through 5.369) 45.2.5.17 DTE XS lane mapping, lane 0 register (Register 5.400)
84	45.2.5.18 DTE XS lane mapping, lane 1 through lane 31 15 registers (Registers 5.401 through 5.431 415) 45.2.5.19 DTE XS FEC symbol error counter lane 0 (Register 5.600, 5.601) 45.2.5.20 DTE XS FEC symbol error counter lane 1 through 31 15 (Registers 5.602 through 5.663 631) 45.2.5.21 DTE XS FEC control register (Register 5.800) 45.2.5.21.1 DTE XS FEC degraded SER enable (5.800.2) 45.2.5.21.2 DTE XS FEC bypass indication enable (5.800.1)
85	45.2.5.22 DTE XS FEC status register (Register 5.801) 45.2.5.22.1 Local degraded SER received (5.801.6) 45.2.5.22.2 Remote degraded SER received (5.801.5) 45.2.5.22.3 DTE XS FEC degraded SER (5.801.4) 45.2.5.22.4 DTE XS FEC degraded SER ability (5.801.3) 45.2.5.22.5 DTE XS FEC high SER (5.801.2) 45.2.5.23 DTE XS FEC corrected codewords counter (Register 5.802, 5.803)
86	45.2.5.24 DTE XS FEC uncorrected codewords counter (Register 5.804, 5.805) 45.2.5.25 DTE XS FEC degraded SER activate threshold register (Register 5.806, 5.807) 45.2.5.26 DTE XS FEC degraded SER deactivate threshold register (Register 5.808, 5.809) 45.2.5.27 DTE XS FEC degraded SER interval register (Register 5.810, 5.811) 45.2.7 Auto-Negotiation registers 45.2.7.12 Backplane Ethernet, BASE-R copper status (Register 7.48) 45.2.7.12.3 Negotiated Port Type (7.48.1, 7.48.2, 7.48.3, 7.48.5, 7.48.6, 7.48.8, 7.48.9, 7.48.10, 7.48.11, 7.48.12, 7.48.13, 7.48.14, 7.48.15, 7.49.0, 7.49.1, 7.49.2, 7.49.3, 7.49.4, 7.49.5, 7.49.7)
87	45.2.7.13 Backplane Ethernet, BASE-R copper status 2 (Register 7.49)
88	69. Introduction to Ethernet operation over electrical backplanes 69.1 Overview 69.1.1 Scope
89	69.1.2 Relationship of Backplane Ethernet to the ISO OSI reference model 69.2 Summary of Backplane Ethernet Sublayers 69.2.1 Reconciliation sublayer and media independent interfaces
90	69.2.3 Physical Layer signaling systems 69.3 Delay constraints 69.5 Protocol implementation conformance statement (PICS) proforma
91	73. Auto-Negotiation for backplane and copper cable assembly 73.2 Relationship to the ISO/IEC Open Systems Interconnection (OSI) reference model
92	73.6 Link codeword encoding 73.6.4 Technology Ability Field
93	73.7 Receive function requirements 73.7.6 Priority Resolution function
94	73.10 State diagrams and variable definitions 73.10.1 State diagram variables
95	73.10.2 State diagram timers
96	90. Ethernet support for time synchronization protocols 90.1 Introduction
98	116. Introduction to 200 Gb/s and 400 Gb/s networks 116.1 Overview 116.1.2 Relationship of 200 Gigabit and 400 Gigabit Ethernet to the ISO OSI reference model 116.1.3 Nomenclature
100	116.1.4 Physical Layer signaling systems
101	116.4 Delay constraints
102	120. Physical Medium Attachment (PMA) sublayer, type 200GBASE-R and 400GBASE-R 120.5 Functions within the PMA 120.5.11 PMA test patterns (optional) 120.5.11.2 Test patterns for PAM4 encoded signals 120.5.11.2.2 PRBS31Q test pattern
103	124. Physical Medium Dependent (PMD) sublayer and medium, type 400GBASE-DR4, 400GBASE-DR4-2, 800GBASE-DR8, and 800GBASE-DR8-2 124.1 Overview
105	124.1.1 Bit error ratio
106	124.2 Physical Medium Dependent (PMD) service interface
107	124.3 Delay and Skew 124.3.1 Delay constraints 124.3.2 Skew constraints 124.3.2.1 Skew constraints for 400GBASE-DR4 and 400GBASE-DR4-2 124.3.2.2 Skew constraints for 800GBASE-DR8 and 800GBASE-DR8-2
108	124.4 PMD MDIO function mapping
109	124.5 PMD functional specifications 124.5.1 PMD block diagram
110	124.5.2 PMD transmit function 124.5.3 PMD receive function 124.5.4 PMD global signal detect function
111	124.5.5 PMD lane-by-lane signal detect function 124.5.8 PMD lane-by-lane transmit disable function (optional) 124.6 Lane assignments
112	124.7 PMD to MDI optical specifications for 400GBASE-DR4, 400GBASE-DR4-2, 800GBASE-DR8, and 800GBASE-DR8-2 124.7.1 400GBASE-DR4 transmitter Transmitter optical specifications
115	124.7.2 400GBASE-DR4 receive Receive optical specifications
117	124.7.3 400GBASE-DR4 illustrative Illustrative link power budget budgets
119	124.8 Definition of optical parameters and measurement methods 124.8.1 Test patterns for optical parameters
121	124.8.5 Transmitter and dispersion eye closure for PAM4 (TDECQ) 124.8.5.1 Channel requirements
122	124.8.5a Transmitter eye closure for PAM4 (TECQ) 124.8.5b Transmitter overshoot and undershoot 124.8.5c Transmitter power excursion 124.8.9 Receiver sensitivity 124.8.9.1 Receiver sensitivity for 400GBASE-DR4
123	124.8.9.2 Receiver sensitivity for 400GBASE-DR4-2, 800GBASE-DR8, and 800GBASE-DR8-2 124.9 Safety, installation, environment, and labeling 124.9.2 Laser safety 124.9.4 Environment
124	124.9.5 Electromagnetic emission 124.11 Characteristics of the fiber optic cabling (channel) 124.11.1 Optical fiber cable
125	124.11.2.1 Connection insertion loss 124.11.3 Medium Dependent Interface (MDI) 124.11.3.1 Optical lane assignments 124.11.3.1.1 Optical lane assignments for 400GBASE-DR4 and 400GBASE-DR4-2
126	124.11.3.1.2 Optical lane assignments for 800GBASE-DR8 and 800GBASE-DR8-2 124.11.3.2 Medium Dependent Interface (MDI) MDI requirements for 400GBASE-DR4 and 400GBASE-DR4-2 124.11.3.3 MDI requirements for 800GBASE-DR8 and 800GBASE-DR8-2
127	124.11a Interoperation between 400GBASE-DR4 and 400GBASE-DR4-2, and between 800GBASE-DR8 and 800GBASE-DR8-2 124.11a.1 Interoperation between 400GBASE-DR4 and 400GBASE-DR4-2 124.11a.2 Interoperation between 800GBASE-DR8 and 800GBASE-DR8-2
128	124.12 Protocol implementation conformance statement (PICS) proforma for Clause 124, Physical Medium Dependent (PMD) sublayer and medium, type 400GBASE-DR4, 400GBASE-DR4-2, 800GBASE-DR8, and 800GBASE-DR8-2 124.12.1 Introduction 124.12.2 Identification 124.12.2.2 Protocol summary
129	124.12.3 Major capabilities/options 124.12.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and medium, type 400GBASE-DR4, 400GBASE-DR4-2, 800GBASE-DR8, and 800GBASE-DR8-2 124.12.4.1 PMD functional specifications 124.12.4.3 PMD to MDI optical specifications for 400GBASE-DR4
130	124.12.4.3a PMD to MDI optical specifications for 400GBASE-DR4-2 124.12.4.3b PMD to MDI optical specifications for 800GBASE-DR8 124.12.4.3c PMD to MDI optical specifications for 800GBASE-DR8-2
131	124.12.4.4 Optical measurement methods
132	124.12.4.6 Characteristics of the fiber optic cabling and MDI
133	162. Physical Medium Dependent (PMD) sublayer and baseband medium, type 100GBASE-CR1, 200GBASE-CR2, and 400GBASE-CR4, and 800GBASE-CR8 162.1 Overview
135	162.2 Conventions
136	162.3 PMD service interfaces 162.4 PCS requirements for Auto-Negotiation (AN) service interface
137	162.5 Delay constraints 162.6 Skew constraints 162.6.3 Skew Constraints for 800GBASE-CR8
138	162.7 PMD MDIO function mapping
140	162.8 PMD functional specifications 162.8.1 Link block diagram 162.8.11 PMD control function
141	162.8.11.1 Training pattern polynomials and seeds 162.9 PMD electrical characteristics 162.9.1 Signal paths
142	162.9.4 Transmitter characteristics 162.9.5 Receiver characteristics 162.9.5.1 Receiver signaling rate
143	162.10 Channel characteristics 162.11 Cable assembly characteristics
144	162.12 MDI specifications
145	162.14 Protocol implementation conformance statement (PICS) proforma for Clause 162, Physical Medium Dependent (PMD) sublayer and baseband medium, type 100GBASE-CR1, 200GBASE-CR2, and 400GBASE-CR4, and 800GBASE-CR8 162.14.1 Introduction 162.14.2 Identification 162.14.2.2 Protocol summary
146	162.14.3 Major capabilities/options 162.14.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and baseband medium, type 100GBASE-CR1, 200GBASE-CR2, and 400GBASE-CR4, and 800GBASE-CR8
147	162.14.4.2 PMD control function
148	163. Physical Medium Dependent (PMD) sublayer and baseband medium, type 100GBASE-KR1, 200GBASE-KR2, and 400GBASE-KR4, and 800GBASE-KR8 163.1 Overview
150	163.2 Conventions 163.3 PMD service interfaces 163.5 Delay constraints
151	163.6 Skew constraints 163.6.3 Skew Constraints for 800GBASE-KR8
152	163.8 PMD functional specifications 163.8.1 Link block diagram
153	163.9 Electrical characteristics 163.9.2 Transmitter characteristics 163.9.3 Receiver characteristics 163.9.3.1 Receiver signaling rate
154	163.9.3.5 Receiver interference tolerance 163.10 Channel characteristics 163.11 MDI specifications
155	163.13 Protocol implementation conformance statement (PICS) proforma for Clause 163, Physical Medium Dependent (PMD) sublayer and baseband medium, type 100GBASE-KR1, 200GBASE-KR2, and 400GBASE-KR4, and 800GBASE-KR8 163.13.1 Introduction 163.13.2 Identification 163.13.2.2 Protocol summary
156	163.13.3 Major capabilities/options 163.13.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and baseband medium, type 100GBASE-KR1, 200GBASE-KR2, and 400GBASE-KR4, and 800GBASE-KR8
157	163.13.4.2 PMD control function
158	167. Physical Medium Dependent (PMD) sublayer and medium, type 100GBASE-VR1, 200GBASE-VR2, 400GBASE-VR4, 800GBASE-VR8, 100GBASE-SR1, 200GBASE-SR2, and 400GBASE-SR4, and 800GBASE-SR8 167.1 Overview
160	167.1.1 Bit error ratio
161	167.2 Physical Medium Dependent (PMD) service interface 167.3 Delay and Skew 167.3.1 Delay constraints
162	167.3.2 Skew constraints 167.3.2.1 Skew constraints for 100GBASE-VR1, 100GBASE-SR1, 200GBASE-VR2, 200GBASE-SR2, 400GBASE-VR4, and 400GBASE-SR4 167.3.2.2 Skew constraints for 800GBASE-VR8 and 800GBASE-SR8
163	167.5 PMD functional specifications 167.5.1 PMD block diagram 167.5.2 PMD transmit function 167.5.3 PMD receive function 167.5.4 PMD global signal detect function
164	167.6 Lane assignments 167.7 PMD to MDI optical specifications for 100GBASE-VR1, 200GBASE-VR2, 400GBASE-VR4, 800GBASE-VR8, 100GBASE-SR1, 200GBASE-SR2, and 400GBASE-SR4, and 800GBASE-SR8
165	167.7.1 Transmitter optical specifications
166	167.7.2 Receiver optical specifications
167	167.7.3 Illustrative link power budget
168	167.8 Definition of optical parameters and measurement methods 167.8.1 Test patterns for optical parameters
170	167.8.6 Transmitter and dispersion eye closure for PAM4 (TDECQ). 167.8.13 Receiver sensitivity 167.9 Safety, installation, environment, and labeling 167.9.2 Laser safety
171	167.9.4 Environment 167.9.5 Electromagnetic emission 167.9.7 PMD labeling requirements 167.10 Fiber optic cabling model
173	167.10.3 Medium Dependent Interface (MDI) 167.10.3.1a Optical lane assignments for 800GBASE-VR8 and 800GBASE-SR8
174	167.10.3.4 MDI requirements for 800GBASE-VR8 and 800GBASE-SR8
175	167.11 Protocol implementation conformance statement (PICS) proforma for Clause 167, Physical Medium Dependent (PMD) sublayer and medium, type 100GBASE-VR1, 200GBASE-VR2, 400GBASE-VR4, 800GBASE-VR8, 100GBASE-SR1, 200GBASE-SR2, and 400GBASE-SR4, and 8… 167.11.1 Introduction 167.11.2 Identification 167.11.2.2 Protocol summary
176	167.11.3 Major capabilities/options 167.11.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and medium, type 100GBASE-VR1, 200GBASE-VR2, 400GBASE-VR4, 800GBASE-VR8, 100GBASE-SR1, 200GBASE-SR2, and 400GBASE-SR4, and 800GBASE-SR8 167.11.4.1 PMD functional specifications
177	167.11.4.6 Characteristics of the fiber optic cabling and MDI
178	169. Introduction to 800 Gb/s networks 169.1 Overview 169.1.1 Scope 169.1.2 Relationship of 800 Gigabit Ethernet to the ISO OSI reference model
179	169.1.3 Nomenclature
180	169.1.4 Physical Layer signaling systems
181	169.2 Summary of 800 Gigabit Ethernet architecture 169.2.1 Reconciliation Sublayer (RS) and 800 Gb/s Media Independent Interface (800GMII) 169.2.2 800GMII Extender and 800GMII Extender Sublayer (800GXS) 169.2.3 Physical Coding Sublayer (PCS)
182	169.2.4 Physical Medium Attachment (PMA) sublayer 169.2.5 Physical Medium Dependent (PMD) sublayer 169.2.6 Auto-Negotiation 169.2.7 Management interface (MDIO/MDC) 169.2.8 Management 169.3 Service interface specification method and notation 169.3.1 Inter-sublayer service interface
183	169.3.2 Instances of the inter-sublayer service interface
186	169.3.3 Semantics of inter-sublayer service interface primitives 169.4 Delay constraints
187	169.5 Skew constraints
189	169.6 FEC Degrade
190	169.7 State diagrams 169.8 Protocol implementation conformance statement (PICS) proforma
191	170. Reconciliation Sublayer (RS) and Media Independent Interface for 800 Gb/s (800GMII) 170.1 Overview
192	170.1.1 Summary of major concepts 170.1.2 Application 170.1.3 Rate of operation 170.1.4 Delay constraints
193	170.1.5 Allocation of functions 170.1.6 800GMII structure 170.1.7 Mapping of 800GMII signals to PLS service primitives 170.2 800GMII data stream 170.3 800GMII functional specifications
194	170.4 Protocol implementation conformance statement (PICS) proforma for Clause 170, Reconciliation Sublayer (RS) and Media Independent Interface for 800 Gb/s operation (800GMII) 170.4.1 Introduction 170.4.2 Identification 170.4.2.1 Implementation identification 170.4.2.2 Protocol summary
195	170.4.3 Major capabilities/options 170.4.4 PICS proforma tables for Reconciliation Sublayer (RS) and Media Independent Interface for 800 Gb/s operation (800GMII) 170.4.4.1 General 170.4.4.2 Mapping of PLS service primitives
196	170.4.4.3 Data stream structure 170.4.4.4 800GMII signal functional specifications
197	170.4.4.5 Link fault signaling state diagram
199	171. 800GMII Extender and 800GMII Extender Sublayer (800GXS) 171.1 Overview
200	171.1.1 Summary of functions 171.2 DTE 800GXS 171.2.1 DTE 800GXS inter-sublayer interfaces
201	171.3 PHY 800GXS
203	171.3.1 PHY 800GXS inter-sublayer interfaces 171.3.2 PHY 800GXS service interface 171.3.3 Service interface below PHY 800GXS
204	171.4 800GAUI-n 171.5 Link fault signaling in the receive direction 171.6 FEC degrade 171.6.1 DTE 800GXS FEC degrade signaling 171.6.2 PHY 800GXS FEC degrade signaling 171.7 800GXS partitioning example
205	171.8 800GXS MDIO function mapping
209	171.9 Protocol implementation conformance statement (PICS) proforma for Clause 171, 800GMII Extender and 800GMII Extender Sublayer (800GXS) 171.9.1 Introduction 171.9.2 Identification 171.9.2.1 Implementation identification 171.9.2.2 Protocol summary
210	171.9.3 Major capabilities/options 171.9.4 PICS proforma tables for 800GMII Extender and 800GMII Extender Sublayer (800GXS) 171.9.4.1 Transmit function
211	171.9.4.2 Receive function 171.9.4.3 64B/66B coding rules
212	171.9.4.4 Management 171.9.4.5 Loopback 171.9.4.6 Delay constraints
213	172. Physical Coding Sublayer (PCS), type 800GBASE-R 172.1 Overview 172.1.1 Scope 172.1.2 Relationship of the 800GBASE-R PCS to other standards 172.1.3 Summary of functions
214	172.1.4 FEC Degrade 172.1.5 Inter-sublayer interfaces 172.1.5.1 PCS service interface
215	172.1.5.2 Physical Medium Attachment (PMA) service interface 172.1.6 Functional block diagram
217	172.2 PCS functions 172.2.1 Overview 172.2.2 Use of 66-bit blocks
218	172.2.3 64B/66B code 172.2.4 Transmit function 172.2.4.1 64B/66B encoder 172.2.4.1.1 State-diagram encoder 172.2.4.1.2 Stateless encoder 172.2.4.2 Rate matching
219	172.2.4.3 Block distribution 172.2.4.4 64B/66B to 256B/257B transcoder 172.2.4.5 Scrambler 172.2.4.6 Alignment marker mapping and insertion
222	172.2.4.7 Pre-FEC distribution 172.2.4.8 Reed-Solomon encoder
223	172.2.4.9 Symbol distribution 172.2.4.10 Transmit bit ordering and distribution 172.2.4.11 Test-pattern generator 172.2.5 Receive function 172.2.5.1 Alignment lock and deskew
224	172.2.5.2 Lane reorder and de-interleave 172.2.5.3 Reed-Solomon decoder 172.2.5.4 Post-FEC interleave 172.2.5.5 Alignment marker removal 172.2.5.6 Descrambler 172.2.5.7 256B/257B to 64B/66B transcoder 172.2.5.8 Block collection 172.2.5.9 64B/66B decoder
225	172.2.5.9.1 State-diagram decoder 172.2.5.9.2 Stateless decoder 172.2.5.10 Rate matching 172.2.6 Detailed functions and state diagrams 172.2.6.1 State diagram conventions 172.2.6.2 State variables 172.2.6.2.1 Constants
226	172.2.6.2.2 Variables
227	172.2.6.2.3 Functions 172.2.6.2.4 Counters 172.2.6.3 State diagrams
228	172.3 PCS management 172.3.1 PCS MDIO function mapping
230	172.3.2 FEC_corrected_cw_counter 172.3.3 FEC_uncorrected_cw_counter 172.3.4 FEC_symbol_error_counter_i 172.3.5 FEC_cw_counter 172.3.6 FEC_codeword_error_bin_i 172.4 Loopback 172.5 Delay constraints
231	172.6 Auto-Negotiation
232	172.7 Protocol implementation conformance statement (PICS) proforma for Clause 172, Physical Coding Sublayer (PCS), type 800GBASE-R 172.7.1 Introduction 172.7.2 Identification 172.7.2.1 Implementation identification 172.7.2.2 Protocol summary
233	172.7.3 Major capabilities/options 172.7.4 PICS proforma tables for Physical Coding Sublayer (PCS), type 800GBASE-R 172.7.4.1 Transmit function
234	172.7.4.2 Receive function
235	172.7.4.3 64B/66B coding rules 172.7.4.4 Management 172.7.4.5 Loopback
236	172.7.4.6 Delay constraints 172.7.4.7 Auto-Negotiation
237	173. Physical Medium Attachment (PMA) sublayer, type 800GBASE-R 173.1 Overview 173.1.1 Scope 173.1.2 Position of the PMA in the 800GBASE-R sublayers 173.1.3 Summary of functions
238	173.1.4 PMA sublayer positioning
239	173.2 PMA service interface
240	173.3 Service interface below PMA
241	173.4 PMA types 173.4.1 32:8 PMA
242	173.4.2 8:32 PMA
243	173.4.3 8:8 PMA
244	173.5 Functions within the PMA 173.5.1 Per input-lane clock and data recovery (CDR)
245	173.5.2 Bit-level multiplexing 173.5.2.1 32:8 PMA bit-level multiplexing 173.5.2.2 8:32 PMA bit-level multiplexing
246	173.5.2.3 8:8 PMA bit-level multiplexing 173.5.3 Skew and Skew Variation 173.5.3.1 Skew generation toward SP1 173.5.3.2 Skew tolerance at SP1 173.5.3.3 Skew generation toward SP2
247	173.5.3.4 Skew tolerance at SP5 173.5.3.5 Skew generation at SP6 173.5.3.6 Skew tolerance at SP6 173.5.4 Delay constraints
248	173.5.5 Clocking architecture 173.5.6 Signal drivers 173.5.7 PAM4 Encoding 173.5.7.1 Gray mapping 173.5.7.2 Precoding
249	173.5.8 Signal status 173.5.8.1 32:8 PMA signal status 173.5.8.2 8:32 PMA signal status 173.5.8.3 8:8 PMA signal status 173.5.9 PMA local loopback mode (optional) 173.5.10 PMA remote loopback mode (optional) 173.5.11 PMA test patterns (optional)
250	173.6 PMA MDIO function mapping
252	173.7 Protocol implementation conformance statement (PICS) proforma for Clause 173, Physical Medium Attachment (PMA) sublayer, type 800GBASE-R 173.7.1 Introduction 173.7.2 Identification 173.7.2.1 Implementation identification 173.7.2.2 Protocol summary
253	173.7.3 Major capabilities/options 173.7.4 Skew generation and tolerance
254	173.7.5 Delay constraints
255	173.7.6 Test patterns 173.7.7 Loopback 173.7.8 Precoding
256	173.7.9 Signal status 173.7.10 Electrical
257	Annex 4A (normative) Simplified full duplex media access control 4A.4 Specific implementations 4A.4.2 MAC parameters
258	Annex 31B (normative) MAC Control PAUSE operation 31B.3 Detailed specification of PAUSE operation 31B.3.7 Timing considerations for PAUSE operation 31B.4 Protocol implementation conformance statement (PICS) proforma for MAC Control PAUSE operation 31B.4.3 Major capabilities/options
259	31B.4.6 PAUSE command MAC timing considerations
260	Annex 90A (informative) Timestamping accuracy considerations 90A.3 Considerations for use of different data delay measurement points
261	Annex 93A (normative) Specification methods for electrical channels 93A.1 Channel Operating Margin
262	Annex 120F (normative) Chip-to-chip Attachment Unit Interfaces 100GAUI-1 C2C, 200GAUI-2 C2C, 400GAUI-4 C2C, and 800GAUI-8 C2C Chip-to-chip 100 Gb/s one-lane Attachment Unit Interface (100GAUI-1 C2C), 200 Gb/s two-lane Attachment Unit Interface (200GA… 120F.1 Overview
265	120F.2 Compliance points 120F.3 Electrical characteristics 120F.3.1 Transmitter electrical characteristics
266	120F.3.2 Receiver characteristics 120F.3.2.1 Receiver signaling rate 120F.4 Channel characteristics
267	120F.5 Protocol implementation conformance statement (PICS) proforma for Annex 120F, Chip-to-chip Attachment Unit Interfaces 100GAUI-1 C2C, 200GAUI-2 C2C, 400GAUI-4 C2C, and 800GAUI-8 C2C Chip-to-chip 100 Gb/s one-lane Attachment Unit Interface (100G… 120F.5.1 Introduction
268	120F.5.2 Identification 120F.5.2.2 Protocol summary 120F.5.3 Major capabilities/options
269	120F.5.4 PICS proforma tables for Chip-to-chip Attachment Unit Interfaces 100GAUI-1 C2C, 200GAUI-2 C2C, 400GAUI-4 C2C, and 800GAUI-8 C2C Chip-to-chip 100 Gb/s one-lane Attachment Unit Interface (100GAUI-1 C2C), 200 Gb/s two-lane Attachment Unit Inter…
270	Annex 120G (normative) Chip-to-module Attachment Unit Interfaces 100GAUI-1 C2M, 200GAUI-2 C2M, 400GAUI-4 C2M, and 800GAUI-8 C2M Chip-to-module 100 Gb/s one-lane Attachment Unit Interface (100GAUI-1 C2M), 200 Gb/s two-lane Attachment Unit Interface (2… 120G.1 Overview
272	120G.1.1 Bit error ratio 120G.2 Compliance point definitions
274	120G.3 Electrical characteristics 120G.3.1 Host output characteristics 120G.3.1.5 Host output eye height and vertical eye closure (VEC)
275	120G.3.2 Module output characteristics 120G.3.2.1 Module output modes 120G.3.2.2 Module output eye height and VEC
276	120G.3.3 Host input characteristics 120G.3.3.5 Host stressed input tolerance 120G.3.3.5.2 Host stressed input test calibration 120G.3.3.5.3 Host stressed input test procedure
277	120G.3.4 Module input characteristics 120G.3.4.3 Module stressed input tolerance 120G.3.4.3.2 Module stressed input test calibration 120G.3.4.3.3 Module stressed input test procedure
279	120G.6 Protocol implementation conformance statement (PICS) proforma for Annex 120G, Chip-to-module Attachment Unit Interfaces 100GAUI-1 C2M, 200GAUI-2 C2M, 400GAUI-4 C2M, and 800GAUI-8 C2M Chip-to-module 100 Gb/s one-lane Attachment Unit Interface (… 120G.6.1 Introduction 120G.6.2 Identification 120G.6.2.2 Protocol summary
280	120G.6.3 Major capabilities/options 120G.6.4 PICS proforma tables for Chip-to-module Attachment Unit Interfaces 100GAUI-1 C2M, 200GAUI-2 C2M, 400GAUI-4 C2M, and 800GAUI-8 C2M Chip-to- module 100 Gb/s one-lane Attachment Unit Interface (100GAUI-1 C2M), 200 Gb/s two-lane Attachment Unit …
281	Annex 162A (informative) Transmitter, receiver and channel parameters associated with test points TP0 and TP5 for 100GBASE-CR1, 200GBASE-CR2, and 400GBASE-CR4, and 800GBASE-CR8 162A.1 Overview 162A.6 Channel effective return loss (ERL)
282	Annex 162B (normative) Test fixtures for 100GBASE-CR1, 200GBASE-CR2, 400GBASE-CR4, 800GBASE-CR8, 100GAUI-1 C2M, 200GAUI-2 C2M, and 400GAUI-4 C2M, and 800GAUI-8 C2M 162B.1 Test fixtures
283	162B.5 Protocol implementation conformance statement (PICS) proforma for Annex 162B, Test fixtures for 100GBASE-CR1, 200GBASE-CR2, 400GBASE-CR4, 800GBASE-CR8, 100GAUI-1 C2M, 200GAUI-2 C2M, and 400GAUI-4 C2M, and 800GAUI-8 C2M 162B.5.1 Introduction 162B.5.2 Identification 162B.5.2.2 Protocol summary
284	162B.5.4 PICS proforma tables for test fixtures for Test fixtures for 100GBASE-CR1, 200GBASE-CR2, 400GBASE-CR4, 100GAUI-1 C2M, 200GAUI-2 C2M, and 400GAUI-4 C2M, and 800GAUI-8 C2M
285	Annex 162C (normative) MDIs for 100GBASE-CR1, 200GBASE-CR2, and 400GBASE-CR4, and 800GBASE-CR8 162C.1 Overview
287	162C.2.5 QSFP-DD800 162C.2.6 OSFP
288	162C.3 Protocol implementation conformance statement (PICS) proforma for Annex 162C, MDIs for 100GBASE-CR1, 200GBASE-CR2, and 400GBASE-CR4, and 800GBASE-CR8 162C.3.1 Introduction 162C.3.2 Identification 162C.3.2.2 Protocol summary 162C.3.3 PICS proforma tables for MDIs for 100GBASE-CR1, 200GBASE-CR2, and 400GBASE-CR4, and 800GBASE-CR8
289	Annex 162D (informative) Cable assemblies and hosts for 100GBASE-CR1, 200GBASE-CR2, and 400GBASE-CR4, and 800GBASE-CR8 162D.1 Overview 162D.1.1 Cable assembly types
291	Annex 172A (informative) 800GBASE-R PCS FEC codeword examples
298	Annex 173A (informative) 800 Gb/s PMA sublayer partitioning examples

Additional information

Standard Title	IEEE Approved Draft Standard for Ethernet Amendment 9: Media Access Control Parameters for 800 Gb/s and Physical Layers and Management Parameters for 400 Gb/s and 800 Gb/s Operation
Published Code	IEEE
Publication Date	2024

Preview PDF


PDF Format	Searchable	Printable	Preview Now

IEEE P802.3df 2024

PDF Catalog

Related products