{"id":129402,"date":"2024-10-19T06:33:00","date_gmt":"2024-10-19T06:33:00","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1687-2014\/"},"modified":"2024-10-24T23:35:27","modified_gmt":"2024-10-24T23:35:27","slug":"ieee-1687-2014","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1687-2014\/","title":{"rendered":"IEEE 1687 2014"},"content":{"rendered":"
New IEEE Standard – Active. A methodology for accessing instrumentation embedded within a semiconductor device, without defining the instruments or their features themselves, via the IEEE 1149.1(TM) test access port (TAP) and\/or other signals, is described in this standard. The elements of the methodology include a hardware architecture for the on-chip network connecting the instruments to the chip pins, a hardware description language to describe this network, and a software language and protocol for communicating with the instruments via this network.<\/p>\n
PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
---|---|---|---|---|---|---|---|
1<\/td>\n | IEEE Std 1687-2014 Front cover <\/td>\n<\/tr>\n | ||||||
5<\/td>\n | Important Notices and Disclaimers Concerning IEEE Standards Documents <\/td>\n<\/tr>\n | ||||||
8<\/td>\n | Participants <\/td>\n<\/tr>\n | ||||||
11<\/td>\n | Introduction <\/td>\n<\/tr>\n | ||||||
12<\/td>\n | Contents <\/td>\n<\/tr>\n | ||||||
15<\/td>\n | IMPORTANT NOTICE 1. Overview 1.1 Scope 1.2 Purpose <\/td>\n<\/tr>\n | ||||||
16<\/td>\n | 1.3 Background 1.4 Organization <\/td>\n<\/tr>\n | ||||||
17<\/td>\n | 1.5 Context <\/td>\n<\/tr>\n | ||||||
18<\/td>\n | 2. Normative references 3. Definitions, acronyms, and abbreviations 3.1 Definitions <\/td>\n<\/tr>\n | ||||||
24<\/td>\n | 3.2 Acronyms and abbreviations <\/td>\n<\/tr>\n | ||||||
25<\/td>\n | 4. Technology 4.1 Introduction 4.2 Serial access networks <\/td>\n<\/tr>\n | ||||||
32<\/td>\n | 4.3 On-chip instruments <\/td>\n<\/tr>\n | ||||||
33<\/td>\n | 5. Hardware architecture 5.1 Introduction to the IEEE 1687 network 5.2 Hierarchical IEEE 1687 networks <\/td>\n<\/tr>\n | ||||||
36<\/td>\n | 5.3 Controller 5.4 Instrument interface <\/td>\n<\/tr>\n | ||||||
37<\/td>\n | 5.5 Access network <\/td>\n<\/tr>\n | ||||||
44<\/td>\n | 5.6 Test data register <\/td>\n<\/tr>\n | ||||||
48<\/td>\n | 5.7 Local reset <\/td>\n<\/tr>\n | ||||||
52<\/td>\n | 5.8 Delivery and integration of instruments <\/td>\n<\/tr>\n | ||||||
53<\/td>\n | 5.9 Embedded TAP controller <\/td>\n<\/tr>\n | ||||||
58<\/td>\n | 5.10 Definitions of the structure of IEEE 1687 hardware architecture <\/td>\n<\/tr>\n | ||||||
59<\/td>\n | 5.11 Port functions of a module <\/td>\n<\/tr>\n | ||||||
61<\/td>\n | 5.12 Signals between and within IEEE 1687 modules <\/td>\n<\/tr>\n | ||||||
62<\/td>\n | 5.13 Components comprising a module <\/td>\n<\/tr>\n | ||||||
64<\/td>\n | 5.14 TAP finite state machine embedded in an IEEE 1687 module <\/td>\n<\/tr>\n | ||||||
67<\/td>\n | 5.15 Access network behavior 5.16 Plug-and-play interfaces <\/td>\n<\/tr>\n | ||||||
70<\/td>\n | 6. Instrument Connectivity Language (ICL) 6.1 ICL introduction <\/td>\n<\/tr>\n | ||||||
71<\/td>\n | 6.2 ICL overview <\/td>\n<\/tr>\n | ||||||
73<\/td>\n | 6.3 ICL lexical conventions and definitions <\/td>\n<\/tr>\n | ||||||
87<\/td>\n | 6.4 ICL primitive element keywords and statements <\/td>\n<\/tr>\n | ||||||
149<\/td>\n | 6.5 ICL informational statements <\/td>\n<\/tr>\n | ||||||
155<\/td>\n | 6.6 ICL connectivity 6.7 Inferring information in implicit ICL <\/td>\n<\/tr>\n | ||||||
156<\/td>\n | 6.8 Active values for control signals <\/td>\n<\/tr>\n | ||||||
157<\/td>\n | 7. Procedural Description Language (PDL): level-0 7.1 Purpose 7.2 PDL levels <\/td>\n<\/tr>\n | ||||||
158<\/td>\n | 7.3 Basic PDL concepts <\/td>\n<\/tr>\n | ||||||
161<\/td>\n | 7.4 Retargeting of PDL <\/td>\n<\/tr>\n | ||||||
163<\/td>\n | 7.5 PDL level-0 overview <\/td>\n<\/tr>\n | ||||||
166<\/td>\n | 7.6 PDL general rules <\/td>\n<\/tr>\n | ||||||
168<\/td>\n | 7.7 Generic PDL tokens <\/td>\n<\/tr>\n | ||||||
169<\/td>\n | 7.8 PDL numbers <\/td>\n<\/tr>\n | ||||||
171<\/td>\n | 7.9 PDL level-0 commands <\/td>\n<\/tr>\n | ||||||
196<\/td>\n | 8. Procedural Description Language: level-1 (Tcl) 8.1 Purpose 8.2 Tcl command extensions <\/td>\n<\/tr>\n | ||||||
197<\/td>\n | 8.3 PDL level-1 overview 8.4 PDL level-1 commands <\/td>\n<\/tr>\n | ||||||
203<\/td>\n | 8.5 PDL level-1 example <\/td>\n<\/tr>\n | ||||||
204<\/td>\n | Annex A (informative) ICL grammar A.1 Conventions A.2 ICL language definition <\/td>\n<\/tr>\n | ||||||
213<\/td>\n | Annex B (informative) PDL level-0 grammar B.1 Conventions B.2 Grammar <\/td>\n<\/tr>\n | ||||||
217<\/td>\n | Annex C (informative) PDL level-1 grammar <\/td>\n<\/tr>\n | ||||||
218<\/td>\n | Annex D (informative) PDL differences between IEEE Std 1687-2014 and IEEE Std 1149.1-2013 D.1 Introduction D.2 PDL level-0 command differences <\/td>\n<\/tr>\n | ||||||
220<\/td>\n | D.3 PDL level-1 commands <\/td>\n<\/tr>\n | ||||||
221<\/td>\n | D.4 General operation differences <\/td>\n<\/tr>\n | ||||||
222<\/td>\n | D.5 Creating interoperable PDL <\/td>\n<\/tr>\n | ||||||
226<\/td>\n | Annex E (informative) Examples E.1 Example context <\/td>\n<\/tr>\n | ||||||
228<\/td>\n | E.2 Instrument example <\/td>\n<\/tr>\n | ||||||
229<\/td>\n | E.3 Scan register example <\/td>\n<\/tr>\n | ||||||
231<\/td>\n | E.4 Wrapped instrument example <\/td>\n<\/tr>\n | ||||||
232<\/td>\n | E.5 Daisy-chain example <\/td>\n<\/tr>\n | ||||||
233<\/td>\n | E.6 SIB_mux_pre component example <\/td>\n<\/tr>\n | ||||||
234<\/td>\n | E.7 Single SIB example <\/td>\n<\/tr>\n | ||||||
235<\/td>\n | E.8 Multiple SIB example <\/td>\n<\/tr>\n | ||||||
236<\/td>\n | E.9 Scan muxes with local control example <\/td>\n<\/tr>\n | ||||||
238<\/td>\n | E.10 Scan muxes with remote control example <\/td>\n<\/tr>\n | ||||||
239<\/td>\n | E.11 Nested SIB example: mux_pre <\/td>\n<\/tr>\n | ||||||
241<\/td>\n | E.12 BAD Nested SIB example: mux_post <\/td>\n<\/tr>\n | ||||||
242<\/td>\n | E.13 Exclusive access example: implicit ICL <\/td>\n<\/tr>\n | ||||||
243<\/td>\n | E.14 Exclusive access example: explicit ICL <\/td>\n<\/tr>\n | ||||||
244<\/td>\n | E.15 Exclusive access with broadcast example <\/td>\n<\/tr>\n | ||||||
246<\/td>\n | E.16 Broadcast or daisy-chain example <\/td>\n<\/tr>\n | ||||||
247<\/td>\n | E.17 Branched scan chain example <\/td>\n<\/tr>\n | ||||||
248<\/td>\n | E.18 Branched-then-merged scan chain example <\/td>\n<\/tr>\n | ||||||
250<\/td>\n | E.19 IEEE 1500 wrapper serial port <\/td>\n<\/tr>\n | ||||||
251<\/td>\n | E.20 IEEE 1500 WSP with SWIR bit included <\/td>\n<\/tr>\n | ||||||
253<\/td>\n | E.21 Single embedded TAP controller (eTAPC) example <\/td>\n<\/tr>\n | ||||||
254<\/td>\n | E.22 Basic PDL for a simple instrument <\/td>\n<\/tr>\n | ||||||
256<\/td>\n | E.23 MBIST engine example <\/td>\n<\/tr>\n | ||||||
257<\/td>\n | E.24 MBIST and associated memory example <\/td>\n<\/tr>\n | ||||||
258<\/td>\n | E.25 Combined MBIST and memory example <\/td>\n<\/tr>\n | ||||||
260<\/td>\n | E.26 Addressable instruments <\/td>\n<\/tr>\n | ||||||
261<\/td>\n | E.27 Black-box module <\/td>\n<\/tr>\n | ||||||
262<\/td>\n | E.28 Wide scan interface example <\/td>\n<\/tr>\n | ||||||
263<\/td>\n | E.29 Simple IEEE 1149.1 AccessLink example <\/td>\n<\/tr>\n | ||||||
264<\/td>\n | E.30 Complex IEEE 1149.1 AccessLink example <\/td>\n<\/tr>\n | ||||||
267<\/td>\n | E.31 Generic AccessLink example <\/td>\n<\/tr>\n | ||||||
269<\/td>\n | Annex F (informative) Design guidance F.1 Introduction F.2 Scan register implementations <\/td>\n<\/tr>\n | ||||||
275<\/td>\n | F.3 Scan multiplexers <\/td>\n<\/tr>\n | ||||||
281<\/td>\n | Annex G (informative) Bibliography <\/td>\n<\/tr>\n | ||||||
283<\/td>\n | Back cover <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" IEEE Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device<\/b><\/p>\n |