{"id":136470,"date":"2024-10-19T07:52:27","date_gmt":"2024-10-19T07:52:27","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-802-3ba-2010\/"},"modified":"2024-10-25T00:02:25","modified_gmt":"2024-10-25T00:02:25","slug":"ieee-802-3ba-2010","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-802-3ba-2010\/","title":{"rendered":"IEEE 802.3ba 2010"},"content":{"rendered":"

Amendment Standard – Inactive – Superseded. This amendment to IEEE Std 802.3-2008 includes changes to IEEE Std 802.3-2008 and adds Clause 80 through Clause 88, Annex 83A through Annex 83C, Annex 85A, and Annex 86A. This amendment includes IEEE 802.3 Media Access Control (MAC) parameters, Physical Layer specifications, and management parameters for the transfer of IEEE 802.3 format frames at 40 Gb\/s and 100 Gb\/s.<\/p>\n

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
1<\/td>\nIEEE Std 802.3ba-2010 Cover page <\/td>\n<\/tr>\n
3<\/td>\nTitle page <\/td>\n<\/tr>\n
6<\/td>\nIntroduction <\/td>\n<\/tr>\n
7<\/td>\nNotice to users
Laws and regulations
Copyrights <\/td>\n<\/tr>\n
8<\/td>\nUpdating of IEEE documents
Errata
Interpretations
Patents <\/td>\n<\/tr>\n
9<\/td>\nParticipants
David J. Law, IEEE 802.3 Working Group Chair Wael William Diab, IEEE 802.3 Working Group Vice-Chair Steven B. Carlson, IEEE 802.3 Working Group Executive Secretary Adam Healey, IEEE 802.3 Working Group Secretary Bradley Booth, IEEE 802.3 Working Grou… <\/td>\n<\/tr>\n
12<\/td>\nRobert M. Grow, Chair
Richard H. Hulett, Vice Chair
Steve M. Mills, Past Chair <\/td>\n<\/tr>\n
15<\/td>\nContents <\/td>\n<\/tr>\n
25<\/td>\nImportant Notice <\/td>\n<\/tr>\n
26<\/td>\n1. Introduction
1.1.3.2 Compatibility interfaces
1.2.3 Physical Layer and media notation <\/td>\n<\/tr>\n
27<\/td>\n1.3 Normative references <\/td>\n<\/tr>\n
28<\/td>\n1.4 Definitions <\/td>\n<\/tr>\n
29<\/td>\n1.5 Abbreviations <\/td>\n<\/tr>\n
31<\/td>\n4. Media Access Control
4.4.2 MAC parameters <\/td>\n<\/tr>\n
33<\/td>\n30. Management
30.3.2.1.2 aPhyType
30.3.2.1.3 aPhyTypeList <\/td>\n<\/tr>\n
34<\/td>\n30.3.2.1.5 aSymbolErrorDuringCarrier
30.5.1.1.2 aMAUType <\/td>\n<\/tr>\n
35<\/td>\n30.5.1.1.4 aMediaAvailable <\/td>\n<\/tr>\n
36<\/td>\n30.5.1.1.10a aBIPErrorCount <\/td>\n<\/tr>\n
37<\/td>\n30.5.1.1.10b aLaneMapping
30.5.1.1.14 aFECmode
30.5.1.1.15 aFECCorrectedBlocks <\/td>\n<\/tr>\n
38<\/td>\n30.5.1.1.16 aFECUncorrectableBlocks
30.6.1.1.5 aAutoNegLocalTechnologyAbility <\/td>\n<\/tr>\n
41<\/td>\n45. Management Data Input\/Output (MDIO) Interface
45.2 MDIO Interface Registers
45.2.1 PMA\/PMD registers <\/td>\n<\/tr>\n
43<\/td>\n45.2.1.1 PMA\/PMD control 1 register (Register 1.0)
45.2.1.1.3 Speed selection (1.0.13,1.0.6, 1.0.5:2) <\/td>\n<\/tr>\n
45<\/td>\n45.2.1.1.3a PMA remote loopback (1.0.1)
45.2.1.1.4 PMA local loopback (1.0.0) <\/td>\n<\/tr>\n
46<\/td>\n45.2.1.2.1 Fault (1.1.7)
45.2.1.4.a 100G capable (1.4.9)
45.2.1.4.b 40G capable (1.4.8) <\/td>\n<\/tr>\n
48<\/td>\n45.2.1.6.1 PMA\/PMD type selection (1.7.35:0)
45.2.1.7 10G PMA\/PMD status 2 register (Register 1.8)
45.2.1.7.4 Transmit fault (1.8.11) <\/td>\n<\/tr>\n
49<\/td>\n45.2.1.7.5 Receive fault (1.8.10)
45.2.1.7.15 PMA local loopback ability (1.8.0)
45.2.1.8 10G PMD transmit disable register (Register 1.9) <\/td>\n<\/tr>\n
50<\/td>\n45.2.1.8.a PMD transmit disable 9 (1.9.10)
45.2.1.8.b PMD transmit disable 4, 5, 6, 7, 8 (1.9.5, 1.9.6, 1.9.7, 1.9.8, 1.9.9)
45.2.1.9 10G PMD receive signal detect register (Register 1.10) <\/td>\n<\/tr>\n
51<\/td>\n45.2.1.9.a PMD receive signal detect 9 (1.10.10)
45.2.1.9.b PMD receive signal detect 4, 5, 6, 7, 8 (1.10.5, 1.10.6, 1.10.7, 1.10.8, 1.10.9) <\/td>\n<\/tr>\n
52<\/td>\n45.2.1.10 PMA\/PMD extended ability register (Register 1.11)
45.2.1.11a 40G\/100G PMA\/PMD extended ability register (Register 1.13) <\/td>\n<\/tr>\n
53<\/td>\n45.2.1.11a.1 PMA remote loopback ability (1.13.15)
45.2.1.11a.2 100GBASE-ER4 ability (1.13.11)
45.2.1.11a.3 100GBASE-LR4 ability (1.13.10)
45.2.1.11a.4 100GBASE-SR10 ability (1.13.9)
45.2.1.11a.5 100GBASE-CR10 ability (1.13.8)
45.2.1.11a.6 40GBASE-LR4 ability (1.13.3)
45.2.1.11a.7 40GBASE-SR4 ability (1.13.2)
45.2.1.11a.8 40GBASE-CR4 ability (1.13.1)
45.2.1.11a.9 40GBASE-KR4 ability (1.13.0) <\/td>\n<\/tr>\n
54<\/td>\n45.2.1.77 10GBASE-KR BASE-R PMD control register (Register 1.150)
45.2.1.78 10GBASE-KR BASE-R PMD status register (Register 1.151) <\/td>\n<\/tr>\n
55<\/td>\n45.2.1.78.1 Receiver status 0 (1.151.0)
45.2.1.78.2 Frame lock 0 (1.151.1)
45.2.1.78.3 Start-up protocol status 0 (1.151.2)
45.2.1.78.4 Training failure 0 (1.151.3)
45.2.1.78.5 Receiver status 1, 2, 3 (1.151.4, 1.151.8, 1.151.12)
45.2.1.78.6 Frame lock 1, 2, 3 (1.151.5, 1.151.9, 1.151.13)
45.2.1.78.7 Start-up protocol status 1, 2, 3 (1.151.6, 1.151.10, 1.151.14) <\/td>\n<\/tr>\n
56<\/td>\n45.2.1.78.8 Training failure 1, 2, 3 (1.151.7, 1.151.11, 1.151.15)
45.2.1.79 10GBASE-KR BASE-R LP coefficient update, lane 0 register (Register 1.152)
45.2.1.80 10GBASE-KR BASE-R LP status report, lane 0 register (Register 1.153) <\/td>\n<\/tr>\n
57<\/td>\n45.2.1.81 10GBASE-KR BASE-R LD coefficient update, lane 0 register (Register 1.154)
45.2.1.82 10GBASE-KR BASE-R LD status report, lane 0 register (Register 1.155) <\/td>\n<\/tr>\n
58<\/td>\n45.2.1.82a BASE-R PMD status 2 register (Register 1.156) <\/td>\n<\/tr>\n
59<\/td>\n45.2.1.82a.1 Receiver status 4, 5, 6, 7 (1.156.0, 1.156.4, 1.156.8, 1.156.12)
45.2.1.82a.2 Frame lock 4, 5, 6, 7 (1.156.1, 1.156.5, 1.156.9, 1.156.13)
45.2.1.82a.3 Start-up protocol status 4, 5, 6, 7 (1.156.2, 1.156.6, 1.156.10, 1.156.14)
45.2.1.82a.4 Training failure 4, 5, 6, 7 (1.156.3, 1.156.7, 1.156.11, 1.156.15)
45.2.1.82b BASE-R PMD status 3 register (Register 1.157)
45.2.1.82b.1 Receiver status 8, 9 (1.157.0, 1.157.4) <\/td>\n<\/tr>\n
60<\/td>\n45.2.1.82b.2 Frame lock 8, 9 (1.157.1, 1.157.5)
45.2.1.82b.3 Start-up protocol status 8, 9 (1.157.2, 1.157.6)
45.2.1.82b.4 Training failure 8, 9 (1.157.3, 1.157.7)
45.2.1.85 10GBASE-R FEC ability register (Register 1.170)
45.2.1.85.1 10GBASE-R FEC ability (1.170.0)
45.2.1.85.2 10GBASE-R FEC error indication ability (1.170.1) <\/td>\n<\/tr>\n
61<\/td>\n45.2.1.86 10GBASE-R FEC control register (Register 1.171)
45.2.1.86.1 FEC enable (1.171.0)
45.2.1.86.2 FEC enable error indication (1.171.1)
45.2.1.87 10GBASE-R FEC corrected blocks counter (Register 1.172, 1.173) <\/td>\n<\/tr>\n
62<\/td>\n45.2.1.88 10GBASE-R FEC uncorrected blocks counter (Register 1.174, 1.175)
45.2.1.89 BASE-R FEC corrected blocks counter, lanes 0 through 19 <\/td>\n<\/tr>\n
63<\/td>\n45.2.1.90 BASE-R FEC uncorrected blocks counter, lanes 0 through 19
45.2.1.91 BASE-R LP coefficient update register, lanes 1 through 9
45.2.1.92 BASE-R LP status report register, lanes 1 through 9
45.2.1.93 BASE-R LD coefficient update register, lanes 1 through 9
45.2.1.94 BASE-R LD status report register, lanes 1 through 9 <\/td>\n<\/tr>\n
64<\/td>\n45.2.1.95 Test-pattern ability (Register 1.1500) <\/td>\n<\/tr>\n
65<\/td>\n45.2.1.96 PRBS pattern testing control (Register 1.1501) <\/td>\n<\/tr>\n
66<\/td>\n45.2.1.97 Square wave testing control (Register 1.1510)
45.2.1.98 PRBS Tx pattern testing error counter (Register 1.1600, 1.1601, 1.1602, 1.1603, 1.1604, 1.1605, 1.1606, 1.1607, 1.1608, 1.1609) <\/td>\n<\/tr>\n
67<\/td>\n45.2.1.99 PRBS Rx pattern testing error counter (Register 1.1700, 1.1701, 1.1702, 1.1703, 1.1704, 1.1705, 1.1706, 1.1707, 1.1708, 1.1709) <\/td>\n<\/tr>\n
68<\/td>\n45.2.3 PCS registers <\/td>\n<\/tr>\n
69<\/td>\n45.2.3.2.2 PCS receive link status (3.1.2)
45.2.3.4.3 40G capable (3.4.2) <\/td>\n<\/tr>\n
70<\/td>\n45.2.3.4.4 100G capable (3.4.3)
45.2.3.6 10G PCS control 2 register (Register 3.7)
45.2.3.6.1 PCS type selection (3.7.12:0)
45.2.3.7 10G PCS status 2 register (Register 3.8)
45.2.3.7.3a 100GBASE-R capable (3.8.5) <\/td>\n<\/tr>\n
71<\/td>\n45.2.3.7.3b 40GBASE-R capable (3.8.4)
45.2.3.11 10GBASE-R PCS and 10GBASE-T PCS status 1 register (Register 3.32)
45.2.3.11.1 10GBASE-R and 10GBASE-T receive link status (3.32.12)
45.2.3.11.4 10GBASE-R and 10GBASE-T PCS high BER (3.32.1) <\/td>\n<\/tr>\n
72<\/td>\n45.2.3.11.5 10GBASE-R and 10GBASE-T PCS block lock (3.32.0)
45.2.3.12 10GBASE-R and 10GBASE-T PCS status 2 register (Register 3.33) <\/td>\n<\/tr>\n
73<\/td>\n45.2.3.12.1 Latched block lock (3.33.15)
45.2.3.12.2 Latched high BER (3.33.14)
45.2.3.12.3 BER (3.33.13:8)
45.2.3.12.4 Errored blocks (3.33.7:0) <\/td>\n<\/tr>\n
74<\/td>\n45.2.3.15 10GBASE-R PCS test-pattern control register (Register 3.42)
45.2.3.15.a Scrambled idle test-pattern enable (3.42.7) <\/td>\n<\/tr>\n
75<\/td>\n45.2.3.15.1 10GBASE-R PRBS9 transmit test-pattern enable (3.42.6)
45.2.3.15.2 10GBASE-R PRBS31 receive test-pattern enable (3.42.5)
45.2.3.15.3 10GBASE-R PRBS31 transmit test-pattern enable (3.42.4)
45.2.3.16 10GBASE-R PCS test-pattern error counter register (Register 3.43)
45.2.3.16a BER high order counter (Register 3.44) <\/td>\n<\/tr>\n
76<\/td>\n45.2.3.16b Errored blocks high order counter (Register 3.45)
45.2.3.16c Multi-lane BASE-R PCS alignment status 1 register (Register 3.50)
45.2.3.16c.1 Multi-lane BASE-R PCS alignment status (3.50.12)
45.2.3.16c.2 Block 7 lock (3.50.7)
45.2.3.16c.3 Block 6 lock (3.50.6) <\/td>\n<\/tr>\n
77<\/td>\n45.2.3.16c.4 Block 5 lock (3.50.5)
45.2.3.16c.5 Block 4 lock (3.50.4)
45.2.3.16c.6 Block 3 lock (3.50.3) <\/td>\n<\/tr>\n
78<\/td>\n45.2.3.16c.7 Block 2 lock (3.50.2)
45.2.3.16c.8 Block 1 lock (3.50.1)
45.2.3.16c.9 Block 0 lock (3.50.0)
45.2.3.16d Multi-lane BASE-R PCS alignment status 2 register (Register 3.51)
45.2.3.16d.1 Block 19 lock (3.51.11)
45.2.3.16d.2 Block 18 lock (3.51.10)
45.2.3.16d.3 Block 17 lock (3.51.9)
45.2.3.16d.4 Block 16 lock (3.51.8) <\/td>\n<\/tr>\n
79<\/td>\n45.2.3.16d.5 Block 15 lock (3.51.7)
45.2.3.16d.6 Block 14 lock (3.51.6) <\/td>\n<\/tr>\n
80<\/td>\n45.2.3.16d.7 Block 13 lock (3.51.5)
45.2.3.16d.8 Block 12 lock (3.51.4)
45.2.3.16d.9 Block 11 lock (3.51.3)
45.2.3.16d.10 Block 10 lock (3.51.2)
45.2.3.16d.11 Block 9 lock (3.51.1)
45.2.3.16d.12 Block 8 lock (3.51.0)
45.2.3.16e Multi-lane BASE-R PCS alignment status 3 register (Register 3.52)
45.2.3.16e.1 Lane 7 aligned (3.52.7) <\/td>\n<\/tr>\n
81<\/td>\n45.2.3.16e.2 Lane 6 aligned (3.52.6)
45.2.3.16e.3 Lane 5 aligned (3.52.5)
45.2.3.16e.4 Lane 4 aligned (3.52.4)
45.2.3.16e.5 Lane 3 aligned (3.52.3) <\/td>\n<\/tr>\n
82<\/td>\n45.2.3.16e.6 Lane 2 aligned (3.52.2)
45.2.3.16e.7 Lane 1 aligned (3.52.1)
45.2.3.16e.8 Lane 0 aligned (3.52.0)
45.2.3.16f Multi-lane BASE-R PCS alignment status 4 register (Register 3.53)
45.2.3.16f.1 Lane 19 aligned (3.53.11)
45.2.3.16f.2 Lane 18 aligned (3.53.10)
45.2.3.16f.3 Lane 17 aligned (3.53.9)
45.2.3.16f.4 Lane 16 aligned (3.53.8) <\/td>\n<\/tr>\n
83<\/td>\n45.2.3.16f.5 Lane 15 aligned (3.53.7)
45.2.3.16f.6 Lane 14 aligned (3.53.6) <\/td>\n<\/tr>\n
84<\/td>\n45.2.3.16f.7 Lane 13 aligned (3.53.5)
45.2.3.16f.8 Lane 12 aligned (3.53.4)
45.2.3.16f.9 Lane 11 aligned (3.53.3)
45.2.3.16f.10 Lane 10 aligned (3.53.2)
45.2.3.16f.11 Lane 9 aligned (3.53.1)
45.2.3.16f.12 Lane 8 aligned (3.53.0)
45.2.3.36 BIP error counter lane 0 (Register 3.200) <\/td>\n<\/tr>\n
85<\/td>\n45.2.3.37 BIP error counter, lanes 1 through 19 (Registers 3.201 through 3.219)
45.2.3.38 Lane 0 mapping register (Register 3.400)
45.2.3.39 Lanes 1 through 19 mapping registers (Registers 3.401 through 3.419) <\/td>\n<\/tr>\n
86<\/td>\n45.2.7 Auto-Negotiation registers
45.2.7.12 Backplane Ethernet, BASE-R copper status (Register 7.48) <\/td>\n<\/tr>\n
87<\/td>\n45.2.7.12.1 10GBASE-KR BASE-R FEC negotiated (7.48.4)
45.2.7.12.2 Negotiated Port Type (7.48.1, 7.48.2, 7.48.3, 7.48.5, 7.48.6, 7.48.8)
45.2.7.12.3 Backplane Ethernet, BASE-R copper AN ability (7.48.0) <\/td>\n<\/tr>\n
88<\/td>\n45.5 Protocol implementation conformance statement (PICS) proforma for Clause 45, MDIO interface
45.5.3.2 PMA\/PMD MMD options <\/td>\n<\/tr>\n
90<\/td>\n45.5.3.3 PMA\/PMD management functions <\/td>\n<\/tr>\n
92<\/td>\n45.5.3.6 PCS options <\/td>\n<\/tr>\n
93<\/td>\n45.5.3.7 PCS management functions <\/td>\n<\/tr>\n
95<\/td>\n52. Physical Medium Dependent (PMD) sublayer and baseband medium, type 10GBASE-S (short wavelength serial), 10GBASE-L (long wavelength serial), and 10GBASE-E (extra long wavelength serial)
52.9.10 Transmitter and dispersion penalty measurement <\/td>\n<\/tr>\n
97<\/td>\n69. Introduction to Ethernet operation over electrical backplanes
69.1 Overview
69.1.1 Scope
69.1.2 Objectives
69.1.3 Relationship of Backplane Ethernet to the ISO OSI reference model <\/td>\n<\/tr>\n
98<\/td>\n69.2 Summary of Backplane Ethernet Sublayers
69.2.1 Reconciliation Sublayer and media independent interfaces <\/td>\n<\/tr>\n
99<\/td>\n69.2.3 Physical Layer signaling systems
69.2.5 Management
69.3 Delay constraints <\/td>\n<\/tr>\n
101<\/td>\n73. Auto-Negotiation for backplane and copper cable assembly
73.2 Relationship to the ISO\/IEC Open Systems Interconnection (OSI) reference model
73.3 Functional specifications <\/td>\n<\/tr>\n
102<\/td>\n73.5 DME transmission
73.5.1 DME page encoding electrical specifications
73.5.1.1 DME electrical specifications <\/td>\n<\/tr>\n
103<\/td>\n73.6 Link codeword encoding
73.6.4 Technology Ability Field
73.6.5 FEC capability <\/td>\n<\/tr>\n
104<\/td>\n73.7 Receive function requirements
73.7.1 DME page reception
73.7.2 Receive Switch function
73.7.4.1 Parallel Detection function <\/td>\n<\/tr>\n
105<\/td>\n73.7.6 Priority Resolution function
73.10 State diagrams and variable definitions
73.10.1 State diagram variables <\/td>\n<\/tr>\n
106<\/td>\n73.10.2 State diagram timers <\/td>\n<\/tr>\n
108<\/td>\n73.11 Protocol implementation conformance statement (PICS) proforma for Clause 73, Auto-Negotiation for Bbackplane Ethernet and copper cable assembly
73.11.1 Introduction
73.11.2.2 Protocol summary
73.11.4 PICS proforma tables for Auto-Negotiation for backplane and copper cable assembly
73.11.4.2 DME transmission <\/td>\n<\/tr>\n
109<\/td>\n73.11.4.3 Link codeword encoding
73.11.4.7 State diagrams and variable definitions <\/td>\n<\/tr>\n
111<\/td>\n74. Forward Error Correction (FEC) sublayer for 10GBASE-R PHYs
74.1 Overview
74.2 Objectives
74.3 Relationship to other sublayers <\/td>\n<\/tr>\n
112<\/td>\n74.4 Inter-sublayer interfaces <\/td>\n<\/tr>\n
113<\/td>\n74.4.1 Functional block diagram for 10GBASE-R PHYs
74.4.2 Functional block diagram for 40GBASE-R PHYs <\/td>\n<\/tr>\n
114<\/td>\n74.4.3 Functional block diagram for 100GBASE-R PHYs <\/td>\n<\/tr>\n
115<\/td>\n74.5 FEC service interface <\/td>\n<\/tr>\n
116<\/td>\n74.5.1 10GBASE-R service primitives
74.5.1.1 FEC_UNITDATA.request
74.5.1.1.1 Semantics of the service primitive
74.5.1.1.2 When generated
74.5.1.1.3 Effect of receipt
74.5.1.2 FEC_UNITDATA.indication
74.5.1.2.1 Semantics of the service primitive <\/td>\n<\/tr>\n
117<\/td>\n74.5.1.2.2 When generated
74.5.1.2.3 Effect of receipt
74.5.1.3 FEC_SIGNAL.indication
74.5.1.3.1 Semantics of the service primitive
74.5.1.3.2 When generated
74.5.1.3.3 Effect of receipt
74.5.2 40GBASE-R and 100GBASE-R service primitives <\/td>\n<\/tr>\n
118<\/td>\n74.6 Delay constraints
74.7 FEC principle of operation <\/td>\n<\/tr>\n
119<\/td>\n74.7.3 Composition of the FEC block
74.7.4.1 Reverse gearbox function
74.7.4.1.1 Reverse gearbox function for 10GBASE-R
74.7.4.1.2 Reverse gearbox function for 40GBASE-R and 100GBASE-R <\/td>\n<\/tr>\n
121<\/td>\n74.7.4.3 FEC transmission bit ordering <\/td>\n<\/tr>\n
122<\/td>\n74.7.4.4 FEC (2112, 2080) encoder
74.7.4.5 FEC decoder <\/td>\n<\/tr>\n
123<\/td>\n74.7.4.5.1 FEC (2112,2080) decoding <\/td>\n<\/tr>\n
125<\/td>\n74.7.4.6 FEC receive bit ordering <\/td>\n<\/tr>\n
126<\/td>\n74.8 FEC MDIO function mapping
74.8.1 FEC capability <\/td>\n<\/tr>\n
127<\/td>\n74.8.2 FEC enable
74.8.3 FEC Enable Error Indication
74.8.3.1 FEC Error Indication ability
74.8.4.1 FEC_corrected_blocks_counter <\/td>\n<\/tr>\n
128<\/td>\n74.8.4.2 FEC_uncorrected_blocks_counter
74.9 BASE-R PHY test-pattern mode
74.10.2.2 Variables <\/td>\n<\/tr>\n
129<\/td>\n74.11 Protocol implementation conformance statement (PICS) proforma for Clause 74, Forward Error Correction (FEC) sublayer for 10GBASE-R PHYs
74.11.1 Introduction
74.11.2.2 Protocol summary <\/td>\n<\/tr>\n
130<\/td>\n74.11.3 Major capabilities\/options
74.11.5 FEC requirements <\/td>\n<\/tr>\n
131<\/td>\n80. Introduction to 40 Gb\/s and 100 Gb\/s networks
80.1 Overview
80.1.1 Scope
80.1.2 Objectives
80.1.3 Relationship of 40 Gigabit and 100 Gigabit Ethernet to the ISO OSI reference model <\/td>\n<\/tr>\n
133<\/td>\n80.1.4 Nomenclature
80.1.5 Physical Layer signaling systems <\/td>\n<\/tr>\n
134<\/td>\n80.2 Summary of 40 Gigabit and 100 Gigabit Ethernet sublayers
80.2.1 Reconciliation Sublayer (RS) and Media Independent Interface
80.2.2 Physical Coding Sublayer (PCS) <\/td>\n<\/tr>\n
135<\/td>\n80.2.3 Forward Error Correction (FEC) sublayer
80.2.4 Physical Medium Attachment (PMA) sublayer
80.2.5 Physical Medium Dependent (PMD) sublayer
80.2.6 Auto-Negotiation
80.2.7 Management interface (MDIO\/MDC)
80.2.8 Management <\/td>\n<\/tr>\n
136<\/td>\n80.3 Service interface specification method and notation
80.3.1 Inter-sublayer service interface
80.3.2 Instances of the Inter-sublayer service interface <\/td>\n<\/tr>\n
139<\/td>\n80.3.3 Semantics of inter-sublayer service interface primitives
80.3.3.1 IS_UNITDATA_i.request
80.3.3.1.1 Semantics of the service primitive
80.3.3.1.2 When generated
80.3.3.1.3 Effect of receipt
80.3.3.2 IS_UNITDATA_i.indication
80.3.3.2.1 Semantics of the service primitive <\/td>\n<\/tr>\n
140<\/td>\n80.3.3.2.2 When generated
80.3.3.2.3 Effect of receipt
80.3.3.3 IS_SIGNAL.indication
80.3.3.3.1 Semantics of the service primitive
80.3.3.3.2 When generated
80.3.3.3.3 Effect of receipt
80.4 Delay constraints <\/td>\n<\/tr>\n
141<\/td>\n80.5 Skew constraints <\/td>\n<\/tr>\n
145<\/td>\n80.6 State diagrams
80.7 Protocol implementation conformance statement (PICS) proforma <\/td>\n<\/tr>\n
147<\/td>\n81. Reconciliation Sublayer (RS) and Media Independent Interface for 40 Gb\/s and 100 Gb\/s operation (XLGMII and CGMII)
81.1 Overview <\/td>\n<\/tr>\n
148<\/td>\n81.1.1 Summary of major concepts
81.1.2 Application
81.1.3 Rate of operation
81.1.4 Delay constraints <\/td>\n<\/tr>\n
149<\/td>\n81.1.5 Allocation of functions
81.1.6 XLGMII\/CGMII structure <\/td>\n<\/tr>\n
150<\/td>\n81.1.7 Mapping of XLGMII\/CGMII signals to PLS service primitives
81.1.7.1 Mapping of PLS_DATA.request
81.1.7.1.1 Function
81.1.7.1.2 Semantics of the service primitive
81.1.7.1.3 When generated
81.1.7.1.4 Effect of receipt <\/td>\n<\/tr>\n
151<\/td>\n81.1.7.2 Mapping of PLS_DATA.indication
81.1.7.2.1 Function
81.1.7.2.2 Semantics of the service primitive
81.1.7.2.3 When generated
81.1.7.2.4 Effect of receipt
81.1.7.3 Mapping of PLS_CARRIER.indication
81.1.7.4 Mapping of PLS_SIGNAL.indication
81.1.7.5 Mapping of PLS_DATA_VALID.indication
81.1.7.5.1 Function
81.1.7.5.2 Semantics of the service primitive <\/td>\n<\/tr>\n
152<\/td>\n81.1.7.5.3 When generated
81.1.7.5.4 Effect of receipt
81.2 XLGMII\/CGMII data stream <\/td>\n<\/tr>\n
153<\/td>\n81.2.1 Inter-frame
81.2.2 Preamble and start of frame delimiter <\/td>\n<\/tr>\n
154<\/td>\n81.2.3 Data
81.2.4 End of frame delimiter
81.2.5 Definition of Start of Packet and End of Packet Delimiters
81.3 XLGMII\/CGMII functional specifications
81.3.1 Transmit
81.3.1.1 TX_CLK <\/td>\n<\/tr>\n
155<\/td>\n81.3.1.2 TXC (transmit control)
81.3.1.3 TXD (transmit data) <\/td>\n<\/tr>\n
157<\/td>\n81.3.1.4 Start control character alignment <\/td>\n<\/tr>\n
158<\/td>\n81.3.2 Receive
81.3.2.1 RX_CLK (receive clock)
81.3.2.2 RXC (receive control) <\/td>\n<\/tr>\n
160<\/td>\n81.3.2.3 RXD (receive data) <\/td>\n<\/tr>\n
161<\/td>\n81.3.3 Error and fault handling
81.3.3.1 Response to error indications by the XLGMII\/CGMII <\/td>\n<\/tr>\n
162<\/td>\n81.3.3.2 Conditions for generation of transmit Error control characters
81.3.3.3 Response to received invalid frame sequences
81.3.4 Link fault signaling <\/td>\n<\/tr>\n
163<\/td>\n81.3.4.1 Variables and counters
81.3.4.2 State Diagram <\/td>\n<\/tr>\n
165<\/td>\n81.4 Protocol implementation conformance statement (PICS) proforma for Clause 81, Reconciliation Sublayer (RS) and Media Independent Interface for 40 Gb\/s and 100 Gb\/s operation
81.4.1 Introduction
81.4.2 Identification
81.4.2.1 Implementation identification
81.4.2.2 Protocol summary <\/td>\n<\/tr>\n
166<\/td>\n81.4.2.3 Major capabilities\/options
81.4.3 PICS proforma tables for Reconciliation Sublayer and Media Independent Interface for 40 Gb\/s and 100 Gb\/s operation
81.4.3.1 General
81.4.3.2 Mapping of PLS service primitives <\/td>\n<\/tr>\n
167<\/td>\n81.4.3.3 Data stream structure <\/td>\n<\/tr>\n
168<\/td>\n81.4.3.4 XLGMII\/CGMII signal functional specifications <\/td>\n<\/tr>\n
169<\/td>\n81.4.3.5 Link fault signaling state diagram <\/td>\n<\/tr>\n
171<\/td>\n82. Physical Coding Sublayer (PCS) for 64B\/66B, type 40GBASE-R and 100GBASE-R
82.1 Overview
82.1.1 Scope
82.1.2 Relationship of 40GBASE-R and 100GBASE-R to other standards <\/td>\n<\/tr>\n
172<\/td>\n82.1.3 Summary of 40GBASE-R and 100GBASE-R sublayers
82.1.3.1 Physical Coding Sublayer (PCS) <\/td>\n<\/tr>\n
173<\/td>\n82.1.4 Inter-sublayer interfaces
82.1.4.1 PCS service interface (XLGMII\/CGMII)
82.1.4.2 Physical Medium Attachment (PMA) service interface
82.1.5 Functional block diagram <\/td>\n<\/tr>\n
174<\/td>\n82.2 Physical Coding Sublayer (PCS)
82.2.1 Functions within the PCS <\/td>\n<\/tr>\n
175<\/td>\n82.2.2 Use of blocks <\/td>\n<\/tr>\n
176<\/td>\n82.2.3 64B\/66B transmission code
82.2.3.1 Notation conventions
82.2.3.2 Transmission order <\/td>\n<\/tr>\n
179<\/td>\n82.2.3.3 Block structure <\/td>\n<\/tr>\n
180<\/td>\n82.2.3.4 Control codes <\/td>\n<\/tr>\n
181<\/td>\n82.2.3.5 Valid and invalid blocks
82.2.3.6 Idle (\/I\/)
82.2.3.7 Start (\/S\/)
82.2.3.8 Terminate (\/T\/) <\/td>\n<\/tr>\n
182<\/td>\n82.2.3.9 ordered_set (\/O\/)
82.2.3.10 Error (\/E\/)
82.2.4 Transmit process
82.2.5 Scrambler
82.2.6 Block distribution <\/td>\n<\/tr>\n
183<\/td>\n82.2.7 Alignment marker insertion <\/td>\n<\/tr>\n
185<\/td>\n82.2.8 BIP calculations <\/td>\n<\/tr>\n
186<\/td>\n82.2.9 PMA or FEC Interface <\/td>\n<\/tr>\n
187<\/td>\n82.2.10 Test-pattern generators
82.2.11 Block synchronization
82.2.12 PCS lane deskew
82.2.13 PCS lane reorder <\/td>\n<\/tr>\n
188<\/td>\n82.2.14 Alignment marker removal
82.2.15 Descrambler
82.2.16 Receive process
82.2.17 Test-pattern checker <\/td>\n<\/tr>\n
189<\/td>\n82.2.18 Detailed functions and state diagrams
82.2.18.1 State diagram conventions
82.2.18.2 State variables
82.2.18.2.1 Constants
82.2.18.2.2 Variables <\/td>\n<\/tr>\n
191<\/td>\n82.2.18.2.3 Functions <\/td>\n<\/tr>\n
192<\/td>\n82.2.18.2.4 Counters <\/td>\n<\/tr>\n
193<\/td>\n82.2.18.2.5 Timers
82.2.18.3 State diagrams <\/td>\n<\/tr>\n
194<\/td>\n82.3 PCS Management
82.3.1 PMD MDIO function mapping <\/td>\n<\/tr>\n
195<\/td>\n82.4 Loopback
82.5 Delay constraints <\/td>\n<\/tr>\n
196<\/td>\n82.6 Auto-Negotiation <\/td>\n<\/tr>\n
202<\/td>\n82.7 Protocol implementation conformance statement (PICS) proforma for Clause 82, Physical Coding Sublayer (PCS) for 64B\/66B, type 40GBASE-R and 100GBASE-R
82.7.1 Introduction
82.7.2 Identification
82.7.2.1 Implementation identification
82.7.2.2 Protocol summary <\/td>\n<\/tr>\n
203<\/td>\n82.7.3 Major capabilities\/options <\/td>\n<\/tr>\n
204<\/td>\n82.7.4 PICS Proforma Tables for PCS, type 40GBASE-R and 100GBASE-R
82.7.4.1 Coding rules
82.7.4.2 Scrambler and Descrambler <\/td>\n<\/tr>\n
205<\/td>\n82.7.4.3 Deskew and Reordering
82.7.4.4 Alignment Markers
82.7.5 Test-pattern modes <\/td>\n<\/tr>\n
206<\/td>\n82.7.5.1 Bit order
82.7.6 Management <\/td>\n<\/tr>\n
207<\/td>\n82.7.6.1 State diagrams <\/td>\n<\/tr>\n
208<\/td>\n82.7.6.2 Loopback
82.7.6.3 Delay constraints
82.7.6.5 Auto-Negotiation for Backplane Ethernet functions <\/td>\n<\/tr>\n
209<\/td>\n83. Physical Medium Attachment (PMA) sublayer, type 40GBASE-R and 100GBASE-R
83.1 Overview
83.1.1 Scope
83.1.2 Position of the PMA in the 40GBASE-R or 100GBASE-R sublayers
83.1.3 Summary of functions
83.1.4 PMA sublayer positioning <\/td>\n<\/tr>\n
212<\/td>\n83.2 PMA interfaces
83.3 PMA service interface <\/td>\n<\/tr>\n
214<\/td>\n83.4 Service interface below PMA <\/td>\n<\/tr>\n
215<\/td>\n83.5 Functions within the PMA
83.5.1 Per input-lane clock and data recovery
83.5.2 Bit-level multiplexing <\/td>\n<\/tr>\n
218<\/td>\n83.5.3 Skew and Skew Variation
83.5.3.1 Skew generation toward SP1
83.5.3.2 Skew tolerance at SP1
83.5.3.3 Skew generation toward SP2
83.5.3.4 Skew tolerance at SP5
83.5.3.5 Skew generation at SP6 <\/td>\n<\/tr>\n
219<\/td>\n83.5.3.6 Skew tolerance at SP6
83.5.4 Delay constraints
83.5.5 Clocking architecture
83.5.6 Signal drivers <\/td>\n<\/tr>\n
220<\/td>\n83.5.7 Link status
83.5.8 PMA local loopback mode
83.5.9 PMA remote loopback mode (optional) <\/td>\n<\/tr>\n
221<\/td>\n83.5.10 PMA test patterns (optional) <\/td>\n<\/tr>\n
222<\/td>\n83.6 PMA MDIO function mapping <\/td>\n<\/tr>\n
227<\/td>\n83.7 Protocol implementation conformance statement (PICS) proforma for Clause 83, Physical Medium Attachment (PMA) sublayer, type 40GBASE-R and 100GBASE-R
83.7.1 Introduction
83.7.2 Identification
83.7.2.1 Implementation identification
83.7.2.2 Protocol summary <\/td>\n<\/tr>\n
228<\/td>\n83.7.3 Major capabilities\/options <\/td>\n<\/tr>\n
230<\/td>\n83.7.4 Skew generation and tolerance
83.7.5 Test patterns <\/td>\n<\/tr>\n
231<\/td>\n83.7.6 Loopback modes <\/td>\n<\/tr>\n
233<\/td>\n84. Physical Medium Dependent sublayer and baseband medium, type 40GBASE-KR4
84.1 Overview
84.2 Physical Medium Dependent (PMD) service interface <\/td>\n<\/tr>\n
234<\/td>\n84.3 PCS requirements for Auto-Negotiation (AN) service interface <\/td>\n<\/tr>\n
235<\/td>\n84.4 Delay constraints
84.5 Skew constraints
84.6 PMD MDIO function mapping
84.7 PMD functional specifications
84.7.1 Link block diagram
84.7.2 PMD transmit function <\/td>\n<\/tr>\n
237<\/td>\n84.7.3 PMD receive function
84.7.4 Global PMD signal detect function
84.7.5 PMD lane-by-lane signal detect function
84.7.6 Global PMD transmit disable function <\/td>\n<\/tr>\n
238<\/td>\n84.7.7 PMD lane-by-lane transmit disable function
84.7.8 Loopback mode
84.7.9 PMD_fault function
84.7.10 PMD transmit fault function
84.7.11 PMD receive fault function <\/td>\n<\/tr>\n
239<\/td>\n84.7.12 PMD control function
84.8 40GBASE-KR4 electrical characteristics
84.8.1 Transmitter characteristics
84.8.1.1 Test fixture
84.8.2 Receiver characteristics
84.8.2.1 Receiver interference tolerance
84.9 Interconnect characteristics
84.10 Environmental specifications
84.10.1 General safety <\/td>\n<\/tr>\n
240<\/td>\n84.10.2 Network safety
84.10.3 Installation and maintenance guidelines
84.10.4 Electromagnetic compatibility
84.10.5 Temperature and humidity <\/td>\n<\/tr>\n
241<\/td>\n84.11 Protocol implementation conformance statement (PICS) proforma for Clause 84, Physical Medium Dependent sublayer and baseband medium, type 40GBASE-KR4
84.11.1 Introduction
84.11.2 Identification
84.11.2.1 Implementation identification
84.11.2.2 Protocol summary <\/td>\n<\/tr>\n
242<\/td>\n84.11.3 Major capabilities\/options <\/td>\n<\/tr>\n
243<\/td>\n84.11.4 PICS proforma tables for Clause 84, Physical Medium Dependent (PMD) sublayer and baseband medium, type 40GBASE-KR4
84.11.4.1 PMD functional specifications <\/td>\n<\/tr>\n
244<\/td>\n84.11.4.2 Management functions
84.11.4.3 Transmitter electrical characteristics
84.11.4.4 Receiver electrical characteristics <\/td>\n<\/tr>\n
245<\/td>\n84.11.4.5 Environmental specifications <\/td>\n<\/tr>\n
247<\/td>\n85. Physical Medium Dependent sublayer and baseband medium, type 40GBASE-CR4 and 100GBASE-CR10
85.1 Overview <\/td>\n<\/tr>\n
248<\/td>\n85.2 Physical Medium Dependent (PMD) service interface <\/td>\n<\/tr>\n
249<\/td>\n85.3 PCS requirements for Auto-Negotiation (AN) service interface
85.4 Delay constraints
85.5 Skew constraints <\/td>\n<\/tr>\n
250<\/td>\n85.6 PMD MDIO function mapping <\/td>\n<\/tr>\n
252<\/td>\n85.7 PMD functional specifications
85.7.1 Link block diagram <\/td>\n<\/tr>\n
253<\/td>\n85.7.2 PMD Transmit function
85.7.3 PMD Receive function
85.7.4 Global PMD signal detect function <\/td>\n<\/tr>\n
254<\/td>\n85.7.5 PMD lane-by-lane signal detect function
85.7.6 Global PMD transmit disable function
85.7.7 PMD lane-by-lane transmit disable function
85.7.8 Loopback mode <\/td>\n<\/tr>\n
255<\/td>\n85.7.9 PMD_fault function
85.7.10 PMD transmit fault function
85.7.11 PMD receive fault function
85.7.12 PMD control function
85.8 MDI Electrical specifications for 40GBASE-CR4 and 100GBASE-CR10
85.8.1 Signal levels <\/td>\n<\/tr>\n
256<\/td>\n85.8.2 Signal paths
85.8.3 Transmitter characteristics <\/td>\n<\/tr>\n
257<\/td>\n85.8.3.1 Transmitter differential output return loss
85.8.3.2 Transmitter noise parameter measurements <\/td>\n<\/tr>\n
258<\/td>\n85.8.3.3 Transmitter output waveform <\/td>\n<\/tr>\n
260<\/td>\n85.8.3.3.1 Coefficient initialization
85.8.3.3.2 Coefficient step size
85.8.3.3.3 Coefficient range
85.8.3.3.4 Waveform acquisition
85.8.3.3.5 Linear fit to the waveform measurement at TP2 <\/td>\n<\/tr>\n
261<\/td>\n85.8.3.3.6 Transfer function between the transmit function and TP2 <\/td>\n<\/tr>\n
262<\/td>\n85.8.3.4 Insertion loss TP0 to TP2 or TP3 to TP5 <\/td>\n<\/tr>\n
263<\/td>\n85.8.3.5 Test fixture <\/td>\n<\/tr>\n
264<\/td>\n85.8.3.6 Test fixture impedance
85.8.3.7 Test fixture insertion loss
85.8.3.8 Data dependent jitter (DDJ)
85.8.3.9 Signaling rate range <\/td>\n<\/tr>\n
265<\/td>\n85.8.4 Receiver characteristics at TP3 summary
85.8.4.1 Receiver differential input return loss <\/td>\n<\/tr>\n
266<\/td>\n85.8.4.2 Receiver interference tolerance test
85.8.4.2.1 Test setup <\/td>\n<\/tr>\n
267<\/td>\n85.8.4.2.2 Test channel
85.8.4.2.3 Test channel calibration <\/td>\n<\/tr>\n
268<\/td>\n85.8.4.2.4 Pattern generator
85.8.4.2.5 Test procedure
85.8.4.3 Bit error ratio
85.8.4.4 Signaling rate range
85.8.4.5 AC coupling <\/td>\n<\/tr>\n
269<\/td>\n85.9 Channel characteristics
85.10 Cable assembly characteristics
85.10.1 Characteristic impedance and reference impedance
85.10.2 Cable assembly insertion loss <\/td>\n<\/tr>\n
271<\/td>\n85.10.3 Cable assembly insertion loss deviation (ILD) <\/td>\n<\/tr>\n
272<\/td>\n85.10.4 Cable assembly return loss <\/td>\n<\/tr>\n
273<\/td>\n85.10.5 Cable assembly multiple disturber near-end crosstalk (MDNEXT) loss
85.10.6 Cable assembly multiple disturber far-end crosstalk (MDFEXT) loss <\/td>\n<\/tr>\n
274<\/td>\n85.10.7 Cable assembly integrated crosstalk noise (ICN) <\/td>\n<\/tr>\n
276<\/td>\n85.10.8 Cable assembly test fixture
85.10.9 Mated test fixtures <\/td>\n<\/tr>\n
277<\/td>\n85.10.9.1 Mated test fixtures insertion loss
85.10.9.2 Mated test fixtures return loss <\/td>\n<\/tr>\n
278<\/td>\n85.10.9.3 Mated test fixtures common-mode return loss <\/td>\n<\/tr>\n
279<\/td>\n85.10.9.4 Mated test fixtures common-mode conversion loss <\/td>\n<\/tr>\n
280<\/td>\n85.10.9.5 Mated test fixtures integrated crosstalk noise
85.10.10 Shielding
85.10.11 Crossover function <\/td>\n<\/tr>\n
281<\/td>\n85.11 MDI specification
85.11.1 40GBASE-CR4 MDI connectors
85.11.1.1 Style-1 40GBASE-CR4 MDI connectors <\/td>\n<\/tr>\n
282<\/td>\n85.11.1.1.1 Style-1 AC coupling <\/td>\n<\/tr>\n
283<\/td>\n85.11.1.2 Style-2 40GBASE-CR4 MDI connectors
85.11.1.2.1 Style-2 40GBASE-CR4 Connector pin assignments <\/td>\n<\/tr>\n
284<\/td>\n85.11.2 100GBASE-CR10 MDI connectors <\/td>\n<\/tr>\n
286<\/td>\n85.11.2.1 100GBASE-CR10 MDI AC coupling
85.11.3 Electronic keying
85.12 Environmental specifications <\/td>\n<\/tr>\n
287<\/td>\n85.13 Protocol implementation conformance statement (PICS) proforma for Clause 85, Physical Medium Dependent (PMD) sublayer and baseband medium, type 40GBASE-CR4 and 100GBASE-CR10
85.13.1 Introduction
85.13.2 Identification
85.13.2.1 Implementation identification
85.13.2.2 Protocol summary <\/td>\n<\/tr>\n
288<\/td>\n85.13.3 PICS proforma tables for 40GBASE-CR4 and 100GBASE-CR10 PMDs and baseband medium
85.13.4 Major capabilities\/options <\/td>\n<\/tr>\n
290<\/td>\n85.13.4.1 PMD functional specifications <\/td>\n<\/tr>\n
291<\/td>\n85.13.4.2 Management functions <\/td>\n<\/tr>\n
292<\/td>\n85.13.4.3 Transmitter specifications
85.13.4.4 Receiver specifications <\/td>\n<\/tr>\n
293<\/td>\n85.13.4.5 Cable assembly specifications <\/td>\n<\/tr>\n
294<\/td>\n85.13.4.6 MDI connector specifications
85.13.4.7 Environmental specifications <\/td>\n<\/tr>\n
295<\/td>\n86. Physical Medium Dependent (PMD) sublayer and medium, type 40GBASE\u2013SR4 and 100GBASE\u2013SR10
86.1 Overview <\/td>\n<\/tr>\n
297<\/td>\n86.2 Physical Medium Dependent (PMD) service interface <\/td>\n<\/tr>\n
298<\/td>\n86.3 Delay and Skew
86.3.1 Delay constraints
86.3.2 Skew and Skew Variation constraints
86.4 PMD MDIO function mapping <\/td>\n<\/tr>\n
299<\/td>\n86.5 PMD functional specifications
86.5.1 PMD block diagram <\/td>\n<\/tr>\n
300<\/td>\n86.5.2 PMD transmit function
86.5.3 PMD receive function
86.5.4 PMD global signal detect function <\/td>\n<\/tr>\n
301<\/td>\n86.5.5 PMD lane-by-lane signal detect function
86.5.6 PMD reset function
86.5.7 PMD global transmit disable function (optional) <\/td>\n<\/tr>\n
302<\/td>\n86.5.8 PMD lane-by-lane transmit disable function (optional)
86.5.9 PMD fault function (optional)
86.5.10 PMD transmit fault function (optional)
86.5.11 PMD receive fault function (optional)
86.6 Lane assignments
86.7 PMD to MDI specifications for 40GBASE-SR4 or 100GBASE-SR10 <\/td>\n<\/tr>\n
303<\/td>\n86.7.1 Transmitter optical specifications <\/td>\n<\/tr>\n
304<\/td>\n86.7.2 Characteristics of signal within, and at the receiving end of, a compliant optical channel <\/td>\n<\/tr>\n
305<\/td>\n86.7.3 40GBASE\u2013SR4 or 100GBASE\u2013SR10 receiver optical specifications <\/td>\n<\/tr>\n
306<\/td>\n86.7.4 40GBASE\u2013SR4 or 100GBASE\u2013SR10 illustrative link power budget
86.8 Definitions of optical and dual-use parameters and measurement methods
86.8.1 Test points and compliance boards <\/td>\n<\/tr>\n
308<\/td>\n86.8.2 Test patterns and related subclauses <\/td>\n<\/tr>\n
309<\/td>\n86.8.2.1 Multi-lane testing considerations
86.8.3 Parameters applicable to both electrical and optical signals
86.8.3.1 Skew and Skew Variation <\/td>\n<\/tr>\n
310<\/td>\n86.8.3.2 Eye diagrams
86.8.3.2.1 Eye mask acceptable hit count examples
86.8.3.3 Jitter
86.8.3.3.1 J2 Jitter
86.8.3.3.2 J9 Jitter <\/td>\n<\/tr>\n
311<\/td>\n86.8.4 Optical parameter definitions
86.8.4.1 Wavelength and spectral width
86.8.4.2 Average optical power
86.8.4.3 Optical Modulation Amplitude (OMA)
86.8.4.4 Transmitter and dispersion penalty (TDP)
86.8.4.5 Extinction ratio
86.8.4.6 Transmitter optical waveform (transmit eye) <\/td>\n<\/tr>\n
312<\/td>\n86.8.4.6.1 Optical transmitter eye mask <\/td>\n<\/tr>\n
313<\/td>\n86.8.4.7 Stressed receiver sensitivity
86.8.4.8 Receiver jitter tolerance <\/td>\n<\/tr>\n
314<\/td>\n86.9 Safety, installation, environment, and labeling
86.9.1 General safety
86.9.2 Laser safety
86.9.3 Installation
86.9.4 Environment
86.9.5 PMD labeling
86.10 Optical channel
86.10.1 Fiber optic cabling model <\/td>\n<\/tr>\n
315<\/td>\n86.10.2 Characteristics of the fiber optic cabling (channel)
86.10.2.1 Optical fiber cable
86.10.2.2 Optical fiber connection <\/td>\n<\/tr>\n
316<\/td>\n86.10.2.2.1 Connection insertion loss
86.10.2.2.2 Maximum discrete reflectance
86.10.3 Medium Dependent Interface (MDI)
86.10.3.1 Optical lane assignments for 40GBASE-SR4 <\/td>\n<\/tr>\n
317<\/td>\n86.10.3.2 Optical lane assignments for 100GBASE-SR10
86.10.3.3 Medium Dependent Interface (MDI) requirements <\/td>\n<\/tr>\n
319<\/td>\n86.11 Protocol implementation conformance statement (PICS) proforma for Clause 86, Physical Medium Dependent (PMD) sublayer and medium, type 40GBASE\u2013SR4 and 100GBASE\u2013SR10
86.11.1 Introduction
86.11.2 Identification
86.11.2.1 Implementation identification
86.11.2.2 Protocol summary <\/td>\n<\/tr>\n
320<\/td>\n86.11.3 Major capabilities\/options <\/td>\n<\/tr>\n
321<\/td>\n86.11.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and medium, types 40GBASE\u2013SR4 and 100GBASE\u2013SR10
86.11.4.1 PMD functional specifications <\/td>\n<\/tr>\n
322<\/td>\n86.11.4.2 Management functions
86.11.4.3 Optical specifications for 40GBASE\u2013SR4 or 100GBASE\u2013SR10 <\/td>\n<\/tr>\n
323<\/td>\n86.11.4.4 Definitions of parameters and measurement methods
86.11.4.5 Environmental and safety specifications <\/td>\n<\/tr>\n
324<\/td>\n86.11.4.6 Optical channel and MDI <\/td>\n<\/tr>\n
325<\/td>\n87. Physical Medium Dependent (PMD) sublayer and medium, type 40GBASE\u2013LR4
87.1 Overview
87.2 Physical Medium Dependent (PMD) service interface <\/td>\n<\/tr>\n
327<\/td>\n87.3 Delay and Skew
87.3.1 Delay constraints
87.3.2 Skew constraints
87.4 PMD MDIO function mapping
87.5 PMD functional specifications
87.5.1 PMD block diagram <\/td>\n<\/tr>\n
328<\/td>\n87.5.2 PMD transmit function <\/td>\n<\/tr>\n
329<\/td>\n87.5.3 PMD receive function
87.5.4 PMD global signal detect function <\/td>\n<\/tr>\n
330<\/td>\n87.5.5 PMD lane-by-lane signal detect function
87.5.6 PMD reset function
87.5.7 PMD global transmit disable function (optional)
87.5.8 PMD lane-by-lane transmit disable function <\/td>\n<\/tr>\n
331<\/td>\n87.5.9 PMD fault function (optional)
87.5.10 PMD transmit fault function (optional)
87.5.11 PMD receive fault function (optional)
87.6 Wavelength-division-multiplexed lane assignments
87.7 PMD to MDI optical specifications for 40GBASE\u2013LR4 <\/td>\n<\/tr>\n
332<\/td>\n87.7.1 40GBASE\u2013LR4 transmitter optical specifications <\/td>\n<\/tr>\n
333<\/td>\n87.7.2 40GBASE\u2013LR4 receive optical specifications
87.7.3 40GBASE\u2013LR4 illustrative link power budget <\/td>\n<\/tr>\n
334<\/td>\n87.8 Definition of optical parameters and measurement methods
87.8.1 Test patterns for optical parameters
87.8.2 Skew and Skew Variation <\/td>\n<\/tr>\n
335<\/td>\n87.8.3 Wavelength
87.8.4 Average optical power
87.8.5 Optical Modulation Amplitude (OMA) <\/td>\n<\/tr>\n
336<\/td>\n87.8.6 Transmitter and dispersion penalty
87.8.6.1 Reference transmitter requirements
87.8.6.2 Channel requirements <\/td>\n<\/tr>\n
337<\/td>\n87.8.6.3 Reference receiver requirements
87.8.6.4 Test procedure
87.8.7 Extinction ratio
87.8.8 Relative Intensity Noise (RIN20OMA)
87.8.9 Transmitter optical waveform (transmit eye) <\/td>\n<\/tr>\n
338<\/td>\n87.8.10 Receiver sensitivity
87.8.11 Stressed receiver sensitivity
87.8.11.1 Stressed receiver conformance test block diagram <\/td>\n<\/tr>\n
339<\/td>\n87.8.11.2 Stressed receiver conformance test signal characteristics and calibration <\/td>\n<\/tr>\n
341<\/td>\n87.8.11.3 Stressed receiver conformance test signal verification
87.8.11.4 Sinusoidal jitter for receiver conformance test <\/td>\n<\/tr>\n
342<\/td>\n87.8.11.5 Stressed receiver conformance test procedure for WDM conformance testing <\/td>\n<\/tr>\n
343<\/td>\n87.8.12 Receiver 3 dB electrical upper cutoff frequency
87.9 Safety, installation, environment, and labeling
87.9.1 General safety
87.9.2 Laser safety <\/td>\n<\/tr>\n
344<\/td>\n87.9.3 Installation
87.9.4 Environment
87.9.4.1 Electromagnetic emission
87.9.4.2 Temperature, humidity, and handling
87.9.5 PMD labeling requirements <\/td>\n<\/tr>\n
345<\/td>\n87.10 Fiber optic cabling model
87.11 Characteristics of the fiber optic cabling (channel) <\/td>\n<\/tr>\n
346<\/td>\n87.11.1 Optical fiber cable
87.11.2 Optical fiber connection
87.11.2.1 Connection insertion loss
87.11.2.2 Maximum discrete reflectance
87.11.3 Medium Dependent Interface (MDI) requirements <\/td>\n<\/tr>\n
347<\/td>\n87.12 Protocol implementation conformance statement (PICS) proforma for Clause 87, Physical Medium Dependent (PMD) sublayer and medium, type 40GBASE-LR4
87.12.1 Introduction
87.12.2 Identification
87.12.2.1 Implementation identification
87.12.2.2 Protocol summary <\/td>\n<\/tr>\n
348<\/td>\n87.12.3 Major capabilities\/options <\/td>\n<\/tr>\n
349<\/td>\n87.12.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and medium, type 40GBASE-LR4
87.12.4.1 PMD functional specifications <\/td>\n<\/tr>\n
350<\/td>\n87.12.4.2 Management functions
87.12.4.3 PMD to MDI optical specifications for 40GBASE-LR4 <\/td>\n<\/tr>\n
351<\/td>\n87.12.4.4 Optical measurement methods
87.12.4.5 Environmental specifications
87.12.4.6 Characteristics of the fiber optic cabling and MDI <\/td>\n<\/tr>\n
353<\/td>\n88. Physical Medium Dependent (PMD) sublayer and medium, type 100GBASE\u2013LR4 and 100GBASE\u2013ER4
88.1 Overview
88.2 Physical Medium Dependent (PMD) service interface <\/td>\n<\/tr>\n
355<\/td>\n88.3 Delay and Skew
88.3.1 Delay constraints
88.3.2 Skew constraints
88.4 PMD MDIO function mapping
88.5 PMD functional specifications
88.5.1 PMD block diagram <\/td>\n<\/tr>\n
357<\/td>\n88.5.2 PMD transmit function
88.5.3 PMD receive function
88.5.4 PMD global signal detect function <\/td>\n<\/tr>\n
358<\/td>\n88.5.5 PMD lane-by-lane signal detect function
88.5.6 PMD reset function
88.5.7 PMD global transmit disable function (optional)
88.5.8 PMD lane-by-lane transmit disable function <\/td>\n<\/tr>\n
359<\/td>\n88.5.9 PMD fault function (optional)
88.5.10 PMD transmit fault function (optional)
88.5.11 PMD receive fault function (optional)
88.6 Wavelength-division-multiplexed lane assignments
88.7 PMD to MDI optical specifications for 100GBASE\u2013LR4 and 100GBASE\u2013ER4 <\/td>\n<\/tr>\n
360<\/td>\n88.7.1 100GBASE\u2013LR4 and 100GBASE\u2013ER4 transmitter optical specifications <\/td>\n<\/tr>\n
362<\/td>\n88.7.2 100GBASE\u2013LR4 and 100GBASE\u2013ER4 receive optical specifications <\/td>\n<\/tr>\n
363<\/td>\n88.7.3 100GBASE\u2013LR4 and 100GBASE\u2013ER4 illustrative link power budgets
88.8 Definition of optical parameters and measurement methods
88.8.1 Test patterns for optical parameters
88.8.2 Wavelength <\/td>\n<\/tr>\n
364<\/td>\n88.8.3 Average optical power
88.8.4 Optical Modulation Amplitude (OMA) <\/td>\n<\/tr>\n
365<\/td>\n88.8.5 Transmitter and dispersion penalty (TDP)
88.8.5.1 Reference transmitter requirements
88.8.5.2 Channel requirements <\/td>\n<\/tr>\n
366<\/td>\n88.8.5.3 Reference receiver requirements
88.8.5.4 Test procedure
88.8.6 Extinction ratio
88.8.7 Relative Intensity Noise (RIN20OMA)
88.8.8 Transmitter optical waveform (transmit eye) <\/td>\n<\/tr>\n
367<\/td>\n88.8.9 Receiver sensitivity
88.8.10 Stressed receiver sensitivity
88.8.11 Receiver 3 dB electrical upper cutoff frequency
88.9 Safety, installation, environment, and labeling
88.9.1 General safety
88.9.2 Laser safety <\/td>\n<\/tr>\n
368<\/td>\n88.9.3 Installation
88.9.4 Environment
88.9.5 Electromagnetic emission
88.9.6 Temperature, humidity, and handling
88.9.7 PMD labeling requirements <\/td>\n<\/tr>\n
369<\/td>\n88.10 Fiber optic cabling model
88.11 Characteristics of the fiber optic cabling (channel) <\/td>\n<\/tr>\n
370<\/td>\n88.11.1 Optical fiber cable
88.11.2 Optical fiber connection
88.11.2.1 Connection insertion loss
88.11.2.2 Maximum discrete reflectance
88.11.3 Medium Dependent Interface (MDI) requirements <\/td>\n<\/tr>\n
371<\/td>\n88.12 Protocol implementation conformance statement (PICS) proforma for Clause 88, Physical Medium Dependent (PMD) sublayer and medium, type 100GBASE\u2013LR4 and 100GBASE\u2013ER4
88.12.1 Introduction
88.12.2 Identification
88.12.2.1 Implementation identification
88.12.2.2 Protocol summary <\/td>\n<\/tr>\n
372<\/td>\n88.12.3 Major capabilities\/options <\/td>\n<\/tr>\n
373<\/td>\n88.12.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and medium, types 100GBASE\u2013LR4 and 100GBASE\u2013ER4
88.12.4.1 PMD functional specifications <\/td>\n<\/tr>\n
374<\/td>\n88.12.4.2 Management functions
88.12.4.3 PMD to MDI optical specifications for 100GBASE\u2013LR4
88.12.4.4 PMD to MDI optical specifications for 100GBASE\u2013ER4 <\/td>\n<\/tr>\n
375<\/td>\n88.12.4.5 Optical measurement methods
88.12.4.6 Environmental specifications
88.12.4.7 Characteristics of the fiber optic cabling and MDI <\/td>\n<\/tr>\n
377<\/td>\nAnnex A (informative) Bibliography
Bibliography <\/td>\n<\/tr>\n
379<\/td>\nAnnex 4A (normative) Simplified full duplex media access control
Simplified full duplex media access control
4A.4.2 MAC parameters <\/td>\n<\/tr>\n
381<\/td>\nAnnex 31B (normative) MAC Control PAUSE operation
MAC Control PAUSE operation
31B.3.7 Timing considerations for PAUSE operation <\/td>\n<\/tr>\n
382<\/td>\n31B.4 Protocol implementation conformance statement (PICS) proforma for MAC Control PAUSE operation
31B.4.3 Major capabilities\/options <\/td>\n<\/tr>\n
383<\/td>\n31B.4.6 PAUSE command MAC timing considerations <\/td>\n<\/tr>\n
385<\/td>\nAnnex 69A (normative) Interference tolerance testing
Interference tolerance testing <\/td>\n<\/tr>\n
387<\/td>\nAnnex 69B (informative) Interconnect characteristics
Interconnect characteristics <\/td>\n<\/tr>\n
391<\/td>\nAnnex 83A (normative) 40 Gb\/s Attachment Unit Interface (XLAUI) and 100 Gb\/s Attachment Unit Interface (CAUI)
40 Gb\/s Attachment Unit Interface (XLAUI) and 100 Gb\/s Attachment Unit Interface (CAUI)
83A.1 Overview <\/td>\n<\/tr>\n
392<\/td>\n83A.1.1 Summary of major concepts
83A.1.2 Rate of operation
83A.2 XLAUI\/CAUI link block diagram <\/td>\n<\/tr>\n
393<\/td>\n83A.2.1 Transmitter compliance points <\/td>\n<\/tr>\n
394<\/td>\n83A.2.2 Receiver compliance points
83A.3 XLAUI\/CAUI electrical characteristics
83A.3.1 Signal levels <\/td>\n<\/tr>\n
395<\/td>\n83A.3.2 Signal paths
83A.3.3 Transmitter characteristics
83A.3.3.1 Output amplitude <\/td>\n<\/tr>\n
396<\/td>\n83A.3.3.2 Rise\/fall time <\/td>\n<\/tr>\n
397<\/td>\n83A.3.3.3 Differential output return loss
83A.3.3.4 Common-mode output return loss <\/td>\n<\/tr>\n
398<\/td>\n83A.3.3.5 Transmitter eye mask and transmitter jitter definition <\/td>\n<\/tr>\n
399<\/td>\n83A.3.4 Receiver characteristics <\/td>\n<\/tr>\n
400<\/td>\n83A.3.4.1 Bit error ratio
83A.3.4.2 Input signal definition
83A.3.4.3 Differential input return loss <\/td>\n<\/tr>\n
401<\/td>\n83A.3.4.4 Differential to common-mode input return loss <\/td>\n<\/tr>\n
402<\/td>\n83A.3.4.5 AC coupling
83A.3.4.6 Jitter tolerance <\/td>\n<\/tr>\n
403<\/td>\n83A.4 Interconnect characteristics <\/td>\n<\/tr>\n
404<\/td>\n83A.4.1 Characteristic impedance <\/td>\n<\/tr>\n
405<\/td>\n83A.5 Electrical parameter measurement methods
83A.5.1 Transmit jitter
83A.5.2 Receiver tolerance <\/td>\n<\/tr>\n
406<\/td>\n83A.6 Environmental specifications
83A.6.1 General safety
83A.6.2 Network safety
83A.6.3 Installation and maintenance guidelines
83A.6.4 Electromagnetic compatibility
83A.6.5 Temperature and humidity <\/td>\n<\/tr>\n
407<\/td>\n83A.7 Protocol implementation conformance statement (PICS) proforma for Annex 83A, 40 Gb\/s Attachment Unit Interface (XLAUI) and 100 Gb\/s Attachment Unit Interface (CAUI)
83A.7.1 Introduction
83A.7.2 Identification
83A.7.2.1 Implementation identification
83A.7.2.2 Protocol summary <\/td>\n<\/tr>\n
408<\/td>\n83A.7.3 Major capabilities\/options
83A.7.4 XLAUI\/CAUI transmitter requirements <\/td>\n<\/tr>\n
409<\/td>\n83A.7.5 XLAUI\/CAUI receiver requirements
83A.7.6 Electrical measurement methods
83A.7.7 Environmental specifications <\/td>\n<\/tr>\n
411<\/td>\nAnnex 83B (normative) Chip-module 40 Gb\/s Attachment Unit Interface (XLAUI) and 100 Gb\/s Attachment Unit Interface (CAUI)
Chip-module 40 Gb\/s Attachment Unit Interface (XLAUI) and 100 Gb\/s Attachment Unit Interface (CAUI)
83B.1 Overview <\/td>\n<\/tr>\n
413<\/td>\n83B.2 Compliance point specifications for chip-module XLAUI\/CAUI <\/td>\n<\/tr>\n
415<\/td>\n83B.2.1 Module specifications <\/td>\n<\/tr>\n
417<\/td>\n83B.2.2 Host specifications <\/td>\n<\/tr>\n
418<\/td>\n83B.2.3 Host input signal tolerance <\/td>\n<\/tr>\n
419<\/td>\n83B.3 Environmental specifications
83B.3.1 General safety
83B.3.2 Network safety
83B.3.3 Installation and maintenance guidelines
83B.3.4 Electromagnetic compatibility <\/td>\n<\/tr>\n
420<\/td>\n83B.3.5 Temperature and humidity <\/td>\n<\/tr>\n
421<\/td>\n83B.4 Protocol implementation conformance statement (PICS) proforma for Annex 83B, Chip-module 40 Gb\/s Attachment Unit Interface (XLAUI) and 100 Gb\/s Attachment Unit Interface (CAUI)
83B.4.1 Introduction
83B.4.2 Identification
83B.4.2.1 Implementation identification
83B.4.2.2 Protocol summary <\/td>\n<\/tr>\n
422<\/td>\n83B.4.3 Major capabilities\/options
83B.4.4 Module requirements
83B.4.5 Host requirements <\/td>\n<\/tr>\n
423<\/td>\n83B.4.6 Environmental specifications <\/td>\n<\/tr>\n
425<\/td>\nAnnex 83C (informative) PMA sublayer partitioning examples
PMA sublayer partitioning examples
83C.1 Partitioning examples with FEC
83C.1.1 FEC implemented with PCS <\/td>\n<\/tr>\n
426<\/td>\n83C.1.2 FEC implemented with PMD
83C.2 Partitioning examples without FEC
83C.2.1 Single PMA sublayer without FEC <\/td>\n<\/tr>\n
427<\/td>\n83C.2.2 Single XLAUI\/CAUI without FEC
83C.2.3 Separate SERDES for optical module interface <\/td>\n<\/tr>\n
429<\/td>\nAnnex 85A (informative) 40GBASE-CR4 and 100GBASE-CR10 TP0 and TP5 test point parameters
40GBASE-CR4 and 100GBASE-CR10 TP0 and TP5 test point parameters
85A.1 Overview
85A.2 Transmitter characteristics at TP0 <\/td>\n<\/tr>\n
430<\/td>\n85A.3 Receiver characteristics at TP5
85A.4 Transmitter and receiver differential printed circuit board trace loss <\/td>\n<\/tr>\n
431<\/td>\n85A.5 Channel insertion loss <\/td>\n<\/tr>\n
432<\/td>\n85A.6 Channel return loss
85A.7 Channel insertion loss deviation (ILD) <\/td>\n<\/tr>\n
433<\/td>\n85A.8 Channel integrated crosstalk noise (ICN) <\/td>\n<\/tr>\n
435<\/td>\nAnnex 86A (normative) Parallel Physical Interface (nPPI) for 40GBASE-SR4 and 40GBASE-LR4 (XLPPI) and 100GBASE-SR10 (CPPI)
Parallel Physical Interface (nPPI) for 40GBASE-SR4 and 40GBASE-LR4 (XLPPI) and 100GBASE-SR10 (CPPI)
86A.1 Overview
86A.2 Block diagram and test points
86A.3 Lane assignments <\/td>\n<\/tr>\n
436<\/td>\n86A.4 Electrical specifications for nPPI
86A.4.1 nPPI host to module electrical specifications <\/td>\n<\/tr>\n
437<\/td>\n86A.4.1.1 Differential return losses at TP1 and TP1a <\/td>\n<\/tr>\n
438<\/td>\n86A.4.1.2 Common-mode output return loss at TP1a
86A.4.2 nPPI module to host electrical specifications
86A.4.2.1 Differential return losses at TP4 and TP4a <\/td>\n<\/tr>\n
439<\/td>\n86A.4.2.2 Common-mode output return loss at TP4
86A.5 Definitions of electrical parameters and measurement methods
86A.5.1 Test points and compliance boards <\/td>\n<\/tr>\n
441<\/td>\n86A.5.1.1 Compliance board parameters
86A.5.1.1.1 Reference insertion losses of HCB and MCB <\/td>\n<\/tr>\n
442<\/td>\n86A.5.1.1.2 Electrical specifications of mated HCB and MCB <\/td>\n<\/tr>\n
444<\/td>\n86A.5.2 Test patterns and related subclauses <\/td>\n<\/tr>\n
445<\/td>\n86A.5.3 Parameter definitions
86A.5.3.1 AC common-mode voltage
86A.5.3.2 Termination mismatch <\/td>\n<\/tr>\n
446<\/td>\n86A.5.3.3 Transition time
86A.5.3.4 Data Dependent Pulse Width Shrinkage (DDPWS) <\/td>\n<\/tr>\n
447<\/td>\n86A.5.3.5 Signal to noise ratio Qsq <\/td>\n<\/tr>\n
448<\/td>\n86A.5.3.6 Eye mask for TP1a and TP4
86A.5.3.7 Reference impedances for electrical measurements
86A.5.3.8 Host input signal tolerance
86A.5.3.8.1 Introduction
86A.5.3.8.2 Test equipment and setup
86A.5.3.8.3 Stressed eye jitter characteristics <\/td>\n<\/tr>\n
450<\/td>\n86A.5.3.8.4 Calibration
86A.5.3.8.5 Calibration procedure <\/td>\n<\/tr>\n
451<\/td>\n86A.5.3.8.6 Test procedure <\/td>\n<\/tr>\n
452<\/td>\n86A.6 Recommended electrical channel <\/td>\n<\/tr>\n
453<\/td>\n86A.7 Safety, installation, environment, and labeling
86A.7.1 General safety
86A.7.2 Installation
86A.7.3 Environment
86A.7.4 PMD labeling <\/td>\n<\/tr>\n
454<\/td>\n86A.8 Protocol implementation conformance statement (PICS) proforma for Annex 86A, Parallel Physical Interface (nPPI) for 40GBASE-SR4 and 40GBASE-LR4 (XLPPI) and 100GBASE-SR10 (CPPI)
86A.8.1 Introduction
86A.8.2 Identification
86A.8.2.1 Implementation identification
86A.8.2.2 Protocol summary <\/td>\n<\/tr>\n
455<\/td>\n86A.8.3 Major capabilities\/options
86A.8.4 PICS proforma tables for Parallel Physical Interface (nPPI) for 40GBASE- SR4 and 40GBASE-LR4 (XLPPI) and 100GBASE-SR10 (CPPI)
86A.8.4.1 PMD functional specifications <\/td>\n<\/tr>\n
456<\/td>\n86A.8.4.2 Electrical specifications for nPPI
86A.8.4.3 Definitions of parameters and measurement methods <\/td>\n<\/tr>\n
457<\/td>\n86A.8.4.4 Environmental and safety specifications <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard for Information technology– Local and metropolitan area networks– Specific requirements– Part 3: CSMA\/CD Access Method and Physical Layer Specifications Amendment 4: Media Access Control Parameters, Physical Layers, and Management Parameters for 40 Gb\/s and 100 Gb\/s Operation<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n2010<\/td>\n457<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":136472,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-136470","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/136470","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/136472"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=136470"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=136470"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=136470"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}