{"id":136582,"date":"2024-10-19T07:52:51","date_gmt":"2024-10-19T07:52:51","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-iec-61523-4-2015\/"},"modified":"2024-10-25T00:02:46","modified_gmt":"2024-10-25T00:02:46","slug":"ieee-iec-61523-4-2015","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-iec-61523-4-2015\/","title":{"rendered":"IEEE IEC 61523 4 2015"},"content":{"rendered":"

Adoption Standard – Active. A method is provided for specifying power intent for an electronic design, for use in verification of the structure and behavior of the design in the context of a given power management architecture, and for driving implementation of that power management architecture. The method supports incremental refinement of power intent specifications required for IP-based design flows.<\/p>\n

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
1<\/td>\nIEC 61523-4 (IEEE Std 1801-2013) Front Cover <\/td>\n<\/tr>\n
4<\/td>\nContents <\/td>\n<\/tr>\n
12<\/td>\nIntroduction
\n <\/td>\n<\/tr>\n
16<\/td>\nImportant Notice
1. Overview <\/td>\n<\/tr>\n
18<\/td>\n1.4 Use of color in this standard
1.5 Contents of this standard <\/td>\n<\/tr>\n
19<\/td>\n2. Normative references
3. Definitions, acronyms, and abbreviations
3.1 Definitions <\/td>\n<\/tr>\n
24<\/td>\n3.2 Acronyms and abbreviations <\/td>\n<\/tr>\n
26<\/td>\n4. UPF concepts
4.1 Design structure
4.1.1 Transistors
4.1.2 Standard cells
4.1.3 Hard macros
4.2 Design representation
4.2.1 Models <\/td>\n<\/tr>\n
27<\/td>\n4.2.2 Netlist
4.2.3 Behavioral models
4.2.4 HDL scopes
4.2.5 Design hierarchy <\/td>\n<\/tr>\n
28<\/td>\n4.2.6 Logic hierarchy
4.2.7 Hierarchy navigation <\/td>\n<\/tr>\n
29<\/td>\n4.2.8 Ports and nets
4.2.9 Connecting nets to ports
4.3 Power architecture <\/td>\n<\/tr>\n
30<\/td>\n4.3.1 Power domains
4.3.2 Drivers, receivers, sources, and sinks <\/td>\n<\/tr>\n
31<\/td>\n4.3.3 Isolation and level-shifting <\/td>\n<\/tr>\n
32<\/td>\n4.3.4 State retention
4.4 Power distribution <\/td>\n<\/tr>\n
33<\/td>\n4.4.1 Supply network elements <\/td>\n<\/tr>\n
34<\/td>\n4.4.2 Supply network construction <\/td>\n<\/tr>\n
36<\/td>\n4.4.3 Supply equivalence <\/td>\n<\/tr>\n
38<\/td>\n4.5 Power management
4.5.1 Related supplies
4.5.2 Driver and receiver supplies <\/td>\n<\/tr>\n
39<\/td>\n4.5.3 Logic sources and sinks
4.5.4 Power-management requirements <\/td>\n<\/tr>\n
40<\/td>\n4.5.5 Power-management strategies
4.5.6 Power-management implementation <\/td>\n<\/tr>\n
41<\/td>\n4.5.7 Power control logic
4.6 Power states
4.6.1 Power state of a supply port or supply net
4.6.2 Power state of a supply set <\/td>\n<\/tr>\n
42<\/td>\n4.6.3 Predefined supply set power states
4.6.4 Power states of power domains <\/td>\n<\/tr>\n
43<\/td>\n4.6.5 Power states of systems and subsystems
4.6.6 Incremental refinement of power states <\/td>\n<\/tr>\n
44<\/td>\n4.7 Simstates <\/td>\n<\/tr>\n
45<\/td>\n4.8 Successive refinement <\/td>\n<\/tr>\n
46<\/td>\n4.9 Tool flow <\/td>\n<\/tr>\n
47<\/td>\n4.10 File structure <\/td>\n<\/tr>\n
48<\/td>\n5. Language basics
5.1 UPF is Tcl
5.2 Conventions used <\/td>\n<\/tr>\n
49<\/td>\n5.3 Lexical elements <\/td>\n<\/tr>\n
50<\/td>\n5.3.1 Identifiers
5.3.2 Keywords and reserved words
5.3.3 Names <\/td>\n<\/tr>\n
52<\/td>\n5.3.4 Lists and strings
5.3.5 Special characters
5.4 Boolean expressions <\/td>\n<\/tr>\n
54<\/td>\n5.5 Object declaration <\/td>\n<\/tr>\n
55<\/td>\n5.6 Attributes of objects <\/td>\n<\/tr>\n
58<\/td>\n5.7 Power state name spaces <\/td>\n<\/tr>\n
59<\/td>\n5.8 Precedence <\/td>\n<\/tr>\n
60<\/td>\n5.9 Generic UPF command semantics
5.10 effective_element_list semantics <\/td>\n<\/tr>\n
61<\/td>\n5.10.1 Transitive TRUE <\/td>\n<\/tr>\n
62<\/td>\n5.10.2 Result <\/td>\n<\/tr>\n
63<\/td>\n5.11 Command refinement <\/td>\n<\/tr>\n
64<\/td>\n5.12 Error handling <\/td>\n<\/tr>\n
65<\/td>\n5.12.1 errorCode
5.12.2 errorInfo
5.13 Units <\/td>\n<\/tr>\n
66<\/td>\n6. Power intent commands
6.1 Categories
6.2 add_domain_elements [deprecated] <\/td>\n<\/tr>\n
67<\/td>\n6.3 add_port_state [legacy]
6.4 add_power_state <\/td>\n<\/tr>\n
72<\/td>\n6.5 add_pst_state [legacy] <\/td>\n<\/tr>\n
73<\/td>\n6.6 apply_power_model <\/td>\n<\/tr>\n
74<\/td>\n6.7 associate_supply_set <\/td>\n<\/tr>\n
75<\/td>\n6.8 begin_power_model <\/td>\n<\/tr>\n
76<\/td>\n6.9 bind_checker <\/td>\n<\/tr>\n
78<\/td>\n6.10 connect_logic_net <\/td>\n<\/tr>\n
79<\/td>\n6.11 connect_supply_net <\/td>\n<\/tr>\n
80<\/td>\n6.12 connect_supply_set <\/td>\n<\/tr>\n
82<\/td>\n6.13 create_composite_domain <\/td>\n<\/tr>\n
83<\/td>\n6.14 create_hdl2upf_vct <\/td>\n<\/tr>\n
84<\/td>\n6.15 create_logic_net <\/td>\n<\/tr>\n
85<\/td>\n6.16 create_logic_port <\/td>\n<\/tr>\n
86<\/td>\n6.17 create_power_domain <\/td>\n<\/tr>\n
89<\/td>\n6.18 create_power_switch <\/td>\n<\/tr>\n
95<\/td>\n6.19 create_pst [legacy]
6.20 create_supply_net <\/td>\n<\/tr>\n
96<\/td>\n6.20.1 Supply net resolution
6.20.2 Resolutions methods <\/td>\n<\/tr>\n
97<\/td>\n6.20.3 Supply nets defined in HDL <\/td>\n<\/tr>\n
98<\/td>\n6.21 create_supply_port <\/td>\n<\/tr>\n
99<\/td>\n6.22 create_supply_set <\/td>\n<\/tr>\n
100<\/td>\n6.22.1 Referencing supply set functions
6.22.2 Implicit supply net
6.23 create_upf2hdl_vct <\/td>\n<\/tr>\n
101<\/td>\n6.24 describe_state_transition <\/td>\n<\/tr>\n
102<\/td>\n6.25 end_power_model <\/td>\n<\/tr>\n
103<\/td>\n6.26 find_objects <\/td>\n<\/tr>\n
104<\/td>\n6.26.1 Pattern matching and wildcarding
6.26.2 Wildcarding examples <\/td>\n<\/tr>\n
105<\/td>\n6.27 load_simstate_behavior <\/td>\n<\/tr>\n
106<\/td>\n6.28 load_upf <\/td>\n<\/tr>\n
107<\/td>\n6.29 load_upf_protected <\/td>\n<\/tr>\n
108<\/td>\n6.30 map_isolation_cell [deprecated]
6.31 map_level_shifter_cell [deprecated]
6.32 map_power_switch <\/td>\n<\/tr>\n
109<\/td>\n6.33 map_retention_cell <\/td>\n<\/tr>\n
112<\/td>\n6.34 merge_power_domains [deprecated] <\/td>\n<\/tr>\n
113<\/td>\n6.35 name_format <\/td>\n<\/tr>\n
114<\/td>\n6.36 save_upf <\/td>\n<\/tr>\n
115<\/td>\n6.37 set_design_attributes <\/td>\n<\/tr>\n
116<\/td>\n6.38 set_design_top
6.39 set_domain_supply_net [legacy] <\/td>\n<\/tr>\n
117<\/td>\n6.40 set_equivalent <\/td>\n<\/tr>\n
119<\/td>\n6.41 set_isolation <\/td>\n<\/tr>\n
125<\/td>\n6.42 set_isolation_control [deprecated] <\/td>\n<\/tr>\n
126<\/td>\n6.43 set_level_shifter <\/td>\n<\/tr>\n
131<\/td>\n6.44 set_partial_on_translation
6.45 set_pin_related_supply [deprecated] <\/td>\n<\/tr>\n
132<\/td>\n6.46 set_port_attributes <\/td>\n<\/tr>\n
136<\/td>\n6.47 set_power_switch [deprecated]
6.48 set_repeater <\/td>\n<\/tr>\n
139<\/td>\n6.49 set_retention <\/td>\n<\/tr>\n
143<\/td>\n6.50 set_retention_control [deprecated]
6.51 set_retention_elements <\/td>\n<\/tr>\n
144<\/td>\n6.52 set_scope <\/td>\n<\/tr>\n
145<\/td>\n6.53 set_simstate_behavior <\/td>\n<\/tr>\n
146<\/td>\n6.54 upf_version <\/td>\n<\/tr>\n
147<\/td>\n6.55 use_interface_cell <\/td>\n<\/tr>\n
150<\/td>\n7. Power management cell commands
7.1 Introduction <\/td>\n<\/tr>\n
151<\/td>\n7.2 define_always_on_cell <\/td>\n<\/tr>\n
152<\/td>\n7.3 define_diode_clamp <\/td>\n<\/tr>\n
153<\/td>\n7.4 define_isolation_cell <\/td>\n<\/tr>\n
156<\/td>\n7.5 define_level_shifter_cell <\/td>\n<\/tr>\n
160<\/td>\n7.6 define_power_switch_cell <\/td>\n<\/tr>\n
162<\/td>\n7.7 define_retention_cell <\/td>\n<\/tr>\n
165<\/td>\n8. UPF processing
8.1 Overview
8.2 Data requirements
8.3 Processing phases <\/td>\n<\/tr>\n
166<\/td>\n8.3.1 Phase 1\u2014read and resolve UPF specification
8.3.2 Phase 2\u2014build power intent model <\/td>\n<\/tr>\n
167<\/td>\n8.3.3 Phase 3\u2014recognize implemented power intent <\/td>\n<\/tr>\n
168<\/td>\n8.3.4 Phase 4\u2014apply power intent model to design
8.4 Error checking <\/td>\n<\/tr>\n
169<\/td>\n9. Simulation semantics
9.1 Supply network creation <\/td>\n<\/tr>\n
170<\/td>\n9.2 Supply network simulation
9.2.1 Supply network initialization <\/td>\n<\/tr>\n
171<\/td>\n9.2.2 Power-switch evaluation <\/td>\n<\/tr>\n
172<\/td>\n9.2.3 Supply network evaluation
9.3 Power state simulation
9.3.1 Power state control <\/td>\n<\/tr>\n
173<\/td>\n9.3.2 Power state determination <\/td>\n<\/tr>\n
174<\/td>\n9.4 Simstate simulation <\/td>\n<\/tr>\n
175<\/td>\n9.4.1 NORMAL
9.4.2 CORRUPT
9.4.3 CORRUPT_ON_ACTIVITY
9.4.4 CORRUPT_ON_CHANGE <\/td>\n<\/tr>\n
176<\/td>\n9.4.5 CORRUPT_STATE_ON_CHANGE
9.4.6 CORRUPT_STATE_ON_ACTIVITY
9.4.7 NOT_NORMAL
9.5 Transitioning from one simstate state to another
9.5.1 Any state transition to CORRUPT <\/td>\n<\/tr>\n
177<\/td>\n9.5.2 Any state transition to CORRUPT_ON_ACTIVITY
9.5.3 Any state transition to CORRUPT_ON_CHANGE
9.5.4 Any state transition to CORRUPT_STATE_ON_CHANGE
9.5.5 Any state transition to CORRUPT_STATE_ON_ACTIVITY
9.5.6 Any state transition to NORMAL
9.5.7 Any state transition to NOT_NORMAL
9.6 Simulation of retention <\/td>\n<\/tr>\n
178<\/td>\n9.6.1 Retention corruption summary <\/td>\n<\/tr>\n
179<\/td>\n9.6.2 Retention modeling for different retention styles <\/td>\n<\/tr>\n
183<\/td>\n9.7 Simulation of isolation
9.8 Simulation of level-shifting
9.9 Simulation of repeater <\/td>\n<\/tr>\n
184<\/td>\nAnnex A (informative) Bibliography
\n <\/td>\n<\/tr>\n
185<\/td>\nAnnex B (normative) HDL package UPF
\n
B.1 Supply net logic type values
B.2 Path names
B.3 VHDL UPF package <\/td>\n<\/tr>\n
190<\/td>\nB.4 SystemVerilog UPF package <\/td>\n<\/tr>\n
197<\/td>\nAnnex C (normative) Queries
\n <\/td>\n<\/tr>\n
198<\/td>\nC.1 query_upf <\/td>\n<\/tr>\n
200<\/td>\nC.2 query_associate_supply_set <\/td>\n<\/tr>\n
201<\/td>\nC.3 query_bind_checker <\/td>\n<\/tr>\n
202<\/td>\nC.4 query_cell_instances
C.5 query_cell_mapped <\/td>\n<\/tr>\n
203<\/td>\nC.6 query_composite_domain <\/td>\n<\/tr>\n
204<\/td>\nC.7 query_design_attributes <\/td>\n<\/tr>\n
205<\/td>\nC.8 query_hdl2upf_vct <\/td>\n<\/tr>\n
206<\/td>\nC.9 query_isolation <\/td>\n<\/tr>\n
207<\/td>\nC.10 query_isolation_control [deprecated] <\/td>\n<\/tr>\n
208<\/td>\nC.11 query_level_shifter <\/td>\n<\/tr>\n
209<\/td>\nC.12 query_map_isolation_cell [deprecated]
C.13 query_map_level_shifter_cell [deprecated] <\/td>\n<\/tr>\n
210<\/td>\nC.14 query_map_power_switch <\/td>\n<\/tr>\n
211<\/td>\nC.15 query_map_retention_cell <\/td>\n<\/tr>\n
212<\/td>\nC.16 query_name_format <\/td>\n<\/tr>\n
213<\/td>\nC.17 query_net_ports
C.18 query_partial_on_translation <\/td>\n<\/tr>\n
214<\/td>\nC.19 query_pin_related_supply [deprecated]
C.20 query_port_attributes <\/td>\n<\/tr>\n
215<\/td>\nC.21 query_port_direction
C.22 query_port_net <\/td>\n<\/tr>\n
216<\/td>\nC.23 query_port_state <\/td>\n<\/tr>\n
217<\/td>\nC.24 query_power_domain <\/td>\n<\/tr>\n
218<\/td>\nC.25 query_power_domain_element
C.26 query_power_state <\/td>\n<\/tr>\n
219<\/td>\nC.27 query_power_switch <\/td>\n<\/tr>\n
221<\/td>\nC.28 query_pst [legacy] <\/td>\n<\/tr>\n
222<\/td>\nC.29 query_pst_state [legacy] <\/td>\n<\/tr>\n
223<\/td>\nC.30 query_retention <\/td>\n<\/tr>\n
224<\/td>\nC.31 query_retention_control [deprecated]
C.32 query_retention_elements <\/td>\n<\/tr>\n
225<\/td>\nC.33 query_simstate_behavior <\/td>\n<\/tr>\n
227<\/td>\nC.34 query_state_transition <\/td>\n<\/tr>\n
228<\/td>\nC.35 query_supply_net <\/td>\n<\/tr>\n
229<\/td>\nC.36 query_supply_port <\/td>\n<\/tr>\n
230<\/td>\nC.37 query_supply_set <\/td>\n<\/tr>\n
231<\/td>\nC.38 query_upf2hdl_vct <\/td>\n<\/tr>\n
232<\/td>\nC.39 query_use_interface_cell <\/td>\n<\/tr>\n
234<\/td>\nAnnex D (informative) Replacing deprecated and legacy commands and options
\n
D.1 Deprecated and legacy constructs <\/td>\n<\/tr>\n
237<\/td>\nD.2 Recommendations for replacing deprecated and legacy constructs <\/td>\n<\/tr>\n
242<\/td>\nAnnex E (informative) Low-power design methodology
\n
E.1 Design, implementation, and verification flow for a soft IP <\/td>\n<\/tr>\n
244<\/td>\nE.2 RTL design stage <\/td>\n<\/tr>\n
254<\/td>\nE.3 Logic implementation <\/td>\n<\/tr>\n
258<\/td>\nE.4 Physical implementation <\/td>\n<\/tr>\n
262<\/td>\nE.5 SoC integration flow
E.6 How to create a configuration UPF <\/td>\n<\/tr>\n
267<\/td>\nAnnex F (normative) Value conversion tables
\n
F.1 VHDL_SL2UPF
F.2 UPF2VHDL_SL
F.3 VHDL_SL2UPF_GNDZERO <\/td>\n<\/tr>\n
268<\/td>\nF.4 UPF_GNDZERO2VHDL_SL
F.5 SV_LOGIC2UPF
F.6 UPF2SV_LOGIC
F.7 SV_LOGIC2UPF_GNDZERO
F.8 UPF_GNDZERO2SV_LOGIC <\/td>\n<\/tr>\n
269<\/td>\nF.9 VHDL_TIED_HI
F.10 SV_TIED_HI
F.11 VHDL_TIED_LO
F.12 SV_TIED_LO <\/td>\n<\/tr>\n
270<\/td>\nAnnex G (normative) Supporting hard IP
\n
G.1 Attributing feedthrough ports of hard IP <\/td>\n<\/tr>\n
271<\/td>\nG.2 Attributing unconnected ports of hard IP <\/td>\n<\/tr>\n
273<\/td>\nAnnex H (normative) UPF power-management commands semantics and Liberty mappings
\n
H.1 Introduction
H.2 define_always_on_cell <\/td>\n<\/tr>\n
275<\/td>\nH.3 define_diode_clamp <\/td>\n<\/tr>\n
276<\/td>\nH.4 define_isolation_cell <\/td>\n<\/tr>\n
279<\/td>\nH.5 define_level_shifter_cell <\/td>\n<\/tr>\n
282<\/td>\nH.6 define_power_switch_cell <\/td>\n<\/tr>\n
284<\/td>\nH.7 define_retention_cell <\/td>\n<\/tr>\n
288<\/td>\nAnnex I (informative) Power-management cell modeling examples
\n
I.1 Modeling always-on cells <\/td>\n<\/tr>\n
291<\/td>\nI.2 Modeling cells with internal diodes <\/td>\n<\/tr>\n
292<\/td>\nI.3 Modeling isolation cells <\/td>\n<\/tr>\n
300<\/td>\nI.4 Modeling level-shifters <\/td>\n<\/tr>\n
308<\/td>\nI.5 Modeling power-switch cells <\/td>\n<\/tr>\n
312<\/td>\nI.6 Modeling state retention cells <\/td>\n<\/tr>\n
318<\/td>\nAnnex J (normative) Switching Activity Interchange Format
\n <\/td>\n<\/tr>\n
319<\/td>\nJ.1 Syntactic conventions <\/td>\n<\/tr>\n
320<\/td>\nJ.2 Lexical conventions <\/td>\n<\/tr>\n
322<\/td>\nJ.3 Backward SAIF file <\/td>\n<\/tr>\n
337<\/td>\nJ.4 Library forward SAIF file <\/td>\n<\/tr>\n
344<\/td>\nJ.5 RTL forward SAIF file <\/td>\n<\/tr>\n
348<\/td>\nAnnex K (informative) IEEE List of Participants <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE\/IEC International Standard – Design and Verification of Low-Power Integrated Circuits<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n2015<\/td>\n351<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":136586,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-136582","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/136582","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/136586"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=136582"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=136582"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=136582"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}