{"id":147512,"date":"2024-10-19T08:39:49","date_gmt":"2024-10-19T08:39:49","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-62659-2015\/"},"modified":"2024-10-25T00:55:47","modified_gmt":"2024-10-25T00:55:47","slug":"ieee-62659-2015","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-62659-2015\/","title":{"rendered":"IEEE 62659 2015"},"content":{"rendered":"
New IEEE Standard – Active.<\/p>\n
PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
---|---|---|---|---|---|---|---|
1<\/td>\n | IEC\/IEEE 62659:2015 Front cover <\/td>\n<\/tr>\n | ||||||
3<\/td>\n | Title page <\/td>\n<\/tr>\n | ||||||
4<\/td>\n | CONTENTS <\/td>\n<\/tr>\n | ||||||
5<\/td>\n | FOREWORD IEEE Notice to users <\/td>\n<\/tr>\n | ||||||
7<\/td>\n | INTRODUCTION <\/td>\n<\/tr>\n | ||||||
8<\/td>\n | 1 Scope 2 Normative references 3 Terms and definitions <\/td>\n<\/tr>\n | ||||||
10<\/td>\n | 4 Abbreviations <\/td>\n<\/tr>\n | ||||||
11<\/td>\n | 5 Nanomaterials incorporation into electronics fabrication 5.1 General Figures Figure 1 \u2013 Relationship between bottom-up, top-down and hybrid devicefabrication processes for nanoelectronics over length scales Tables Table 1 \u2013 Bottom-up process for nanoelectronics Table 2 \u2013 Top-down process for nanoelectronics <\/td>\n<\/tr>\n | ||||||
12<\/td>\n | 5.2 Raw materials acquisition Table 3 \u2013 Comparison of CMOS processes with exemplary CNT electronics process <\/td>\n<\/tr>\n | ||||||
13<\/td>\n | 5.3 Materials processing 5.4 Design 5.5 Fabrication 5.6 Test 5.7 End-use 6 Safety and environmental issues <\/td>\n<\/tr>\n | ||||||
14<\/td>\n | Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" IEC\/IEEE International Standard – Nanomanufacturing — Large scale manufacturing for nanoelectronics<\/b><\/p>\n |