{"id":154557,"date":"2024-10-19T09:11:55","date_gmt":"2024-10-19T09:11:55","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1149-6-2016\/"},"modified":"2024-10-25T01:27:27","modified_gmt":"2024-10-25T01:27:27","slug":"ieee-1149-6-2016","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1149-6-2016\/","title":{"rendered":"IEEE 1149.6 2016"},"content":{"rendered":"
Revision Standard – Active. This standard augments IEEE Std 1149.1 to improve the ability for testing differential and\/or ac-coupled interconnections between integrated circuits on circuit boards and systems.<\/p>\n
PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
---|---|---|---|---|---|---|---|
1<\/td>\n | IEEE Std 1149.6\u2122-2015 Front Cover <\/td>\n<\/tr>\n | ||||||
3<\/td>\n | Title page <\/td>\n<\/tr>\n | ||||||
5<\/td>\n | Important Notices and Disclaimers Concerning IEEE Standards Documents <\/td>\n<\/tr>\n | ||||||
8<\/td>\n | Participants <\/td>\n<\/tr>\n | ||||||
9<\/td>\n | Introduction <\/td>\n<\/tr>\n | ||||||
12<\/td>\n | Contents <\/td>\n<\/tr>\n | ||||||
15<\/td>\n | Important Notice 1. Overview 1.1 Scope 1.2 Purpose <\/td>\n<\/tr>\n | ||||||
16<\/td>\n | 1.3 Organization of the standard <\/td>\n<\/tr>\n | ||||||
17<\/td>\n | 1.4 Context 1.5 Objectives <\/td>\n<\/tr>\n | ||||||
18<\/td>\n | 2. Normative references 3. Definitions and acronyms 3.1 Definitions <\/td>\n<\/tr>\n | ||||||
24<\/td>\n | 3.2 Acronyms <\/td>\n<\/tr>\n | ||||||
25<\/td>\n | 4. Technology <\/td>\n<\/tr>\n | ||||||
26<\/td>\n | 4.1 Signal pin types 4.2 Signal coupling and coupling combinations <\/td>\n<\/tr>\n | ||||||
32<\/td>\n | 4.3 The effects of defects <\/td>\n<\/tr>\n | ||||||
34<\/td>\n | 4.4 Defects targeted by the standard <\/td>\n<\/tr>\n | ||||||
35<\/td>\n | 4.5 Differential termination and testability <\/td>\n<\/tr>\n | ||||||
38<\/td>\n | 4.6 Test signal implementation <\/td>\n<\/tr>\n | ||||||
42<\/td>\n | 4.7 Test receiver support for ac testing instructions <\/td>\n<\/tr>\n | ||||||
46<\/td>\n | 4.8 Test receiver support for the (DC) EXTEST instruction <\/td>\n<\/tr>\n | ||||||
48<\/td>\n | 4.9 A general test receiver for dc and ac testing instructions <\/td>\n<\/tr>\n | ||||||
50<\/td>\n | 4.10 Boundary-scan capture data versus configuration <\/td>\n<\/tr>\n | ||||||
52<\/td>\n | 4.11 Noise sources and sensitivities <\/td>\n<\/tr>\n | ||||||
56<\/td>\n | 5. Instructions 5.1 IEEE Std 1149.1 instructions 5.2 AC testing instructions <\/td>\n<\/tr>\n | ||||||
59<\/td>\n | 5.3 The EXTEST_PULSE instruction <\/td>\n<\/tr>\n | ||||||
61<\/td>\n | 5.4 The EXTEST_TRAIN instruction <\/td>\n<\/tr>\n | ||||||
64<\/td>\n | 5.5 ac test signal generation 6. Pin implementation specifications 6.1 Pin identification <\/td>\n<\/tr>\n | ||||||
65<\/td>\n | 6.2 Input test receivers <\/td>\n<\/tr>\n | ||||||
97<\/td>\n | 6.3 Output drivers <\/td>\n<\/tr>\n | ||||||
100<\/td>\n | 6.4 Bidirectional pins <\/td>\n<\/tr>\n | ||||||
104<\/td>\n | 6.5 AC\/DC selection cells <\/td>\n<\/tr>\n | ||||||
106<\/td>\n | 7. Conformance and documentation requirements 7.1 Conformance <\/td>\n<\/tr>\n | ||||||
107<\/td>\n | 7.2 Documentation <\/td>\n<\/tr>\n | ||||||
109<\/td>\n | 7.3 BSDL package for Advanced I\/O description (STD_1149_6_2015) <\/td>\n<\/tr>\n | ||||||
112<\/td>\n | 7.4 BSDL extension structure <\/td>\n<\/tr>\n | ||||||
115<\/td>\n | 7.5 BSDL attribute definitions <\/td>\n<\/tr>\n | ||||||
137<\/td>\n | 7.6 Example BSDL <\/td>\n<\/tr>\n | ||||||
156<\/td>\n | 7.7 PDL procedures for programmable ac pins <\/td>\n<\/tr>\n | ||||||
161<\/td>\n | 7.8 Example PDL procedures for programmable ac pins <\/td>\n<\/tr>\n | ||||||
187<\/td>\n | Annex A (informative) Applications and tools A.1 Chip compliance checking and BSDL and PDL verification <\/td>\n<\/tr>\n | ||||||
193<\/td>\n | A.2 Functional verification A.3 Board interconnection testing <\/td>\n<\/tr>\n | ||||||
203<\/td>\n | Annex B (informative) Noise rejection in edge-detecting mode B.1 Noise rejection by bandwidth limitation <\/td>\n<\/tr>\n | ||||||
205<\/td>\n | B.2 Noise rejection by slew rate limitation <\/td>\n<\/tr>\n | ||||||
206<\/td>\n | Annex C (informative) Advanced I\/O boundary-scan register cells C.1 AC\/DC selection cell AC_SelX C.2 AC\/DC selection cell AC_SelU <\/td>\n<\/tr>\n | ||||||
207<\/td>\n | C.3 Output data cell AC_1 (supports INTEST) <\/td>\n<\/tr>\n | ||||||
208<\/td>\n | C.4 Output data cell AC_2 C.5 Bidirectional output cell AC_7 (supports INTEST) <\/td>\n<\/tr>\n | ||||||
209<\/td>\n | C.6 Bidirectional output cell AC_8 <\/td>\n<\/tr>\n | ||||||
210<\/td>\n | C.7 Self-monitoring output cell AC_9 (supports INTEST) <\/td>\n<\/tr>\n | ||||||
211<\/td>\n | C.8 Self-monitoring output cell AC_10 C.9 AC_40 and AC_41 cells <\/td>\n<\/tr>\n | ||||||
212<\/td>\n | C.10 AC cell mode controls <\/td>\n<\/tr>\n | ||||||
213<\/td>\n | Annex D (informative) Test receiver design examples D.1 LVDS with normal board coupling <\/td>\n<\/tr>\n | ||||||
219<\/td>\n | D.2 LVDS with alternative board coupling <\/td>\n<\/tr>\n | ||||||
220<\/td>\n | D.3 LVDS with on-chip coupling <\/td>\n<\/tr>\n | ||||||
222<\/td>\n | D.4 LVPECL (low-voltage pseudo emitter-coupled logic) <\/td>\n<\/tr>\n | ||||||
224<\/td>\n | D.5 LVPECL with guaranteed on-board ac coupling <\/td>\n<\/tr>\n | ||||||
225<\/td>\n | D.6 LVPECL with on-chip coupling <\/td>\n<\/tr>\n | ||||||
227<\/td>\n | Annex E (informative) A proposed \u201cINITIALIZE\u201d instruction <\/td>\n<\/tr>\n | ||||||
228<\/td>\n | Annex F (informative) Bibliography <\/td>\n<\/tr>\n | ||||||
230<\/td>\n | Back Cover <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" IEEE Approved Draft Standard for Boundary-Scan Testing of Advanced Digital Networks<\/b><\/p>\n |