{"id":154687,"date":"2024-10-19T09:12:24","date_gmt":"2024-10-19T09:12:24","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1801-2016\/"},"modified":"2024-10-25T01:27:53","modified_gmt":"2024-10-25T01:27:53","slug":"ieee-1801-2016","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1801-2016\/","title":{"rendered":"IEEE 1801 2016"},"content":{"rendered":"
Revision Standard – Active. A method is provided for specifying power intent for an electronic design, for use in verification of the structure and behavior of the design in the context of a given power management architecture, and for driving implementation of that power-management architecture. The method supports incremental refinement of power-intent specifications required for IP-based design flows.<\/p>\n
PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
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1<\/td>\n | IEEE Std 1801-2015 Front Cover <\/td>\n<\/tr>\n | ||||||
2<\/td>\n | Title page <\/td>\n<\/tr>\n | ||||||
4<\/td>\n | Important Notices and Disclaimers Concerning IEEE Standards Documents <\/td>\n<\/tr>\n | ||||||
7<\/td>\n | Participants <\/td>\n<\/tr>\n | ||||||
8<\/td>\n | Introduction <\/td>\n<\/tr>\n | ||||||
10<\/td>\n | Contents <\/td>\n<\/tr>\n | ||||||
14<\/td>\n | IMPORTANT NOTICE 1. Overview 1.1 Scope 1.2 Purpose 1.3 Key characteristics of the Unified Power Format <\/td>\n<\/tr>\n | ||||||
16<\/td>\n | 1.4 Contents of this standard <\/td>\n<\/tr>\n | ||||||
17<\/td>\n | 2. Normative references 3. Definitions, acronyms, and abbreviations 3.1 Definitions <\/td>\n<\/tr>\n | ||||||
23<\/td>\n | 3.2 Acronyms and abbreviations <\/td>\n<\/tr>\n | ||||||
24<\/td>\n | 4. Concepts 4.1 Introduction 4.2 Design structure <\/td>\n<\/tr>\n | ||||||
25<\/td>\n | 4.3 Design representation <\/td>\n<\/tr>\n | ||||||
28<\/td>\n | 4.4 Power architecture <\/td>\n<\/tr>\n | ||||||
31<\/td>\n | 4.5 Power distribution <\/td>\n<\/tr>\n | ||||||
39<\/td>\n | 4.6 Power management <\/td>\n<\/tr>\n | ||||||
44<\/td>\n | 4.7 Supply states and power states <\/td>\n<\/tr>\n | ||||||
51<\/td>\n | 4.8 Simstates <\/td>\n<\/tr>\n | ||||||
52<\/td>\n | 4.9 Power intent specification <\/td>\n<\/tr>\n | ||||||
58<\/td>\n | 5. Language basics 5.1 UPF is Tcl 5.2 Conventions used <\/td>\n<\/tr>\n | ||||||
60<\/td>\n | 5.3 Lexical elements <\/td>\n<\/tr>\n | ||||||
64<\/td>\n | 5.4 Boolean expressions <\/td>\n<\/tr>\n | ||||||
66<\/td>\n | 5.5 Object declaration 5.6 Attributes of objects <\/td>\n<\/tr>\n | ||||||
71<\/td>\n | 5.7 Precedence <\/td>\n<\/tr>\n | ||||||
73<\/td>\n | 5.8 Generic UPF command semantics 5.9 effective_element_list semantics <\/td>\n<\/tr>\n | ||||||
76<\/td>\n | 5.10 Command refinement <\/td>\n<\/tr>\n | ||||||
78<\/td>\n | 5.11 Error handling 5.12 Units 5.13 SystemC language basic 6. Power intent commands 6.1 Introduction 6.2 Categories <\/td>\n<\/tr>\n | ||||||
79<\/td>\n | 6.3 add_parameter <\/td>\n<\/tr>\n | ||||||
80<\/td>\n | 6.4 add_port_state (legacy) <\/td>\n<\/tr>\n | ||||||
81<\/td>\n | 6.5 add_power_state <\/td>\n<\/tr>\n | ||||||
87<\/td>\n | 6.6 add_pst_state (legacy) <\/td>\n<\/tr>\n | ||||||
89<\/td>\n | 6.7 add_state_transition <\/td>\n<\/tr>\n | ||||||
91<\/td>\n | 6.8 add_supply_state 6.9 apply_power_model <\/td>\n<\/tr>\n | ||||||
93<\/td>\n | 6.10 associate_supply_set <\/td>\n<\/tr>\n | ||||||
94<\/td>\n | 6.11 begin_power_model <\/td>\n<\/tr>\n | ||||||
96<\/td>\n | 6.12 bind_checker <\/td>\n<\/tr>\n | ||||||
97<\/td>\n | 6.13 connect_logic_net <\/td>\n<\/tr>\n | ||||||
99<\/td>\n | 6.14 connect_supply_net <\/td>\n<\/tr>\n | ||||||
101<\/td>\n | 6.15 connect_supply_set <\/td>\n<\/tr>\n | ||||||
102<\/td>\n | 6.16 create_composite_domain <\/td>\n<\/tr>\n | ||||||
104<\/td>\n | 6.17 create_hdl2upf_vct <\/td>\n<\/tr>\n | ||||||
105<\/td>\n | 6.18 create_logic_net <\/td>\n<\/tr>\n | ||||||
106<\/td>\n | 6.19 create_logic_port <\/td>\n<\/tr>\n | ||||||
107<\/td>\n | 6.20 create_power_domain <\/td>\n<\/tr>\n | ||||||
110<\/td>\n | 6.21 create_power_state_group <\/td>\n<\/tr>\n | ||||||
112<\/td>\n | 6.22 create_power_switch <\/td>\n<\/tr>\n | ||||||
119<\/td>\n | 6.23 create_pst (legacy) <\/td>\n<\/tr>\n | ||||||
120<\/td>\n | 6.24 create_supply_net <\/td>\n<\/tr>\n | ||||||
124<\/td>\n | 6.25 create_supply_port <\/td>\n<\/tr>\n | ||||||
125<\/td>\n | 6.26 create_supply_set <\/td>\n<\/tr>\n | ||||||
126<\/td>\n | 6.27 create_upf2hdl_vct <\/td>\n<\/tr>\n | ||||||
127<\/td>\n | 6.28 describe_state_transition (deprecated) 6.29 end_power_model <\/td>\n<\/tr>\n | ||||||
128<\/td>\n | 6.30 find_objects <\/td>\n<\/tr>\n | ||||||
132<\/td>\n | 6.31 load_simstate_behavior <\/td>\n<\/tr>\n | ||||||
133<\/td>\n | 6.32 load_upf <\/td>\n<\/tr>\n | ||||||
134<\/td>\n | 6.33 load_upf_protected (deprecated) 6.34 map_power_switch <\/td>\n<\/tr>\n | ||||||
135<\/td>\n | 6.35 map_repeater_cell <\/td>\n<\/tr>\n | ||||||
136<\/td>\n | 6.36 map_retention_cell <\/td>\n<\/tr>\n | ||||||
140<\/td>\n | 6.37 name_format <\/td>\n<\/tr>\n | ||||||
141<\/td>\n | 6.38 save_upf <\/td>\n<\/tr>\n | ||||||
142<\/td>\n | 6.39 set_correlated <\/td>\n<\/tr>\n | ||||||
143<\/td>\n | 6.40 set_design_attributes <\/td>\n<\/tr>\n | ||||||
144<\/td>\n | 6.41 set_design_top <\/td>\n<\/tr>\n | ||||||
145<\/td>\n | 6.42 set_domain_supply_net (legacy) <\/td>\n<\/tr>\n | ||||||
146<\/td>\n | 6.43 set_equivalent <\/td>\n<\/tr>\n | ||||||
148<\/td>\n | 6.44 set_isolation <\/td>\n<\/tr>\n | ||||||
155<\/td>\n | 6.45 set_level_shifter <\/td>\n<\/tr>\n | ||||||
161<\/td>\n | 6.46 set_partial_on_translation <\/td>\n<\/tr>\n | ||||||
162<\/td>\n | 6.47 set_port_attributes <\/td>\n<\/tr>\n | ||||||
168<\/td>\n | 6.48 set_repeater <\/td>\n<\/tr>\n | ||||||
171<\/td>\n | 6.49 set_retention <\/td>\n<\/tr>\n | ||||||
175<\/td>\n | 6.50 set_retention_elements <\/td>\n<\/tr>\n | ||||||
176<\/td>\n | 6.51 set_scope <\/td>\n<\/tr>\n | ||||||
177<\/td>\n | 6.52 set_simstate_behavior <\/td>\n<\/tr>\n | ||||||
178<\/td>\n | 6.53 set_variation <\/td>\n<\/tr>\n | ||||||
179<\/td>\n | 6.54 upf_version <\/td>\n<\/tr>\n | ||||||
180<\/td>\n | 6.55 use_interface_cell <\/td>\n<\/tr>\n | ||||||
182<\/td>\n | 7. Power-management cell definition commands 7.1 Introduction <\/td>\n<\/tr>\n | ||||||
183<\/td>\n | 7.2 define_always_on_cell <\/td>\n<\/tr>\n | ||||||
184<\/td>\n | 7.3 define_diode_clamp <\/td>\n<\/tr>\n | ||||||
185<\/td>\n | 7.4 define_isolation_cell <\/td>\n<\/tr>\n | ||||||
188<\/td>\n | 7.5 define_level_shifter_cell <\/td>\n<\/tr>\n | ||||||
192<\/td>\n | 7.6 define_power_switch_cell <\/td>\n<\/tr>\n | ||||||
194<\/td>\n | 7.7 define_retention_cell <\/td>\n<\/tr>\n | ||||||
196<\/td>\n | 8. UPF processing 8.1 Overview <\/td>\n<\/tr>\n | ||||||
197<\/td>\n | 8.2 Data requirements 8.3 Processing phases <\/td>\n<\/tr>\n | ||||||
201<\/td>\n | 8.4 Error checking 9. Simulation semantics 9.1 Supply network creation <\/td>\n<\/tr>\n | ||||||
203<\/td>\n | 9.2 Supply network simulation <\/td>\n<\/tr>\n | ||||||
204<\/td>\n | 9.3 Power state simulation <\/td>\n<\/tr>\n | ||||||
207<\/td>\n | 9.4 Power state transition detection 9.5 Simstate simulation <\/td>\n<\/tr>\n | ||||||
210<\/td>\n | 9.6 Transitioning from one simstate state to another <\/td>\n<\/tr>\n | ||||||
211<\/td>\n | 9.7 Simulation of retention <\/td>\n<\/tr>\n | ||||||
217<\/td>\n | 9.8 Simulation of isolation <\/td>\n<\/tr>\n | ||||||
218<\/td>\n | 9.9 Simulation of level-shifting 9.10 Simulation of repeaters 10. UPF information model 10.1 Overview <\/td>\n<\/tr>\n | ||||||
219<\/td>\n | 10.2 Components of UPF information model <\/td>\n<\/tr>\n | ||||||
220<\/td>\n | 10.3 Identifiers in information model (IDs) <\/td>\n<\/tr>\n | ||||||
223<\/td>\n | 10.4 Classification of objects <\/td>\n<\/tr>\n | ||||||
230<\/td>\n | 10.5 Example of design hierarchy <\/td>\n<\/tr>\n | ||||||
231<\/td>\n | 10.6 Object definitions <\/td>\n<\/tr>\n | ||||||
285<\/td>\n | 11. Information model application programmable interface (API) 11.1 Tcl interface <\/td>\n<\/tr>\n | ||||||
295<\/td>\n | 11.2 HDL interface <\/td>\n<\/tr>\n | ||||||
357<\/td>\n | Annex A (informative) Bibliography <\/td>\n<\/tr>\n | ||||||
358<\/td>\n | Annex B (normative) Value conversion tables <\/td>\n<\/tr>\n | ||||||
361<\/td>\n | Annex C (informative) UPF query examples <\/td>\n<\/tr>\n | ||||||
365<\/td>\n | Annex D (informative) Replacing deprecated and legacy commands and options <\/td>\n<\/tr>\n | ||||||
368<\/td>\n | Annex E (informative) Low-power design methodology <\/td>\n<\/tr>\n | ||||||
395<\/td>\n | Annex F (informative) Power-management cell definitions in UPF and Liberty <\/td>\n<\/tr>\n | ||||||
410<\/td>\n | Annex G (informative) Power-management cell modeling examples <\/td>\n<\/tr>\n | ||||||
474<\/td>\n | Annex H (informative) IP power modeling for system-level design <\/td>\n<\/tr>\n | ||||||
481<\/td>\n | Annex I (normative) Switching Activity Interchange Format <\/td>\n<\/tr>\n | ||||||
515<\/td>\n | Back Cover <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" IEEE Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems<\/b><\/p>\n |