{"id":194733,"date":"2024-10-19T12:21:24","date_gmt":"2024-10-19T12:21:24","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1800-2-2017\/"},"modified":"2024-10-25T04:52:29","modified_gmt":"2024-10-25T04:52:29","slug":"ieee-1800-2-2017","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1800-2-2017\/","title":{"rendered":"IEEE 1800.2 2017"},"content":{"rendered":"

New IEEE Standard – Active. The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library. (The PDF of this standard is available at no cost compliments of the GET IEEE program https:\/\/ieeexplore.ieee.org\/browse\/standards\/get-program\/page)<\/p>\n

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
1<\/td>\nIEEE Std 1800.2\u2122-2017 Front cover <\/td>\n<\/tr>\n
2<\/td>\nTitle page <\/td>\n<\/tr>\n
4<\/td>\nImportant Notices and Disclaimers Concerning IEEE Standards Documents <\/td>\n<\/tr>\n
7<\/td>\nParticipants <\/td>\n<\/tr>\n
8<\/td>\nIntroduction <\/td>\n<\/tr>\n
10<\/td>\nContents <\/td>\n<\/tr>\n
14<\/td>\n1. Overview
1.1 Scope
1.2 Purpose
1.3 Conventions used
1.3.1 Visual cues (meta-syntax) <\/td>\n<\/tr>\n
15<\/td>\n1.3.2 Return values
1.3.3 Inheritance
1.3.4 Operation order on equivalent data objects
1.3.5 uvm_pkg <\/td>\n<\/tr>\n
16<\/td>\n1.3.6 Random stability <\/td>\n<\/tr>\n
17<\/td>\n2. Normative references
3. Definitions, acronyms, and abbreviations
3.1 Definitions <\/td>\n<\/tr>\n
18<\/td>\n3.2 Acronyms and abbreviations <\/td>\n<\/tr>\n
19<\/td>\n4. UVM class reference <\/td>\n<\/tr>\n
21<\/td>\n5. Base classes
5.1 Overview
5.2 uvm_void
5.3 uvm_object
5.3.1 Class declaration
5.3.2 Common methods <\/td>\n<\/tr>\n
22<\/td>\n5.3.3 Seeding
5.3.4 Identification <\/td>\n<\/tr>\n
24<\/td>\n5.3.5 Creation
5.3.6 Printing <\/td>\n<\/tr>\n
25<\/td>\n5.3.7 Recording
5.3.8 Copying <\/td>\n<\/tr>\n
26<\/td>\n5.3.9 Comparing <\/td>\n<\/tr>\n
27<\/td>\n5.3.10 Packing <\/td>\n<\/tr>\n
28<\/td>\n5.3.11 Unpacking <\/td>\n<\/tr>\n
29<\/td>\n5.3.12 Configuration
5.3.13 Field operations <\/td>\n<\/tr>\n
32<\/td>\n5.3.14 Active policy
5.4 uvm_transaction <\/td>\n<\/tr>\n
33<\/td>\n5.4.1 Class declaration
5.4.2 Methods <\/td>\n<\/tr>\n
37<\/td>\n5.5 uvm_port_base #(IF)
5.5.1 Class declaration <\/td>\n<\/tr>\n
38<\/td>\n5.5.2 Methods <\/td>\n<\/tr>\n
41<\/td>\n5.6 uvm_time
5.6.1 Class declaration
5.6.2 Common methods <\/td>\n<\/tr>\n
44<\/td>\n6. Reporting classes
6.1 Overview
6.2 uvm_report_message
6.2.1 Class declaration
6.2.2 Common methods <\/td>\n<\/tr>\n
45<\/td>\n6.2.3 Infrastructure references
6.2.4 Message fields <\/td>\n<\/tr>\n
47<\/td>\n6.3 uvm_report_object <\/td>\n<\/tr>\n
48<\/td>\n6.3.1 Class declaration
6.3.2 Common methods
6.3.3 Reporting <\/td>\n<\/tr>\n
50<\/td>\n6.3.4 Verbosity configuration <\/td>\n<\/tr>\n
51<\/td>\n6.3.5 Action configuration <\/td>\n<\/tr>\n
52<\/td>\n6.3.6 File configuration
6.3.7 Override configuration <\/td>\n<\/tr>\n
53<\/td>\n6.3.8 Report handler configuration
6.4 uvm_report_handler
6.4.1 Class declaration
6.4.2 Common methods <\/td>\n<\/tr>\n
54<\/td>\n6.4.3 Verbosity configuration
6.4.4 Action configuration <\/td>\n<\/tr>\n
55<\/td>\n6.4.5 File configuration <\/td>\n<\/tr>\n
56<\/td>\n6.4.6 Override configuration
6.4.7 Message processing
6.5 Report server
6.5.1 uvm_report_server <\/td>\n<\/tr>\n
60<\/td>\n6.5.2 uvm_default_report_server
6.6 uvm_report_catcher
6.6.1 Class declaration
6.6.2 Common methods <\/td>\n<\/tr>\n
61<\/td>\n6.6.3 Current message state <\/td>\n<\/tr>\n
62<\/td>\n6.6.4 Change message state <\/td>\n<\/tr>\n
63<\/td>\n6.6.5 Callback interface
6.6.6 Reporting <\/td>\n<\/tr>\n
66<\/td>\n7. Recording classes
7.1 uvm_tr_database
7.1.1 Class declaration
7.1.2 Common methods
7.1.3 Database API <\/td>\n<\/tr>\n
67<\/td>\n7.1.4 Stream API
7.1.5 Link API <\/td>\n<\/tr>\n
68<\/td>\n7.1.6 Implementation agnostic API
7.2 uvm_tr_stream
7.2.1 Class declaration
7.2.2 Common methods <\/td>\n<\/tr>\n
69<\/td>\n7.2.3 Introspection API
7.2.4 Stream API <\/td>\n<\/tr>\n
70<\/td>\n7.2.5 Transaction recorder API <\/td>\n<\/tr>\n
71<\/td>\n7.2.6 Handles
7.2.7 Implementation agnostic API <\/td>\n<\/tr>\n
72<\/td>\n7.3 UVM links
7.3.1 uvm_link_base <\/td>\n<\/tr>\n
74<\/td>\n7.3.2 uvm_parent_child_link <\/td>\n<\/tr>\n
75<\/td>\n7.3.3 uvm_cause_effect_link <\/td>\n<\/tr>\n
76<\/td>\n7.3.4 uvm_related_link <\/td>\n<\/tr>\n
77<\/td>\n8. Factory classes
8.1 Overview
8.2 Factory component and object wrappers
8.2.1 Introduction
8.2.2 type_id <\/td>\n<\/tr>\n
78<\/td>\n8.2.3 uvm_component_registry #(T,Tname) <\/td>\n<\/tr>\n
79<\/td>\n8.2.4 uvm_object_registry #(T,Tname) <\/td>\n<\/tr>\n
81<\/td>\n8.2.5 Abstract registries <\/td>\n<\/tr>\n
83<\/td>\n8.3 UVM factory
8.3.1 uvm_factory <\/td>\n<\/tr>\n
88<\/td>\n8.3.2 uvm_object_wrapper <\/td>\n<\/tr>\n
89<\/td>\n8.3.3 uvm_default_factory <\/td>\n<\/tr>\n
90<\/td>\n9. Phasing
9.1 Overview
9.2 Implementation
9.2.1 Class hierarchy
9.2.2 Phasing related classes
9.2.3 Common and run-time phases
9.3 Phasing definition classes
9.3.1 uvm_phase <\/td>\n<\/tr>\n
98<\/td>\n9.3.2 uvm_phase_state_change <\/td>\n<\/tr>\n
99<\/td>\n9.3.3 uvm_phase_cb
9.4 uvm_domain <\/td>\n<\/tr>\n
100<\/td>\n9.4.1 Class declaration
9.4.2 Methods
9.5 uvm_bottomup_phase
9.5.1 Class declaration <\/td>\n<\/tr>\n
101<\/td>\n9.5.2 Methods
9.6 uvm_task_phase <\/td>\n<\/tr>\n
102<\/td>\n9.6.1 Class declaration
9.6.2 Methods
9.7 uvm_topdown_phase
9.7.1 Class declaration <\/td>\n<\/tr>\n
103<\/td>\n9.7.2 Methods
9.8 Predefined phases <\/td>\n<\/tr>\n
104<\/td>\n9.8.1 Common phases <\/td>\n<\/tr>\n
105<\/td>\n9.8.2 UVM run-time phases <\/td>\n<\/tr>\n
108<\/td>\n10. Synchronization classes
10.1 Event classes
10.1.1 uvm_event_base <\/td>\n<\/tr>\n
110<\/td>\n10.1.2 uvm_event#(T) <\/td>\n<\/tr>\n
111<\/td>\n10.2 uvm_event_callback
10.2.1 Class declaration
10.2.2 Methods <\/td>\n<\/tr>\n
112<\/td>\n10.3 uvm_barrier
10.3.1 Class declaration
10.3.2 Methods <\/td>\n<\/tr>\n
114<\/td>\n10.4 Pool classes
10.4.1 uvm_event_pool <\/td>\n<\/tr>\n
115<\/td>\n10.4.2 uvm_barrier_pool
10.5 Objection mechanism
10.5.1 uvm_objection <\/td>\n<\/tr>\n
119<\/td>\n10.5.2 uvm_objection_callback <\/td>\n<\/tr>\n
120<\/td>\n10.6 uvm_heartbeat <\/td>\n<\/tr>\n
121<\/td>\n10.6.1 Class declaration
10.6.2 Methods <\/td>\n<\/tr>\n
122<\/td>\n10.7 Callbacks classes
10.7.1 uvm_callback <\/td>\n<\/tr>\n
123<\/td>\n10.7.2 uvm_callbacks #(T,CB) <\/td>\n<\/tr>\n
127<\/td>\n11. Container classes
11.1 Overview
11.2 uvm_pool #(KEY,T)
11.2.1 Class declaration
11.2.2 Methods <\/td>\n<\/tr>\n
129<\/td>\n11.3 uvm_queue #(T)
11.3.1 Class declaration
11.3.2 Methods <\/td>\n<\/tr>\n
132<\/td>\n12. UVM TLM interfaces
12.1 Overview
12.2 UVM TLM 1
12.2.1 General <\/td>\n<\/tr>\n
133<\/td>\n12.2.2 Unidirectional interfaces and ports
12.2.3 Bidirectional interfaces and ports <\/td>\n<\/tr>\n
134<\/td>\n12.2.4 uvm_tlm_if_base #(T1,T2) <\/td>\n<\/tr>\n
137<\/td>\n12.2.5 Port classes <\/td>\n<\/tr>\n
138<\/td>\n12.2.6 Export classes <\/td>\n<\/tr>\n
140<\/td>\n12.2.7 Implementation (imp) classes <\/td>\n<\/tr>\n
142<\/td>\n12.2.8 FIFO classes <\/td>\n<\/tr>\n
145<\/td>\n12.2.9 Channel classes <\/td>\n<\/tr>\n
148<\/td>\n12.2.10 Analysis ports <\/td>\n<\/tr>\n
149<\/td>\n12.3 UVM TLM 2
12.3.1 General
12.3.2 uvm_tlm_if: transport interfaces <\/td>\n<\/tr>\n
151<\/td>\n12.3.3 Enumerations
12.3.4 Generic payload and extensions <\/td>\n<\/tr>\n
162<\/td>\n12.3.5 Sockets <\/td>\n<\/tr>\n
165<\/td>\n12.3.6 Port classes <\/td>\n<\/tr>\n
166<\/td>\n12.3.7 Export classes <\/td>\n<\/tr>\n
167<\/td>\n12.3.8 Implementation (imp) classes imps <\/td>\n<\/tr>\n
168<\/td>\n12.3.9 uvm_tlm_time <\/td>\n<\/tr>\n
169<\/td>\n13. Predefined component classes
13.1 uvm_component
13.1.1 Class declaration
13.1.2 Common methods <\/td>\n<\/tr>\n
170<\/td>\n13.1.3 Hierarchy interface <\/td>\n<\/tr>\n
171<\/td>\n13.1.4 Phasing interface <\/td>\n<\/tr>\n
177<\/td>\n13.1.5 Configuration interface <\/td>\n<\/tr>\n
178<\/td>\n13.1.6 Recording interface <\/td>\n<\/tr>\n
182<\/td>\n13.1.7 Other interfaces
13.2 uvm_test
13.2.1 Class declaration
13.2.2 Methods <\/td>\n<\/tr>\n
183<\/td>\n13.3 uvm_env
13.3.1 Class declaration
13.3.2 Methods
13.4 uvm_agent
13.4.1 Class declaration
13.4.2 Methods <\/td>\n<\/tr>\n
184<\/td>\n13.5 uvm_monitor
13.5.1 Class declaration
13.5.2 Methods
13.6 uvm_scoreboard
13.6.1 Class declaration
13.6.2 Methods <\/td>\n<\/tr>\n
185<\/td>\n13.7 uvm_driver #(REQ,RSP)
13.7.1 Class declaration
13.7.2 Ports
13.7.3 Methods
13.8 uvm_push_driver #(REQ,RSP) <\/td>\n<\/tr>\n
186<\/td>\n13.8.1 Class declaration
13.8.2 Ports
13.8.3 Methods
13.9 uvm_subscriber
13.9.1 Class declaration
13.9.2 Ports
13.9.3 Methods <\/td>\n<\/tr>\n
188<\/td>\n14. Sequences classes
14.1 uvm_sequence_item
14.1.1 Class declaration
14.1.2 Common fields <\/td>\n<\/tr>\n
190<\/td>\n14.1.3 Reporting interface <\/td>\n<\/tr>\n
192<\/td>\n14.2 uvm_sequence_base
14.2.1 Class declaration
14.2.2 Common methods <\/td>\n<\/tr>\n
193<\/td>\n14.2.3 Sequence execution <\/td>\n<\/tr>\n
194<\/td>\n14.2.4 Run-time phasing <\/td>\n<\/tr>\n
195<\/td>\n14.2.5 Sequence control <\/td>\n<\/tr>\n
198<\/td>\n14.2.6 Sequence item execution <\/td>\n<\/tr>\n
200<\/td>\n14.2.7 Response API <\/td>\n<\/tr>\n
201<\/td>\n14.3 uvm_sequence #(REQ,RSP)
14.3.1 Class declaration
14.3.2 Variables <\/td>\n<\/tr>\n
202<\/td>\n14.3.3 Methods
14.4 uvm_sequence_library <\/td>\n<\/tr>\n
203<\/td>\n14.4.1 Class declaration
14.4.2 Example
14.4.3 Common methods
14.4.4 Sequence selection <\/td>\n<\/tr>\n
205<\/td>\n14.4.5 Sequence registration <\/td>\n<\/tr>\n
207<\/td>\n15. Sequencer classes
15.1 Overview
15.1.1 Sequencer variants
15.1.2 Sequence item ports
15.2 Sequencer interface
15.2.1 uvm_sqr_if_base #(T1,T2) <\/td>\n<\/tr>\n
211<\/td>\n15.2.2 Sequence item pull ports <\/td>\n<\/tr>\n
212<\/td>\n15.3 uvm_sequencer_base
15.3.1 Class declaration
15.3.2 Methods <\/td>\n<\/tr>\n
216<\/td>\n15.3.3 Requests <\/td>\n<\/tr>\n
217<\/td>\n15.3.4 Responses
15.3.5 Default sequence <\/td>\n<\/tr>\n
218<\/td>\n15.4 Common sequencer API
15.4.1 Method
15.4.2 Request <\/td>\n<\/tr>\n
219<\/td>\n15.4.3 Responses
15.5 uvm_sequencer #(REQ,RSP)
15.5.1 Class declaration
15.5.2 Methods <\/td>\n<\/tr>\n
220<\/td>\n15.6 uvm_push_sequencer #(REQ,RSP)
15.6.1 Class declaration
15.6.2 Ports
15.6.3 Methods <\/td>\n<\/tr>\n
221<\/td>\n16. Policy classes
16.1 uvm_policy
16.1.1 Class declaration
16.1.2 Methods <\/td>\n<\/tr>\n
222<\/td>\n16.1.3 Active object <\/td>\n<\/tr>\n
223<\/td>\n16.1.4 recursion_state_e
16.2 uvm_printer <\/td>\n<\/tr>\n
224<\/td>\n16.2.1 Class declaration
16.2.2 Methods
16.2.3 Methods for printer usage <\/td>\n<\/tr>\n
228<\/td>\n16.2.4 Methods for printer subtyping <\/td>\n<\/tr>\n
229<\/td>\n16.2.5 Methods for printer configuration <\/td>\n<\/tr>\n
232<\/td>\n16.2.6 Methods for object print control
16.2.7 Element stack <\/td>\n<\/tr>\n
233<\/td>\n16.2.8 uvm_printer_element <\/td>\n<\/tr>\n
234<\/td>\n16.2.9 uvm_printer_element_proxy <\/td>\n<\/tr>\n
235<\/td>\n16.2.10 uvm_table_printer <\/td>\n<\/tr>\n
236<\/td>\n16.2.11 uvm_tree_printer <\/td>\n<\/tr>\n
237<\/td>\n16.2.12 uvm_line_printer <\/td>\n<\/tr>\n
238<\/td>\n16.3 uvm_comparer
16.3.1 Class declaration <\/td>\n<\/tr>\n
239<\/td>\n16.3.2 Methods
16.3.3 Methods for comparer usage <\/td>\n<\/tr>\n
242<\/td>\n16.3.4 Methods for comparer configuration <\/td>\n<\/tr>\n
243<\/td>\n16.3.5 Methods for comparer reporting control
16.3.6 Methods for object compare control <\/td>\n<\/tr>\n
244<\/td>\n16.4 uvm_recorder
16.4.1 Class declaration
16.4.2 Methods for recorder configuration <\/td>\n<\/tr>\n
245<\/td>\n16.4.3 Introspection API
16.4.4 Transaction recorder API <\/td>\n<\/tr>\n
246<\/td>\n16.4.5 Handles <\/td>\n<\/tr>\n
247<\/td>\n16.4.6 Attribute recording <\/td>\n<\/tr>\n
249<\/td>\n16.4.7 Implementation agnostic API <\/td>\n<\/tr>\n
252<\/td>\n16.5 uvm_packer
16.5.1 Class declaration
16.5.2 Methods <\/td>\n<\/tr>\n
253<\/td>\n16.5.3 Methods for packer subtyping <\/td>\n<\/tr>\n
254<\/td>\n16.5.4 Packing and unpacking <\/td>\n<\/tr>\n
258<\/td>\n16.6 uvm_copier
16.6.1 Class declaration
16.6.2 Methods <\/td>\n<\/tr>\n
259<\/td>\n16.6.3 Methods for object copy control
16.6.4 Methods for copier usage <\/td>\n<\/tr>\n
261<\/td>\n17. Register layer
17.1 Overview
17.2 Global declarations
17.2.1 Types <\/td>\n<\/tr>\n
262<\/td>\n17.2.2 Enumerations <\/td>\n<\/tr>\n
265<\/td>\n18. Register model
18.1 uvm_reg_block
18.1.1 Class declaration
18.1.2 Methods <\/td>\n<\/tr>\n
267<\/td>\n18.1.3 Introspection <\/td>\n<\/tr>\n
271<\/td>\n18.1.4 Coverage <\/td>\n<\/tr>\n
273<\/td>\n18.1.5 Access <\/td>\n<\/tr>\n
274<\/td>\n18.1.6 Back door <\/td>\n<\/tr>\n
277<\/td>\n18.2 uvm_reg_map
18.2.1 Class declaration
18.2.2 Common methods
18.2.3 Methods <\/td>\n<\/tr>\n
280<\/td>\n18.2.4 Introspection <\/td>\n<\/tr>\n
283<\/td>\n18.2.5 Bus access <\/td>\n<\/tr>\n
285<\/td>\n18.3 uvm_reg_file
18.3.1 Class declaration
18.3.2 Methods
18.3.3 Introspection <\/td>\n<\/tr>\n
286<\/td>\n18.3.4 Back door <\/td>\n<\/tr>\n
287<\/td>\n18.4 uvm_reg
18.4.1 Class declaration
18.4.2 Methods <\/td>\n<\/tr>\n
288<\/td>\n18.4.3 Introspection <\/td>\n<\/tr>\n
291<\/td>\n18.4.4 Access <\/td>\n<\/tr>\n
297<\/td>\n18.4.5 Front door <\/td>\n<\/tr>\n
298<\/td>\n18.4.6 Back door <\/td>\n<\/tr>\n
300<\/td>\n18.4.7 Coverage <\/td>\n<\/tr>\n
303<\/td>\n18.4.8 Callbacks <\/td>\n<\/tr>\n
304<\/td>\n18.5 uvm_reg_field
18.5.1 Class declaration
18.5.2 Common methods
18.5.3 Methods <\/td>\n<\/tr>\n
305<\/td>\n18.5.4 Introspection <\/td>\n<\/tr>\n
308<\/td>\n18.5.5 Access <\/td>\n<\/tr>\n
314<\/td>\n18.5.6 Callbacks <\/td>\n<\/tr>\n
315<\/td>\n18.6 uvm_mem
18.6.1 Class declaration
18.6.2 Variables
18.6.3 Methods <\/td>\n<\/tr>\n
316<\/td>\n18.6.4 Introspection <\/td>\n<\/tr>\n
320<\/td>\n18.6.5 HDL access <\/td>\n<\/tr>\n
323<\/td>\n18.6.6 Front door
18.6.7 Back door <\/td>\n<\/tr>\n
326<\/td>\n18.6.8 Coverage <\/td>\n<\/tr>\n
328<\/td>\n18.6.9 Callbacks <\/td>\n<\/tr>\n
329<\/td>\n18.7 uvm_reg_indirect_data
18.7.1 Class declaration
18.7.2 Methods <\/td>\n<\/tr>\n
330<\/td>\n18.8 uvm_reg_fifo
18.8.1 Class declaration
18.8.2 Common variables
18.8.3 Methods
18.8.4 Introspection <\/td>\n<\/tr>\n
331<\/td>\n18.8.5 Access <\/td>\n<\/tr>\n
333<\/td>\n18.9 uvm_vreg
18.9.1 Class declaration <\/td>\n<\/tr>\n
341<\/td>\n18.9.2 uvm_vreg_cbs <\/td>\n<\/tr>\n
343<\/td>\n18.10 uvm_vreg_field
18.10.1 Class declaration
18.10.2 Methods
18.10.3 Introspection <\/td>\n<\/tr>\n
344<\/td>\n18.10.4 HDL access <\/td>\n<\/tr>\n
345<\/td>\n18.10.5 Callbacks <\/td>\n<\/tr>\n
347<\/td>\n18.10.6 uvm_vreg_field_cbs <\/td>\n<\/tr>\n
348<\/td>\n18.11 uvm_reg_cbs
18.11.1 Class declaration
18.11.2 Methods <\/td>\n<\/tr>\n
352<\/td>\n18.11.3 Types
18.11.4 uvm_reg_read_only_cbs
18.11.5 uvm_reg_write_only_cbs <\/td>\n<\/tr>\n
353<\/td>\n18.12 uvm_mem_mam
18.12.1 Class declaration
18.12.2 Types <\/td>\n<\/tr>\n
354<\/td>\n18.12.3 Variables
18.12.4 Methods <\/td>\n<\/tr>\n
355<\/td>\n18.12.5 Memory management <\/td>\n<\/tr>\n
356<\/td>\n18.12.6 Introspection
18.12.7 uvm_mem_region <\/td>\n<\/tr>\n
359<\/td>\n18.12.8 uvm_mem_mam_policy <\/td>\n<\/tr>\n
360<\/td>\n18.12.9 uvm_mem_mam_cfg <\/td>\n<\/tr>\n
362<\/td>\n19. Register layer interaction with RTL design
19.1 Generic register operation descriptors
19.1.1 uvm_reg_item <\/td>\n<\/tr>\n
365<\/td>\n19.1.2 uvm_reg_bus_op <\/td>\n<\/tr>\n
366<\/td>\n19.2 Classes for adapting between register and bus operations
19.2.1 uvm_reg_adapter <\/td>\n<\/tr>\n
367<\/td>\n19.2.2 uvm_reg_tlm_adapter <\/td>\n<\/tr>\n
368<\/td>\n19.3 uvm_reg_predictor
19.3.1 Class declaration
19.3.2 Variables <\/td>\n<\/tr>\n
369<\/td>\n19.3.3 Methods <\/td>\n<\/tr>\n
370<\/td>\n19.4 Register sequence classes
19.4.1 uvm_reg_sequence <\/td>\n<\/tr>\n
376<\/td>\n19.4.2 uvm_reg_frontdoor <\/td>\n<\/tr>\n
377<\/td>\n19.5 uvm_reg_backdoor
19.5.1 Class declaration
19.5.2 Methods <\/td>\n<\/tr>\n
380<\/td>\n19.6 UVM HDL back-door access support routines
19.6.1 Variables
19.6.2 Methods <\/td>\n<\/tr>\n
382<\/td>\nAnnex A (informative) Bibliography <\/td>\n<\/tr>\n
383<\/td>\nAnnex B (normative) Macros and defines <\/td>\n<\/tr>\n
408<\/td>\nAnnex C (normative) Configuration and resource classes
C.1 Overview
C.2 Resources <\/td>\n<\/tr>\n
417<\/td>\nC.3 UVM resource database <\/td>\n<\/tr>\n
420<\/td>\nC.4 UVM configuration database <\/td>\n<\/tr>\n
423<\/td>\nAnnex D (normative) Convenience classes, interface, and methods
D.1 uvm_callback_iter <\/td>\n<\/tr>\n
424<\/td>\nD.2 Component interfaces <\/td>\n<\/tr>\n
428<\/td>\nD.3 uvm_reg_block access methods <\/td>\n<\/tr>\n
430<\/td>\nD.4 Callback typedefs <\/td>\n<\/tr>\n
432<\/td>\nAnnex E (normative) Test sequences
E.1 uvm_reg_hw_reset_seq <\/td>\n<\/tr>\n
433<\/td>\nE.2 Bit bashing test sequences <\/td>\n<\/tr>\n
434<\/td>\nE.3 Register access test sequences <\/td>\n<\/tr>\n
436<\/td>\nE.4 Shared register and memory access test sequences <\/td>\n<\/tr>\n
439<\/td>\nE.5 Memory access test sequences <\/td>\n<\/tr>\n
440<\/td>\nE.6 Memory walking-ones test sequences <\/td>\n<\/tr>\n
442<\/td>\nE.7 uvm_reg_mem_hdl_paths_seq <\/td>\n<\/tr>\n
443<\/td>\nE.8 uvm_reg_mem_built_in_seq <\/td>\n<\/tr>\n
444<\/td>\nAnnex F (normative) Package scope functionality
F.1 Overview
F.2 Types and enumerations <\/td>\n<\/tr>\n
451<\/td>\nF.3 Methods and types <\/td>\n<\/tr>\n
454<\/td>\nF.4 Core service <\/td>\n<\/tr>\n
459<\/td>\nF.5 Traversal <\/td>\n<\/tr>\n
462<\/td>\nF.6 uvm_run_test_callback <\/td>\n<\/tr>\n
463<\/td>\nF.7 uvm_root <\/td>\n<\/tr>\n
467<\/td>\nAnnex G (normative) Command line arguments
G.1 Command line processing <\/td>\n<\/tr>\n
469<\/td>\nG.2 Built-in UVM-aware command line arguments <\/td>\n<\/tr>\n
472<\/td>\nBack cover <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard for Universal Verification Methodology Language Reference Manual<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n2017<\/td>\n472<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":194737,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-194733","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/194733","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/194737"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=194733"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=194733"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=194733"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}