{"id":233919,"date":"2024-10-19T15:15:21","date_gmt":"2024-10-19T15:15:21","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/bs-iec-63011-32018\/"},"modified":"2024-10-25T09:46:34","modified_gmt":"2024-10-25T09:46:34","slug":"bs-iec-63011-32018","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/bsi\/bs-iec-63011-32018\/","title":{"rendered":"BS IEC 63011-3:2018"},"content":{"rendered":"
IEC 63011-3:2018 specifies a reference model of through-silicon via (TSV) electrical characteristics required for an interface design in three dimensional integrated circuit (3-D IC) to transmit and receive digital data and measurement conditions for resistance and capacitance to specify TSV characteristics in 3-D IC. Power devices, RF devices and micro-electromechanical systems (MEMS) are not in the scope of this document. <\/p>\n
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2<\/td>\n | undefined <\/td>\n<\/tr>\n | ||||||
4<\/td>\n | English CONTENTS <\/td>\n<\/tr>\n | ||||||
5<\/td>\n | FOREWORD <\/td>\n<\/tr>\n | ||||||
7<\/td>\n | INTRODUCTION <\/td>\n<\/tr>\n | ||||||
8<\/td>\n | 1 Scope 2 Normative references Figures Figure 1 \u2013 Reference of a multi-chip interconnect system <\/td>\n<\/tr>\n | ||||||
9<\/td>\n | 3 Terms, definitions and abbreviated terms 3.1 Terms and definitions 3.2 Abbreviated terms 4 Measurement conditions to specify TSV characteristics 4.1 Supply chain and TSV circuit model Figure 2 \u2013 3-D IC Supply chain model <\/td>\n<\/tr>\n | ||||||
10<\/td>\n | 4.2 Reference model of TSV electrical characteristics Figure 3 \u2013 TSV electrical characteristic model <\/td>\n<\/tr>\n | ||||||
11<\/td>\n | 4.3 Measurement conditions to specify TSV electrical characteristics 4.3.1 General 4.3.2 Resistance measurement Tables Table 1 \u2013 Policy for model standardization <\/td>\n<\/tr>\n | ||||||
12<\/td>\n | 4.3.3 Capacitance measurement Figure 4 \u2013 Resistance measurement method Figure 5 \u2013 Capacitance measurement method <\/td>\n<\/tr>\n | ||||||
13<\/td>\n | Figure 6 \u2013 Measurement conditions to specify TSV electrical characteristicswhen substrate is not connected to power supply <\/td>\n<\/tr>\n | ||||||
14<\/td>\n | Annex A (informative)Explanatory note A.1 Purpose of establishment A.2 Reference dimension of the TSV model Table A.1 \u2013 Parameters and reference values of the TSV model <\/td>\n<\/tr>\n | ||||||
15<\/td>\n | A.3 Other considerations for implementation A.3.1 General A.3.2 Keep out zone Figure A.1 \u2013 Structure of the TSV model <\/td>\n<\/tr>\n | ||||||
16<\/td>\n | Figure A.2 \u2013 KOZ definition Table A.2 \u2013 Parameters affecting KOZ <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Integrated circuits. Three dimensional integrated circuits – Model and measurement conditions of through-silicon via<\/b><\/p>\n |