{"id":396020,"date":"2024-10-20T04:22:25","date_gmt":"2024-10-20T04:22:25","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-896-1-1991\/"},"modified":"2024-10-26T08:09:12","modified_gmt":"2024-10-26T08:09:12","slug":"ieee-896-1-1991","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-896-1-1991\/","title":{"rendered":"IEEE 896.1-1991"},"content":{"rendered":"

Revision Standard – Inactive-Withdrawn. IEEE Std 896.1-1991 provides a set of tools with which to implement a Futurebus+architecture with performance and cost scalability over time, for multiple generations of single- and multiple-bus multiprocessor systems. Although this specification is principally intended for 64-bit address and data operation, a fully compatible 32-bit subset is provided, along with compatible extensions to support 128- and 256-bit data highways. Allocation of bus bandwidth to competing modules is provided by either a fast centralized arbiter, or a fully distributed, one or two pass, parallel contention arbiter. Bus allocation rules are provided to suit the needs of both real-time (priority based) and fairness (equal opportunity access based) configurations. Transmission of data over the multiplexed address\/data highway is governed by one of two intercompatible transmission methods: (1) a technology-independent, compelled-protocol, supporting broadcast, broadcall, and transfer intervention (the minimum requirement for all Futurebus+systems), and (2) a configurable transfer-rate, source-synchronized protocol supporting only block transfers and source-synchronized broadcast for systems requiring the highest possible performance.<\/p>\n

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
12<\/td>\nOUAD15 I aumu I QUAD13 I QUAD <\/td>\n<\/tr>\n
19<\/td>\n1 Introduction
1.1 Scope <\/td>\n<\/tr>\n
21<\/td>\nDefinitions and Structure
Special Word Usage
2.2 Definitions <\/td>\n<\/tr>\n
26<\/td>\n2.3 Signal Conventions
2.4 Document Structure <\/td>\n<\/tr>\n
27<\/td>\n2.5 Futurebus+ Logo
Bus Line Description
Information Lines
AddressEeturn Address <\/td>\n<\/tr>\n
28<\/td>\nD[255 641* Data Lines
CM[7 01* Command
2.6.1.4 CP* Command Parity
ST[7 01* Status
List of Bus Lines <\/td>\n<\/tr>\n
29<\/td>\nCN2 01* Capability
2.6.1.7 BPI31 01* Bus Parity
TGE7 01* Tag
2.6.1.9 TP* Tag Parity
Synchronization Lines
AS* Address Synchronization
AK* Address Acknowledge
AI* Address Acknowledge Inverse
DS* Data Synchronization
DK* Data Acknowledge
2.6.2.6 DI* Data Acknowledge Inverse
2.6.2.7 ET* End of Tenure
Distributed Arbitration and Arbitrated Message Lines
2.6.3.1 AB17 01* Arbitration Bus
2.6.3.2 ABP* Arbitration Parity <\/td>\n<\/tr>\n
30<\/td>\nA AR* Control Acquisition Synchronization
ACCl 01* Arbitration Condition
RE* Resenus Initialize
Central Arbiter
2.6.5.1 PE* Preemption
2.6.5.2 GR* Grant
2.6.5.3 RQ[l 01* Request
GA[4 Ol* Geographical Address
Reference <\/td>\n<\/tr>\n
38<\/td>\nMnemonics <\/td>\n<\/tr>\n
39<\/td>\nBus Signaling Environment
3.1 Description
Incident Wave Switching
3.1.2 Skew <\/td>\n<\/tr>\n
40<\/td>\n3.2 Specification
3.2.1 Skew
3.2.2 Glitch Filters
Centralized Arbitration
4.1 Description <\/td>\n<\/tr>\n
41<\/td>\n4.1.1 Bus Lines Used for Centralized Arbitration
4.1.1.1 RQO* Request
4.1.1.2 RQ1* Request
4.1.1.3 GR* Grant
4.1.1.4 PE* Preempt
Centralized Arbitration Operation <\/td>\n<\/tr>\n
42<\/td>\nCentral Arbiter Description
4.2 Specification
Bus Arbitration Attributes
Two-Competitor Centralized Arbitration <\/td>\n<\/tr>\n
43<\/td>\nBus Arbitration Signals
4.2.2.1 RQO*
4.2.2.2 RQ1*
4.2.2.3 GR*
4.2.2.4 PE*
Distributed Arbitration and Arbitrated Messages
5.1 Description
Arbitrated Messages-Central Arbiter <\/td>\n<\/tr>\n
44<\/td>\nGeneral Arbitrated Messages
5.1.1.2 Central Arbitrated Messages
and Messages-Distributed Arbiter
General Arbitrated Message Fields
Central Arbitrated Message Fields <\/td>\n<\/tr>\n
45<\/td>\nDistributed Arbitration Messages
Distributed Arbitration Message Fields
Distributed Arbitration Request Fields <\/td>\n<\/tr>\n
46<\/td>\n5.1.2.2.2 Round-Robin Field
Geographical Address Field
Deposing the Master Elect
5.1.2.4 Transaction Preemption <\/td>\n<\/tr>\n
47<\/td>\n5.1.2.5 Parking
Bus Lines
AP A AR* Control Acquisition Synchronization
AC[1 01* Arbitration Condition
5.1.3.3 ABC7 03* Arbitration Bus
5.1.3.4 ABP* Arbitration Parity
Arbitration Competition Logic <\/td>\n<\/tr>\n
48<\/td>\nArbitration Competition Settling Time
Fig 5(a) Serial Implementation of Parallel Contention Logic
Parallel Implementation of Parallel Contention Logic <\/td>\n<\/tr>\n
49<\/td>\nArbitration States
Arbitration Competition Example <\/td>\n<\/tr>\n
50<\/td>\nArbitration Phases
Control Acquisition States <\/td>\n<\/tr>\n
51<\/td>\nPhase 0: Idle Phase
Phase 1: Decision Phase
Control Acquisition Sequence <\/td>\n<\/tr>\n
52<\/td>\nPhase 2: Competition Phase
Phase 3: Error Check
Phase 4: Master Release <\/td>\n<\/tr>\n
53<\/td>\nPhase 5: Tenurehlessage Transfer <\/td>\n<\/tr>\n
54<\/td>\nArbitration Examples
Single-Pass Competition (Central or Distributed)
Single-Pass Competition <\/td>\n<\/tr>\n
55<\/td>\nSingle-Pass Deposed (Distributed) Competition
Single-Pass Deposed Competition <\/td>\n<\/tr>\n
56<\/td>\nDistributed Arbitration Message
Arbitration Message <\/td>\n<\/tr>\n
57<\/td>\nTwo-Pass Competition (Central or Distributed)
C om p e ti ti on <\/td>\n<\/tr>\n
58<\/td>\nSingle-Pass Competition with Error
Arbitrated Message Attributes-Central Arbiter
Arbitrated Message Attributes-Distributed Arbiter
Single-Pass Competition with Error <\/td>\n<\/tr>\n
59<\/td>\n5.2 Specification <\/td>\n<\/tr>\n
60<\/td>\nArbitration AttributecDistributed Arbiter <\/td>\n<\/tr>\n
61<\/td>\nGeneral Arbitration and Message Attributes <\/td>\n<\/tr>\n
63<\/td>\nArbitration Error Attributes
Signal Definition
5.2.7.1 Arbitration Synchronization
5.2.7.1.1 AP* <\/td>\n<\/tr>\n
64<\/td>\n5.2.7.1.2 AQ*
5.2.7.1.3 AR*
5.2.7.2 Arbitration Condition
5.2.7.2.1 ACO*
5.2.7.2.2 AC1*
5.2.7.3 Arbitration Bus
5.2.7.3.1 AB7*
5.2.7.3.2 AB6*
5.2.7.3.3 AB5*
5.2.7.3.4 AB4*
5.2.7.3.5 AB3*
5.2.7.3.6 AB2*
5.2.7.3.7 AB1*
5.2.7.3.8 ABO*
5.2.7.3.9 ABP*
Protocol Definition-Distributed Arbitration and Messages
5.2.8.1 Phase &Idle <\/td>\n<\/tr>\n
65<\/td>\n5.2.8.2 Phase 1-Decision
5.2.8.3 Phase Uompetition
Phase 3-Error Check <\/td>\n<\/tr>\n
66<\/td>\nPhase &Release Mastership
Phase &Transfer Tenure
Protocol Definition-central Arbiter Messages
5.2.9.1 Phase “Idle <\/td>\n<\/tr>\n
67<\/td>\n5.2.9.2 Phase 1-Decision
5.2.9.3 Phase Mompetition
Phase &Error Check
Phase &Release Mastership
Phase &Transfer Tenure <\/td>\n<\/tr>\n
69<\/td>\nParallel Protocol
6.1 Description
6.1.1 Mastership
6.1.2 Transactions
Bus Transaction Phases <\/td>\n<\/tr>\n
70<\/td>\nData Transfer Protocols
6.1.5 Broadcast Handshake <\/td>\n<\/tr>\n
71<\/td>\n6.1.8 Split Transactions
6.1.9 Locked Operations <\/td>\n<\/tr>\n
72<\/td>\n6.1.10 Lock Commands
Mask and Swap Lock Command <\/td>\n<\/tr>\n
73<\/td>\nFetch and Add Lock Command
Mask and Swap Lock Command <\/td>\n<\/tr>\n
74<\/td>\nCompare and Swap Lock Command
Fetch and Add Lock Command <\/td>\n<\/tr>\n
75<\/td>\nCompare and Swap Lock Command <\/td>\n<\/tr>\n
76<\/td>\nBusy
Wait
Extended Bus Width
Extended Address <\/td>\n<\/tr>\n
78<\/td>\n6.1.16.4 Read Locked
6.1.16.5 Write Locked
Address Only Locked
6.1.16.7 Read Partial
6.1.16.8 Write Partial
Read Partial Locked
6.1.16.10 Write Partial Locked
6.1.16.11 Write Response
6.1.16.12 Read Response <\/td>\n<\/tr>\n
79<\/td>\n6.1.16.13 Write No Acknowledge
6.1.1 6.14 Read Invalid
6.1.16.15 Write Invalid
6.1.16.16 Copyback
6.1.16.17 Read Shared
6.1.1 6.1 8 Read Modified
6.1.16.19 Invalidate
6.1.1 6.20 Shared Response <\/td>\n<\/tr>\n
80<\/td>\n6.1.16.21 Modified Response
Bus Signal Descriptions
AS* Address Sync
AK* Address Acknowledge
AI* Address Acknowledge Inverse
DS* Data Sync
DK* Data Acknowledge <\/td>\n<\/tr>\n
81<\/td>\n6.1.17.6 DI* Data Acknowledge Inverse
CM[7 01* Command Field
CM7* Command
6.1.17.10.3 CAO* Capability
Command Field Encoding <\/td>\n<\/tr>\n
82<\/td>\n6.1.17.7.2 CM6* Command
CM5* Command
Data Path Width <\/td>\n<\/tr>\n
83<\/td>\nCM4* Command
CM3* Command
Transaction Command Encoding <\/td>\n<\/tr>\n
84<\/td>\nCM2* Command
CM1* Command
CMO* Command
6.1.17.8 CP* Command Parity
ST[7 01* Status
Table 10 Locked Command Encoding <\/td>\n<\/tr>\n
85<\/td>\nm’7* Status
6.1.17.9.2 ST6*Status6
ST5* Status
6.1.17.9.4 ST4*Status4
6.1.17.9.5 ST3*Status3
Table 11 Status Encoding <\/td>\n<\/tr>\n
86<\/td>\n6.1.17.9.6 ST2*Status2
6.1.17.9.7 ST1* Status1
6.1.17.9.8 STO*StatusO
CAC2 Ol* Capability
Table 12 Capability Encoding <\/td>\n<\/tr>\n
87<\/td>\n6.1.17.10.1 CA2* Capability
6.1.17.10.2 CAl* Capability
6.1.17.11 AD131 01* Address\/Data\/Lane DeselectIReturn Address <\/td>\n<\/tr>\n
88<\/td>\n6.1.17.12 AD[63 321* Address\/Data
Data
6.1.17.14 BFT31 01* Byte Parity <\/td>\n<\/tr>\n
89<\/td>\n6.1.17.15 TG[7 01* Tag
6.1.17.16 TP* Tag Parity
6.1.17.17 ET* End of Tenure
6.1.18 Bus Beats
Single Slave Bus Beat <\/td>\n<\/tr>\n
90<\/td>\nMultiple Slave Bus Beat
Single Slave Bus Beat <\/td>\n<\/tr>\n
91<\/td>\n6.1.19 Transaction Examples
6.1.19.1 Address Only Transaction
Multiple Slave Bus Beat <\/td>\n<\/tr>\n
92<\/td>\nAddress Only Transaction <\/td>\n<\/tr>\n
93<\/td>\n6.1.19.2 Compelled Read
Compelled Read Transaction <\/td>\n<\/tr>\n
94<\/td>\nCompelled Read BroadcastlBroadcall
Compelled Read Transaction with Broadcall <\/td>\n<\/tr>\n
95<\/td>\nCompelled Read Intervention
Compelled Read Transaction with Intervention <\/td>\n<\/tr>\n
96<\/td>\nCompelled Read Partial
Compelled Read Partial Transaction <\/td>\n<\/tr>\n
97<\/td>\n6.1.19.6 Compelled Write
Compelled Write Transaction <\/td>\n<\/tr>\n
98<\/td>\nCompelled Write Broadcast
Compelled Write Transaction with Broadcast <\/td>\n<\/tr>\n
99<\/td>\nCompelled Write Partial
Compelled Write Partial Transaction <\/td>\n<\/tr>\n
100<\/td>\n6.1.19.9 Transaction Error
Transaction Error Timing <\/td>\n<\/tr>\n
101<\/td>\n6.1.19.10 Packet Data Phase
Packet Data Phase Timing <\/td>\n<\/tr>\n
102<\/td>\n6.1.19.11 Single Packet Read
Single Packet Read Transaction <\/td>\n<\/tr>\n
103<\/td>\n6.1.19.12 Single Packet Read Broadcast
Single Packet Read Transaction with Broadcast <\/td>\n<\/tr>\n
104<\/td>\n6.1.19.13 Single Packet Read Intervention
Single Packet Read Transaction with Intervention <\/td>\n<\/tr>\n
105<\/td>\n6.1.19.14 Single Packet Write
Single Packet Write Transaction <\/td>\n<\/tr>\n
106<\/td>\n6.1.19.15 Multiple Packet Read Intervention
Multiple Packet Read Transaction with Intervention <\/td>\n<\/tr>\n
107<\/td>\n6.1.19.16 Multiple Packet Read Intervention Queued
Multiple Packet Read Transaction with Intervention and Queueing <\/td>\n<\/tr>\n
108<\/td>\n6.2 Specification
6.2.1 Attribute Definition
Transfer Protocol Attributes
Split Transaction Attributes <\/td>\n<\/tr>\n
109<\/td>\nAddress\/Data Width Attributes
Transaction Attributes <\/td>\n<\/tr>\n
113<\/td>\nLocked OperationdAttributes <\/td>\n<\/tr>\n
114<\/td>\nData Transfer Length <\/td>\n<\/tr>\n
115<\/td>\nTransaction Status
Master Transaction Status <\/td>\n<\/tr>\n
116<\/td>\n6.2.1.7.2 Module Transaction Status <\/td>\n<\/tr>\n
118<\/td>\nTransaction Timing Attributes <\/td>\n<\/tr>\n
121<\/td>\nDefinition <\/td>\n<\/tr>\n
122<\/td>\nInverse)
(Command)
6.2.2.2 CM[7 01*
CMO* (Command
CM1* (Command
CM2* (Command
CM3* (Command
CM4* (Command
CM5* (Command
CM6* (Command
CM7* (Command
CP* (Command Parity)
6.2.2.3 CN2 Ol*
(Capability)
CAO* (TS*)
cAl* (CO*) <\/td>\n<\/tr>\n
123<\/td>\nCA2* (SR*)
6.2.2.4 ST[7 01*
(Status)
STO* (TE*)
ST1* (BS*\/ED*)
ST2* (SL*)
ST3* (BC*)
ST4* (TF*)
ST5* (IV*)
ST6* (BE*) <\/td>\n<\/tr>\n
124<\/td>\nSynchronization Signals
AS* (Address Sync)
AK* (Address Acknowledge)
AI* (Address Acknowledge Inverse)
DS* (Data Sync)
DK* (Data Acknowledge)
ST7* (WT*)
6.2.2.5 Information Fields
AD163 01* (AddresslData) <\/td>\n<\/tr>\n
127<\/td>\n6.2.2.5.3 BPI31 01* (Bus Parity) <\/td>\n<\/tr>\n
129<\/td>\nTG[7 01* (Tag)
TP* (Tag Parity)
6.2.2.5.6 ET*
6.2.3 Protocol Definition
Master Connection Phase <\/td>\n<\/tr>\n
130<\/td>\nSlave Connection Phase <\/td>\n<\/tr>\n
131<\/td>\nMaster Compelled Data Phase-First Odd Beat
Slave Compelled Data Phase-First Odd Beat <\/td>\n<\/tr>\n
132<\/td>\nMaster Compelled Data Phase-First Even Beat
Slave Compelled Data Phase-First Even Beat <\/td>\n<\/tr>\n
133<\/td>\nMaster Compelled Data Phase-Second Odd Beat
Slave Compelled Data Phase-Second Odd Beat <\/td>\n<\/tr>\n
134<\/td>\nOdd Beats
Odd Beats
Even Beats <\/td>\n<\/tr>\n
135<\/td>\nEven Beats
Master Packet Data Phase-Single Packet Mode <\/td>\n<\/tr>\n
136<\/td>\nSlave Packet Data Phasedingle Packet Mode
Odd Packet Queueing
Odd Packet Queueing
Even Packet Queueing <\/td>\n<\/tr>\n
137<\/td>\nEven Packet Queueing
Packet Transmission
Tr an sm i s s i o n <\/td>\n<\/tr>\n
138<\/td>\nPacket Data Protocol
Master Disconnection Phase <\/td>\n<\/tr>\n
139<\/td>\nSlave Disconnection Phase
Transaction Timeout Recovery <\/td>\n<\/tr>\n
140<\/td>\n7 BusISystem Management
7.1 Description
7.1.1 Bus Control
Power-up
7.1.1.2 System Reset
Power-up Sequence
Table 13 Event and RE* Relationships <\/td>\n<\/tr>\n
141<\/td>\nBus Initialize
7.1.1.4 Live Insertion
7.1.1.5 Live Withdrawal
System Reset Sequence <\/td>\n<\/tr>\n
142<\/td>\nFuturebus+ Control and Status Registers
Module Capability Registers <\/td>\n<\/tr>\n
143<\/td>\nModule Logical Capability Register <\/td>\n<\/tr>\n
144<\/td>\n7.1.2.2 Module Control Registers
Competition Internal Delay Register
Message Frame Size Register
Packet Speed Register <\/td>\n<\/tr>\n
145<\/td>\nLogical Common Control Register <\/td>\n<\/tr>\n
146<\/td>\nLogical Module Control Register
Bus Propogation Delay Register
Competition Settling Time Register
Transaction Time-out Register <\/td>\n<\/tr>\n
147<\/td>\n7.2 Specification
Bus Control Attributes
Message Passing Select Mask <\/td>\n<\/tr>\n
148<\/td>\nRE* Reset Signal
7.2.3 Protocol Definition
7.2.3.1 Powerup
7.2.3.2 System Reset
7.2.3.3 Bus Initialize
7.2.3.4 Live Insertion <\/td>\n<\/tr>\n
149<\/td>\n7.2.3.5 Live Withdrawal
Futurebus+ Control and Status Registers
Module Capability Registers <\/td>\n<\/tr>\n
151<\/td>\n7.2.4.2 Module Control Registers <\/td>\n<\/tr>\n
153<\/td>\nLogical Module Control Register
Bus Propagation Delay Register
Competition Settling Time Register <\/td>\n<\/tr>\n
154<\/td>\nTransaction Timeout Register
Message Passing Select Mask <\/td>\n<\/tr>\n
155<\/td>\nCache Coherence
8.1 Description
Shared Memory Architecture <\/td>\n<\/tr>\n
156<\/td>\n8.1.1 Cache Attributes
8.1.2 Bus Snooping <\/td>\n<\/tr>\n
157<\/td>\nCache Coherence Using Connected Transactions
8.1.3.1 State Changes
Invalid State
Shared Unmodified State <\/td>\n<\/tr>\n
158<\/td>\n8.1.3.2 Read Miss Process
Exclusive Unmodified State
Exclusive Modified State <\/td>\n<\/tr>\n
159<\/td>\n8.1.3.3 Write Miss Process
8.1.3.4 Copyback Process
8.1.3.5 I\/O Controller Optimization <\/td>\n<\/tr>\n
160<\/td>\n8.1.3.6 Examples
Connected Cache Coherence Model <\/td>\n<\/tr>\n
161<\/td>\nLocation
Write a Location <\/td>\n<\/tr>\n
162<\/td>\nCache Resident Fetch and Add <\/td>\n<\/tr>\n
163<\/td>\n8.1.4.1 Split Transactions
8.1.4.1.1 Shared Response
8.1.4.1.2 Modified Response <\/td>\n<\/tr>\n
164<\/td>\nSingle Outstanding Transaction Per Cache Line
Requester and Responder Attributes
8.1.4.4 I\/O Controller Optimization
8.1.4.5 Examples
Location <\/td>\n<\/tr>\n
165<\/td>\nWrite a Location <\/td>\n<\/tr>\n
166<\/td>\nUsing Split Transactions to Delay Invalidation Completions <\/td>\n<\/tr>\n
167<\/td>\n8.1.5.1 Cache Agents
8.1.5.2 Memory Agents
Split Response Architecture <\/td>\n<\/tr>\n
168<\/td>\n8.1.5.3 Split Transactions
8.1.5.3.1 Read Modified
8.1.5.3.2 Invalidate <\/td>\n<\/tr>\n
169<\/td>\n8.1.5.3.3 Write Invalid
8.1.5.3.4 Modified Response
Requester and Responder Attributes
Multiple Outstanding Transactions per Cache Line <\/td>\n<\/tr>\n
170<\/td>\n8.1.5.6 Examples <\/td>\n<\/tr>\n
171<\/td>\nMultiple Bus Segment Split Transaction Example Model <\/td>\n<\/tr>\n
173<\/td>\nWrite a Location <\/td>\n<\/tr>\n
178<\/td>\nSummary of Cache Coherence Commands and Status
Illegal Attribute Combinations
8.1.7.1 Shared Unmodified
8.1.7.2 Exclusive Unmodified
8.1.7.3 Exclusive Modified
Memory Line Modified
8.2 Specification
8.2.1 Module Attributes
8.2.2 Status Attributes <\/td>\n<\/tr>\n
181<\/td>\nCache Module Attributes Per Cache Line <\/td>\n<\/tr>\n
182<\/td>\nRequester Attributes Per Cache Line
Responder Attributes Per Cache Line <\/td>\n<\/tr>\n
183<\/td>\n8.2.6 Protocol Definition
Cache Line Size
8.2.6.2 Cache Line Transfers <\/td>\n<\/tr>\n
184<\/td>\n9 Message Passing
9.1 Description
Futurebus+ Message Passing <\/td>\n<\/tr>\n
185<\/td>\n9.1.1 Frame Level
9.1.1.1 Frame Structure
Frame Notation <\/td>\n<\/tr>\n
186<\/td>\n64-Byte Frame Format <\/td>\n<\/tr>\n
187<\/td>\n9.1.1.2 Mailbox Structure
9.1.1.2.1 Request Mailbox
9.1.1.2.2 Response Mailbox <\/td>\n<\/tr>\n
188<\/td>\n9.1.1.2.3 Broadcast Transactions
Message-Passing Mailboxes <\/td>\n<\/tr>\n
189<\/td>\nFrame Level Protocol
Broadcast Mailbox Select Attribute <\/td>\n<\/tr>\n
190<\/td>\n9.1.1.4 Message Priority
Frame Level Example
Linked List Message Passer <\/td>\n<\/tr>\n
191<\/td>\n9.1.2 Message Level
Message Level Frame Structure
Frame Type <\/td>\n<\/tr>\n
192<\/td>\nFuturebus+ Message Level Frame Structure <\/td>\n<\/tr>\n
193<\/td>\nFrame Size
Message Identification
Extended Header
Message Size
Frame Interval
Sequence Number
Exception Type
Unacknowledged Event Frame <\/td>\n<\/tr>\n
194<\/td>\nAcknowledged Event Frame
Event Positive Acknowledge Frame
Event Negative Acknowledge Frame
Multiple Frame Message Request Frame
Response Frame
Response Frame
Frame <\/td>\n<\/tr>\n
195<\/td>\nFrame
Frame
Frame
Multiple Frame Message Positive
Acknowledge Frame <\/td>\n<\/tr>\n
196<\/td>\n9.1.2.2 Message Protocols
Unacknowledged Single Frame Protocol
Acknowledged Single Frame Protocol
Ordered Multiple Frame Protocol
Unacknowledged Single Frame Message
Acknowledged Single Frame Message <\/td>\n<\/tr>\n
197<\/td>\nSequenced Multiple Frame Protocol
Ordered Multiple Frame Message <\/td>\n<\/tr>\n
198<\/td>\n9.1.2.3 Request\/Response Timeout
Multiple Frame Message Timeout
9.1.2.5 Frame Ordering
Sequenced Multiple Frame Message <\/td>\n<\/tr>\n
199<\/td>\nBus Tenure Time
9.2 Specification
9.2.1 Attribute Definition <\/td>\n<\/tr>\n
200<\/td>\nFrame Format Specification
Frame FormadNon-Futurebus+ Message Level
Frame FormatiUnacknowledged Event Frame <\/td>\n<\/tr>\n
201<\/td>\nFrame Format-Event Positive Acknowledge Frame <\/td>\n<\/tr>\n
203<\/td>\nResponse Frame
Data Frame
Data Frame <\/td>\n<\/tr>\n
204<\/td>\nOrdered Frame
Sequenced Frame <\/td>\n<\/tr>\n
205<\/td>\nAcknowledge Frame
Acknowledge Frame
9.2.3 Message Size
9.2.4 Frame Interval
9.2.5 Sequence Number <\/td>\n<\/tr>\n
206<\/td>\nException Type Field
9.2.7 Protocol Definition
Master Unacknowledged Single Frame Message Protocol
Slave Unacknowledged Single Frame Message Protocol
Slave Acknowledged Single Frame Message Protocol
Master Ordered Multiple Frame Message Protocol <\/td>\n<\/tr>\n
207<\/td>\nMaster Sequenced Multiple Frame Message Protocol
9.2.7.7 Slave Multiple Frame Message Protocol <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard for Futurebus+(R) — Logical Protocol Specification<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n1991<\/td>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":396024,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-396020","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/396020","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/396024"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=396020"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=396020"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=396020"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}