{"id":396048,"date":"2024-10-20T04:22:35","date_gmt":"2024-10-20T04:22:35","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-960-1986-2\/"},"modified":"2024-10-26T08:09:24","modified_gmt":"2024-10-26T08:09:24","slug":"ieee-960-1986-2","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-960-1986-2\/","title":{"rendered":"IEEE 960-1986"},"content":{"rendered":"

New IEEE Standard – Superseded. Mechanical, signal, electrical, and protocol specifications are given for a modular data bus system, which, while allowing equipment designers a wide choice of solutions, ensure compatibility of all designs that obey the mandatory parts of the specification. This standard applies to systems consisting of modular electronic instrument units that process or transfer data or signals, normally in association with computers or other automatic data processors.<\/p>\n

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
20<\/td>\nIntroduction and General Information
I Typical Power Supplies
I Typical Power Supplies
1.1 High Efficiency Power Supply
1.1.1 General
1.1.2 Efficiency
1.1.3 Ambient Temperature Range
1.1.4 Input <\/td>\n<\/tr>\n
21<\/td>\n1.1.5 Output
1.1.6 Remote Sense
1.1.7 Regulation and Stability
1.1.8 Temperature Coefficient
Basic FASTBUS Elements <\/td>\n<\/tr>\n
22<\/td>\n1.1.9 Noise and Ripple
1.1.10 Recovery Time and Turn-on and Turn-off Transients
1.1.1 1 Conducted and Radiated Noise
1.1.12 Output Terminals
1.1.13 Voltage Adjustment Controls <\/td>\n<\/tr>\n
23<\/td>\n1.1.14 Protection
1.1.15 Monitoring
1.1.16 Margining
1.1.17 External Breaker Trip Control
Example of FASTBUS System Topology <\/td>\n<\/tr>\n
24<\/td>\n1.1.18 Switched ac Outlet
1.1.19 Front Panel
1.1.20 Rack Mounting
I 1.2 1 Cooling
1.2 Low-Noise Power Supply
1.2.1 General
1.2.2 Efficiency
1.2.3 Ambient Temperature Range
1.2.4 Input
1.2.5 Output
1.2.6 Remote Sense
1.2.7 Regulation and Stability <\/td>\n<\/tr>\n
25<\/td>\n1.2.8 Temperature Coefficient
1.2.9 Noise and Ripple
1.2.10 Recovery Time and Turn-on and Turn-off Transients
1.2.11 Conducted and Radiated Noise
1.2.12 Output Terminals
1.2.13 Voltage Aaustment Controls
1.2.14 Protection
1.2.15 Monitoring
1.2.16 Margining
1.2.17 External Breaker Trip Control
1.2.18 Switched ac Outlet
1.2.19 Front Panel
1.2.20 Rack Mounting
1.2.21 Cooling
FASTBUS Signals <\/td>\n<\/tr>\n
26<\/td>\nBasic Handshake Read Operation (as seen by Master) <\/td>\n<\/tr>\n
29<\/td>\nWrite Block Transfer (as seen by Master) <\/td>\n<\/tr>\n
30<\/td>\nAddress-Locked Operation Read-Modify-Write (as seen by Master) <\/td>\n<\/tr>\n
35<\/td>\nConventions Definitions Abbreviations and Symbols
Signal Characteristics
12.1 Signal Levels l <\/td>\n<\/tr>\n
47<\/td>\nSignals Signal Lines and Pins
Modules l
13 Modules l
Module Circuit Board l <\/td>\n<\/tr>\n
49<\/td>\n3.3.17 AI Arbitration Request Inhibit CA. ANC) <\/td>\n<\/tr>\n
50<\/td>\n3.3.18 SR Service Request A. Master or Slave)
3.3.19 RB Reset Bus A. Master or Master via SIs)
3.3.20 BH Bus Halted C. ANC)
3.3.21 GA Geographical Address F. Hardwired)
3.3.22 TP T Pins I. Slave)
3.3.23 DL DR Daisy Chain I. Master or Slave)
3.3.24 TX RX Serial Network Lines A. Master or Slave) <\/td>\n<\/tr>\n
51<\/td>\n3.3.25 TR Terminated Restricted Use Lines
3.3.26 UR Unterminated Restricted Use Lines
Other Lines and Pins
3.4 Bus Loading
Voltage and Current Limits for Signal Lines and F Pins
13.2 Connectors l <\/td>\n<\/tr>\n
52<\/td>\nCrates l <\/td>\n<\/tr>\n
53<\/td>\n4.1 Logical Addressing <\/td>\n<\/tr>\n
55<\/td>\nGeographical Address Formats <\/td>\n<\/tr>\n
59<\/td>\nOther Backplane Items <\/td>\n<\/tr>\n
62<\/td>\nSparse Data Scan and Pattern Select Operation <\/td>\n<\/tr>\n
63<\/td>\nFASTBUS Operations: Timing Sequences and Responses
Power l
FASTBUS Operations: Timing Sequences and Responses
5.1 General Master\/Slave Timing Requirements
Handshaked Cycle Timing Sequence <\/td>\n<\/tr>\n
64<\/td>\nMaster Signal Timing Requirements
Tracing the Route Taken by an Operation
5.1.8 SS=4 at Address Time – Reserved
SS=5 at Address Time – Reserved
5.1.11 SS=7 at Address Time – Invalid IA Accepted
Time-out at Data Time <\/td>\n<\/tr>\n
65<\/td>\nSlave Status Responses
5.3.1 SS=O-Valid Action
5.3.2 SS=l-Busy
SS=2 -End of Block
5.3.4 SS=3 – User Defined
5.3.5 SS = 4 – Reserved
5.3.6 SS=5 -Resewed
SS=6 -Data Error (Reject)
SS=7 -Data Error (Accept) <\/td>\n<\/tr>\n
66<\/td>\nUse of Wait (WT)
Host Response to Error Messages
Errors in Transfers to or from FIFOs and 1\/0 Ports
5.5.1 Introduction <\/td>\n<\/tr>\n
67<\/td>\n5.2 Primary Address Cycles
Protective Buffers for Read Operations
Protective Buffers for Write Operations <\/td>\n<\/tr>\n
68<\/td>\nLogical Address Cycle <\/td>\n<\/tr>\n
71<\/td>\nMaster Sequence for Asserting AS
Slave Response to AS(u)
Address Type Specification <\/td>\n<\/tr>\n
72<\/td>\nMaster Response to AK(u) <\/td>\n<\/tr>\n
73<\/td>\nAddress Time SS Response with AK(u) <\/td>\n<\/tr>\n
76<\/td>\nMaster Sequence for Asserting DS
Block Transfer Write <\/td>\n<\/tr>\n
77<\/td>\nMS Interpretation for Data Cycles <\/td>\n<\/tr>\n
78<\/td>\nDiscussion of Slave Status Responses
Slave Data Time SS Responses With DK(t)
Slave SS Responses and Actions at DK(t) <\/td>\n<\/tr>\n
80<\/td>\nMaster Response to DK(t)
Use of Reset Bus (RB) <\/td>\n<\/tr>\n
81<\/td>\n5.4.2 Device Response to RB
Device Response to POWER ON <\/td>\n<\/tr>\n
82<\/td>\nBus Arbitration
Cable Segment l
6 Bus Arbitration
16.2 Cable Segment Connectors and Contact Assignments <\/td>\n<\/tr>\n
83<\/td>\nBus Line Usage for the Arbitration Process
FASTBUS Arbitration Lines <\/td>\n<\/tr>\n
84<\/td>\n6.2 The Arbitration Process <\/td>\n<\/tr>\n
85<\/td>\nArbitration Control Logic in a Master
Arbitration Logic in a Master <\/td>\n<\/tr>\n
86<\/td>\nArbitration for Two Masters Showing Worst-case Delays <\/td>\n<\/tr>\n
87<\/td>\nArbitration for Three Masters Showing Worst-case Delays <\/td>\n<\/tr>\n
88<\/td>\n6.3 Arbitration Rules
AR
6.3.2 ATC Assertion and Release of AI <\/td>\n<\/tr>\n
89<\/td>\nATC Assertion and Release of AG
Master Assertion and Release of AL <\/td>\n<\/tr>\n
90<\/td>\nMaster Assertion and Release of GK
6.4 System-Wide Arbitration <\/td>\n<\/tr>\n
92<\/td>\nAncillary Logic on a Segment
Ancillary Logic on a Segment
Arbitration Timing Control (ATC)
7.1.1 ATC Generation of AI
7.1.2 ATC Generation of AG <\/td>\n<\/tr>\n
93<\/td>\n7.2 Geographical Address Control <\/td>\n<\/tr>\n
94<\/td>\nSystem Handshake Generation (Broadcast) <\/td>\n<\/tr>\n
95<\/td>\n7.4 Run\/Halt Control and Bus Halted <\/td>\n<\/tr>\n
96<\/td>\n7.5 Terminators
7.6 Ancillary Logic for Crate Segments <\/td>\n<\/tr>\n
97<\/td>\n7.7 Ancillary Logic for Cable Segments <\/td>\n<\/tr>\n
98<\/td>\nControl and Status Register Space
Control and Status Register Space <\/td>\n<\/tr>\n
99<\/td>\nSelective Set and Clear Functions <\/td>\n<\/tr>\n
100<\/td>\n8.2 Normal CSR Space Allocation
8.3 CSR Register <\/td>\n<\/tr>\n
102<\/td>\n8.3.1 Device IDS and Their Allocation
8.3.2 Control and Status Bit Allocation
CSR Register 0 Bit Assignments <\/td>\n<\/tr>\n
104<\/td>\n8.4 CSR Register
8.5 CSR Register <\/td>\n<\/tr>\n
106<\/td>\n8.6 CSR Register <\/td>\n<\/tr>\n
107<\/td>\nCSR Register
CSR Register
CSR Register <\/td>\n<\/tr>\n
108<\/td>\nCSR Register
CSR Register
CSR Register 9 and CSR Registers ICh to 1Fh <\/td>\n<\/tr>\n
109<\/td>\nCSR Registers Ah to Fh
CSR Registers 20h to 3Fh
8.15 CSR Registers 70h to 81h <\/td>\n<\/tr>\n
110<\/td>\nCSR Registers AOh to AFh BOh to BFh and COh to CFh
CSR Registers 8000 OOOOh to BFFF FFFFh Parameter Space <\/td>\n<\/tr>\n
112<\/td>\nClearing of CSR Bits <\/td>\n<\/tr>\n
113<\/td>\nInterrupts
9 Interrupts
9.1 Interrupt Operation <\/td>\n<\/tr>\n
114<\/td>\n9.2 The Service Request Line <\/td>\n<\/tr>\n
117<\/td>\nNear- and Far-side Concept for the SI <\/td>\n<\/tr>\n
119<\/td>\n10.3 Contention for Use of an SI <\/td>\n<\/tr>\n
123<\/td>\n10.5.2 CSR#l Far-side Arbitration Level
10.5.3 CSR#8 Near-side Arbitration Level
10.5.4 CSR#9 Timer Control Register <\/td>\n<\/tr>\n
124<\/td>\n10.5.5 CSR#40h Route Table Address Register
10.5.6 CSR#4lh Route Table Data Register
10.5.7 CSR#42h Near-side Geographical Address <\/td>\n<\/tr>\n
128<\/td>\n10.7.4 Negative Responses <\/td>\n<\/tr>\n
129<\/td>\nModification of Geographical and Broadcast Addresses <\/td>\n<\/tr>\n
134<\/td>\nBlock and Pipelined Transfers <\/td>\n<\/tr>\n
140<\/td>\n13 Module Outline <\/td>\n<\/tr>\n
141<\/td>\n13.l(a Module Circuit Board Outline <\/td>\n<\/tr>\n
142<\/td>\n13.1 Module Circuit Board Details <\/td>\n<\/tr>\n
143<\/td>\nGrounding Area For Static Charge Discharge
13.2.1 Segment Connector <\/td>\n<\/tr>\n
145<\/td>\nTwo-Row Module Auxiliary Connector
Connector <\/td>\n<\/tr>\n
147<\/td>\n13.2.3 Other Connectors
Segment and Auxiliary Connector Contact Designations
13.3 Temperature Considerations and Power Dissipation
13.3.1 Die and Module Temperatures <\/td>\n<\/tr>\n
148<\/td>\nCorresponding Circuit Board Footprints <\/td>\n<\/tr>\n
149<\/td>\n13.4 Front Panel
Module Front Panel in Relation to Module Circuit Board <\/td>\n<\/tr>\n
150<\/td>\n13.7 Transients <\/td>\n<\/tr>\n
152<\/td>\n14.2(a Backplane Pin Details <\/td>\n<\/tr>\n
154<\/td>\n14.2(c Connector Guides <\/td>\n<\/tr>\n
156<\/td>\n14.2.l(a Backplane Daisy Chain Wiring (viewed from front of crate)
crate) <\/td>\n<\/tr>\n
162<\/td>\nCable Segment <\/td>\n<\/tr>\n
165<\/td>\nRequirements for Various Implementations
Requirements for Various Implementations
A.l ECL Implementation
A.l.l ECL Connections and Signal Level Details <\/td>\n<\/tr>\n
167<\/td>\nECL Timing Details
A.1.3 Retry Period
A.1.4 Response Times
A.1.5 Terminators
A.l.l Typical ECL Driver-Receiver Layout <\/td>\n<\/tr>\n
169<\/td>\nGA Logic Generating Circuit Requirements
A.1.7 Differential Die Temperatures
A.1.8 Module Distribution in Crate Segments <\/td>\n<\/tr>\n
173<\/td>\nElectrical Specification for Cable Segment
C.l
C.2 ECL Cable Segment Implementation <\/td>\n<\/tr>\n
174<\/td>\nC Cable Segment Logic States <\/td>\n<\/tr>\n
175<\/td>\nC.l(a Schematic Diagram of Cable Segment Driver
C.l(b Example of Cable Segment Driver <\/td>\n<\/tr>\n
176<\/td>\nImplementation Examples of Master Requirements
Implementation Examples of Master Requirements
Master Arbitration Circuitry
D.1
D.l Example of Arbitration Logic <\/td>\n<\/tr>\n
177<\/td>\nFASTBUS Segment Interconnect TypeS-1
FASTBUS Segment Interconnect TypeS-1
General Features of Segment Interconnect TypeS-1
E.lS-1
E.l.l Type <\/td>\n<\/tr>\n
178<\/td>\nE.1.2 Format
E.1.3 Cable Segment
E.1.4 Group Address Field
E.1.5
Route Table Implementation <\/td>\n<\/tr>\n
179<\/td>\nCSR#O ID, Status and Control
E.1.6
E.1.7 NTA Register
Front Panel Features <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard for FASTBUS Modular High-Speed Data Acquisition and Control System<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n1986<\/td>\n217<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":396052,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-396048","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/396048","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/396052"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=396048"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=396048"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=396048"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}