{"id":396340,"date":"2024-10-20T04:24:12","date_gmt":"2024-10-20T04:24:12","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1296-1987\/"},"modified":"2024-10-26T08:11:25","modified_gmt":"2024-10-26T08:11:25","slug":"ieee-1296-1987","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1296-1987\/","title":{"rendered":"IEEE 1296-1987"},"content":{"rendered":"<p>New IEEE Standard &#8211; Inactive-Withdrawn. This standard describes a high-performance backplane bus intended for use in multiple processor systems. The bus incorporates synchronous, 32-bit multiplexed addreddata, with error detection and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective high performance VLSI for the bus interface. The standard defines memory, I\/O, message, and geographic address spaces. The memory space supports single and block transfers. The message space defines a high-level protocol for transferring blocks of data (messages) as multiple packets of data (small data bursts; e.g., 32 bytes in one microsecond) over the bus. This provides a highperformance (e.g., 32 megabytes\/second) interprocessor communication transfers among many different processors on the bus. Error detection and retry is provided for messages. This message passing design also allows a VLSI implementation, such that virtually all modules on the bus will utilize the bus at its highest performance &#8211; 32 to 40 megabytes\/second. The standard provides geographic addressing for ease of configurability, initialization, and diagnostics.<\/p>\n","protected":false},"excerpt":{"rendered":"<p><b>IEEE Standard for a High-Performance Synchronous 32-Bit Bus: MULTIBUS II<\/b><\/p>\n<table class=\"shortdes-table\" style=\"width: 100%\" border=\"0\" cellspacing=\"0\" cellpadding=\"0\">\n<tbody>\n<tr>\n<td>Published By<\/td>\n<td>Publication Date<\/td>\n<td>Number of Pages<\/td>\n<\/tr>\n<tr>\n<td><a href=\"https:\/\/pdfstandards.shop\/product-category\/publishers\/ieee\/\"><b>IEEE<\/b><\/a><\/td>\n<td>1987<\/td>\n<td>260<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":396347,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-396340","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/396340","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/396347"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=396340"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=396340"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=396340"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}