{"id":397714,"date":"2024-10-20T04:31:51","date_gmt":"2024-10-20T04:31:51","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1800-2012\/"},"modified":"2024-10-26T08:19:58","modified_gmt":"2024-10-26T08:19:58","slug":"ieee-1800-2012","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1800-2012\/","title":{"rendered":"IEEE 1800-2012"},"content":{"rendered":"

Revision Standard – Superseded. The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing test benches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages. (Thanks to our sponsor, the PDF of this standard is provided to the public no charge. Visit GETIEEE program located at https:\/\/ieeexplore.ieee.org\/browse\/standards\/get-program\/page for details.)<\/p>\n

PDF Catalog<\/h4>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
1<\/td>\nIEEE Std 1800-2012 Front cover
\n <\/td>\n<\/tr>\n
3<\/td>\nTitle page <\/td>\n<\/tr>\n
6<\/td>\nNotice to users
\n
Laws and regulations
\n
Copyrights
\n
Updating of IEEE documents
\n
Errata
\n
Patents
\n <\/td>\n<\/tr>\n
8<\/td>\nParticipants
\n <\/td>\n<\/tr>\n
11<\/td>\nIntroduction
\n <\/td>\n<\/tr>\n
13<\/td>\nContents
\n <\/td>\n<\/tr>\n
28<\/td>\nList of figures
\n <\/td>\n<\/tr>\n
31<\/td>\nList of tables
\n <\/td>\n<\/tr>\n
35<\/td>\nList of syntax excerpts
\n <\/td>\n<\/tr>\n
41<\/td>\nPart One: Design and Verification Constructs
\n <\/td>\n<\/tr>\n
42<\/td>\nImportant notice
\n
1. Overview
1.1 Scope
1.2 Purpose
1.3 Content summary <\/td>\n<\/tr>\n
43<\/td>\n1.4 Special terms
1.5 Conventions used in this standard <\/td>\n<\/tr>\n
44<\/td>\n1.6 Syntactic description <\/td>\n<\/tr>\n
45<\/td>\n1.7 Use of color in this standard
1.8 Contents of this standard <\/td>\n<\/tr>\n
48<\/td>\n1.9 Deprecated clauses
1.10 Examples
1.11 Prerequisites <\/td>\n<\/tr>\n
49<\/td>\n2. Normative references <\/td>\n<\/tr>\n
51<\/td>\n3. Design and verification building blocks
3.1 General
3.2 Design elements
3.3 Modules <\/td>\n<\/tr>\n
52<\/td>\n3.4 Programs <\/td>\n<\/tr>\n
53<\/td>\n3.5 Interfaces <\/td>\n<\/tr>\n
54<\/td>\n3.6 Checkers
3.7 Primitives
3.8 Subroutines
3.9 Packages <\/td>\n<\/tr>\n
55<\/td>\n3.10 Configurations
3.11 Overview of hierarchy <\/td>\n<\/tr>\n
56<\/td>\n3.12 Compilation and elaboration <\/td>\n<\/tr>\n
58<\/td>\n3.13 Name spaces <\/td>\n<\/tr>\n
59<\/td>\n3.14 Simulation time units and precision <\/td>\n<\/tr>\n
63<\/td>\n4. Scheduling semantics
4.1 General
4.2 Execution of a hardware model and its verification environment
4.3 Event simulation <\/td>\n<\/tr>\n
64<\/td>\n4.4 Stratified event scheduler <\/td>\n<\/tr>\n
69<\/td>\n4.5 SystemVerilog simulation reference algorithm
4.6 Determinism <\/td>\n<\/tr>\n
70<\/td>\n4.7 Nondeterminism
4.8 Race conditions
4.9 Scheduling implication of assignments <\/td>\n<\/tr>\n
72<\/td>\n4.10 PLI callback control points <\/td>\n<\/tr>\n
73<\/td>\n5. Lexical conventions
5.1 General
5.2 Lexical tokens
5.3 White space
5.4 Comments
5.5 Operators <\/td>\n<\/tr>\n
74<\/td>\n5.6 Identifiers, keywords, and system names <\/td>\n<\/tr>\n
75<\/td>\n5.7 Numbers <\/td>\n<\/tr>\n
80<\/td>\n5.8 Time literals
5.9 String literals <\/td>\n<\/tr>\n
82<\/td>\n5.10 Structure literals <\/td>\n<\/tr>\n
83<\/td>\n5.11 Array literals
5.12 Attributes <\/td>\n<\/tr>\n
85<\/td>\n5.13 Built-in methods <\/td>\n<\/tr>\n
87<\/td>\n6. Data types
6.1 General
6.2 Data types and data objects
6.3 Value set <\/td>\n<\/tr>\n
88<\/td>\n6.4 Singular and aggregate types <\/td>\n<\/tr>\n
89<\/td>\n6.5 Nets and variables <\/td>\n<\/tr>\n
90<\/td>\n6.6 Net types <\/td>\n<\/tr>\n
101<\/td>\n6.7 Net declarations <\/td>\n<\/tr>\n
104<\/td>\n6.8 Variable declarations <\/td>\n<\/tr>\n
106<\/td>\n6.9 Vector declarations <\/td>\n<\/tr>\n
107<\/td>\n6.10 Implicit declarations <\/td>\n<\/tr>\n
108<\/td>\n6.11 Integer data types <\/td>\n<\/tr>\n
109<\/td>\n6.12 Real, shortreal, and realtime data types
6.13 Void data type
6.14 Chandle data type <\/td>\n<\/tr>\n
110<\/td>\n6.15 Class
6.16 String data type <\/td>\n<\/tr>\n
115<\/td>\n6.17 Event data type <\/td>\n<\/tr>\n
116<\/td>\n6.18 User-defined types <\/td>\n<\/tr>\n
117<\/td>\n6.19 Enumerations <\/td>\n<\/tr>\n
123<\/td>\n6.20 Constants <\/td>\n<\/tr>\n
130<\/td>\n6.21 Scope and lifetime <\/td>\n<\/tr>\n
132<\/td>\n6.22 Type compatibility <\/td>\n<\/tr>\n
135<\/td>\n6.23 Type operator <\/td>\n<\/tr>\n
136<\/td>\n6.24 Casting <\/td>\n<\/tr>\n
141<\/td>\n6.25 Parameterized data types <\/td>\n<\/tr>\n
143<\/td>\n7. Aggregate data types
7.1 General
7.2 Structures <\/td>\n<\/tr>\n
145<\/td>\n7.3 Unions <\/td>\n<\/tr>\n
149<\/td>\n7.4 Packed and unpacked arrays <\/td>\n<\/tr>\n
153<\/td>\n7.5 Dynamic arrays <\/td>\n<\/tr>\n
156<\/td>\n7.6 Array assignments <\/td>\n<\/tr>\n
157<\/td>\n7.7 Arrays as arguments to subroutines <\/td>\n<\/tr>\n
158<\/td>\n7.8 Associative arrays <\/td>\n<\/tr>\n
161<\/td>\n7.9 Associative array methods <\/td>\n<\/tr>\n
164<\/td>\n7.10 Queues <\/td>\n<\/tr>\n
169<\/td>\n7.11 Array querying functions
7.12 Array manipulation methods <\/td>\n<\/tr>\n
174<\/td>\n8. Classes
8.1 General
8.2 Overview <\/td>\n<\/tr>\n
175<\/td>\n8.3 Syntax <\/td>\n<\/tr>\n
176<\/td>\n8.4 Objects (class instance) <\/td>\n<\/tr>\n
177<\/td>\n8.5 Object properties and object parameter data <\/td>\n<\/tr>\n
178<\/td>\n8.6 Object methods
8.7 Constructors <\/td>\n<\/tr>\n
180<\/td>\n8.8 Typed constructor calls <\/td>\n<\/tr>\n
181<\/td>\n8.9 Static class properties
8.10 Static methods
8.11 This <\/td>\n<\/tr>\n
182<\/td>\n8.12 Assignment, renaming, and copying <\/td>\n<\/tr>\n
184<\/td>\n8.13 Inheritance and subclasses
8.14 Overridden members <\/td>\n<\/tr>\n
185<\/td>\n8.15 Super <\/td>\n<\/tr>\n
186<\/td>\n8.16 Casting
8.17 Chaining constructors <\/td>\n<\/tr>\n
187<\/td>\n8.18 Data hiding and encapsulation
8.19 Constant class properties <\/td>\n<\/tr>\n
188<\/td>\n8.20 Virtual methods <\/td>\n<\/tr>\n
190<\/td>\n8.21 Abstract classes and pure virtual methods
8.22 Polymorphism: dynamic method lookup <\/td>\n<\/tr>\n
191<\/td>\n8.23 Class scope resolution operator :: <\/td>\n<\/tr>\n
193<\/td>\n8.24 Out-of-block declarations <\/td>\n<\/tr>\n
194<\/td>\n8.25 Parameterized classes <\/td>\n<\/tr>\n
197<\/td>\n8.26 Interface classes <\/td>\n<\/tr>\n
207<\/td>\n8.27 Typedef class
8.28 Classes and structures <\/td>\n<\/tr>\n
208<\/td>\n8.29 Memory management <\/td>\n<\/tr>\n
209<\/td>\n9. Processes
9.1 General
9.2 Structured procedures <\/td>\n<\/tr>\n
213<\/td>\n9.3 Block statements <\/td>\n<\/tr>\n
219<\/td>\n9.4 Procedural timing controls <\/td>\n<\/tr>\n
229<\/td>\n9.5 Process execution threads
9.6 Process control <\/td>\n<\/tr>\n
233<\/td>\n9.7 Fine-grain process control <\/td>\n<\/tr>\n
236<\/td>\n10. Assignment statements
10.1 General
10.2 Overview <\/td>\n<\/tr>\n
237<\/td>\n10.3 Continuous assignments <\/td>\n<\/tr>\n
240<\/td>\n10.4 Procedural assignments <\/td>\n<\/tr>\n
245<\/td>\n10.5 Variable declaration assignment (variable initialization)
10.6 Procedural continuous assignments <\/td>\n<\/tr>\n
247<\/td>\n10.7 Assignment extension and truncation <\/td>\n<\/tr>\n
248<\/td>\n10.8 Assignment-like contexts <\/td>\n<\/tr>\n
249<\/td>\n10.9 Assignment patterns <\/td>\n<\/tr>\n
253<\/td>\n10.10 Unpacked array concatenation <\/td>\n<\/tr>\n
256<\/td>\n10.11 Net aliasing <\/td>\n<\/tr>\n
258<\/td>\n11. Operators and expressions
11.1 General
11.2 Overview <\/td>\n<\/tr>\n
259<\/td>\n11.3 Operators <\/td>\n<\/tr>\n
263<\/td>\n11.4 Operator descriptions <\/td>\n<\/tr>\n
283<\/td>\n11.5 Operands <\/td>\n<\/tr>\n
287<\/td>\n11.6 Expression bit lengths <\/td>\n<\/tr>\n
289<\/td>\n11.7 Signed expressions <\/td>\n<\/tr>\n
290<\/td>\n11.8 Expression evaluation rules <\/td>\n<\/tr>\n
291<\/td>\n11.9 Tagged union expressions and member access <\/td>\n<\/tr>\n
293<\/td>\n11.10 String literal expressions <\/td>\n<\/tr>\n
294<\/td>\n11.11 Operator overloading <\/td>\n<\/tr>\n
296<\/td>\n11.12 Minimum, typical, and maximum delay expressions <\/td>\n<\/tr>\n
298<\/td>\n11.13 Let construct <\/td>\n<\/tr>\n
304<\/td>\n12. Procedural programming statements
12.1 General
12.2 Overview
12.3 Syntax <\/td>\n<\/tr>\n
305<\/td>\n12.4 Conditional if\u2013else statement <\/td>\n<\/tr>\n
310<\/td>\n12.5 Case statement <\/td>\n<\/tr>\n
315<\/td>\n12.6 Pattern matching conditional statements <\/td>\n<\/tr>\n
319<\/td>\n12.7 Loop statements <\/td>\n<\/tr>\n
323<\/td>\n12.8 Jump statements <\/td>\n<\/tr>\n
325<\/td>\n13. Tasks and functions (subroutines)
13.1 General
13.2 Overview
13.3 Tasks <\/td>\n<\/tr>\n
329<\/td>\n13.4 Functions <\/td>\n<\/tr>\n
335<\/td>\n13.5 Subroutine calls and argument passing <\/td>\n<\/tr>\n
340<\/td>\n13.6 Import and export functions
13.7 Task and function names
13.8 Parameterized tasks and functions <\/td>\n<\/tr>\n
342<\/td>\n14. Clocking blocks
14.1 General
14.2 Overview
14.3 Clocking block declaration <\/td>\n<\/tr>\n
344<\/td>\n14.4 Input and output skews <\/td>\n<\/tr>\n
345<\/td>\n14.5 Hierarchical expressions <\/td>\n<\/tr>\n
346<\/td>\n14.6 Signals in multiple clocking blocks
14.7 Clocking block scope and lifetime
14.8 Multiple clocking blocks example <\/td>\n<\/tr>\n
347<\/td>\n14.9 Interfaces and clocking blocks <\/td>\n<\/tr>\n
348<\/td>\n14.10 Clocking block events
14.11 Cycle delay: ## <\/td>\n<\/tr>\n
349<\/td>\n14.12 Default clocking <\/td>\n<\/tr>\n
350<\/td>\n14.13 Input sampling <\/td>\n<\/tr>\n
351<\/td>\n14.14 Global clocking <\/td>\n<\/tr>\n
355<\/td>\n14.15 Synchronous events
14.16 Synchronous drives <\/td>\n<\/tr>\n
360<\/td>\n15. Interprocess synchronization and communication
15.1 General
15.2 Overview
15.3 Semaphores <\/td>\n<\/tr>\n
362<\/td>\n15.4 Mailboxes <\/td>\n<\/tr>\n
365<\/td>\n15.5 Named events <\/td>\n<\/tr>\n
370<\/td>\n16. Assertions
16.1 General
16.2 Overview
16.3 Immediate assertions <\/td>\n<\/tr>\n
373<\/td>\n16.4 Deferred assertions <\/td>\n<\/tr>\n
380<\/td>\n16.5 Concurrent assertions overview <\/td>\n<\/tr>\n
383<\/td>\n16.6 Boolean expressions <\/td>\n<\/tr>\n
384<\/td>\n16.7 Sequences <\/td>\n<\/tr>\n
388<\/td>\n16.8 Declaring sequences <\/td>\n<\/tr>\n
396<\/td>\n16.9 Sequence operations <\/td>\n<\/tr>\n
418<\/td>\n16.10 Local variables <\/td>\n<\/tr>\n
424<\/td>\n16.11 Calling subroutines on match of a sequence <\/td>\n<\/tr>\n
425<\/td>\n16.12 Declaring properties <\/td>\n<\/tr>\n
451<\/td>\n16.13 Multiclock support <\/td>\n<\/tr>\n
461<\/td>\n16.14 Concurrent assertions <\/td>\n<\/tr>\n
478<\/td>\n16.15 Disable iff resolution <\/td>\n<\/tr>\n
480<\/td>\n16.16 Clock resolution <\/td>\n<\/tr>\n
485<\/td>\n16.17 Expect statement <\/td>\n<\/tr>\n
486<\/td>\n16.18 Clocking blocks and concurrent assertions <\/td>\n<\/tr>\n
488<\/td>\n17. Checkers
17.1 Overview
17.2 Checker declaration <\/td>\n<\/tr>\n
491<\/td>\n17.3 Checker instantiation <\/td>\n<\/tr>\n
494<\/td>\n17.4 Context inference <\/td>\n<\/tr>\n
495<\/td>\n17.5 Checker procedures <\/td>\n<\/tr>\n
497<\/td>\n17.6 Covergroups in checkers <\/td>\n<\/tr>\n
498<\/td>\n17.7 Checker variables <\/td>\n<\/tr>\n
504<\/td>\n17.8 Functions in checkers
17.9 Complex checker example <\/td>\n<\/tr>\n
507<\/td>\n18. Constrained random value generation
18.1 General
18.2 Overview
18.3 Concepts and usage <\/td>\n<\/tr>\n
510<\/td>\n18.4 Random variables <\/td>\n<\/tr>\n
512<\/td>\n18.5 Constraint blocks <\/td>\n<\/tr>\n
532<\/td>\n18.6 Randomization methods <\/td>\n<\/tr>\n
533<\/td>\n18.7 In-line constraints\u2014randomize() with <\/td>\n<\/tr>\n
536<\/td>\n18.8 Disabling random variables with rand_mode() <\/td>\n<\/tr>\n
537<\/td>\n18.9 Controlling constraints with constraint_mode() <\/td>\n<\/tr>\n
538<\/td>\n18.10 Dynamic constraint modification <\/td>\n<\/tr>\n
539<\/td>\n18.11 In-line random variable control <\/td>\n<\/tr>\n
540<\/td>\n18.12 Randomization of scope variables\u2014std::randomize() <\/td>\n<\/tr>\n
541<\/td>\n18.13 Random number system functions and methods <\/td>\n<\/tr>\n
543<\/td>\n18.14 Random stability <\/td>\n<\/tr>\n
545<\/td>\n18.15 Manually seeding randomize <\/td>\n<\/tr>\n
546<\/td>\n18.16 Random weighted case\u2014randcase <\/td>\n<\/tr>\n
547<\/td>\n18.17 Random sequence generation\u2014randsequence <\/td>\n<\/tr>\n
557<\/td>\n19. Functional coverage
19.1 General
19.2 Overview <\/td>\n<\/tr>\n
558<\/td>\n19.3 Defining the coverage model: covergroup <\/td>\n<\/tr>\n
560<\/td>\n19.4 Using covergroup in classes <\/td>\n<\/tr>\n
562<\/td>\n19.5 Defining coverage points <\/td>\n<\/tr>\n
573<\/td>\n19.6 Defining cross coverage <\/td>\n<\/tr>\n
582<\/td>\n19.7 Specifying coverage options <\/td>\n<\/tr>\n
587<\/td>\n19.8 Predefined coverage methods <\/td>\n<\/tr>\n
589<\/td>\n19.9 Predefined coverage system tasks and system functions
19.10 Organization of option and type_option members <\/td>\n<\/tr>\n
590<\/td>\n19.11 Coverage computation <\/td>\n<\/tr>\n
595<\/td>\n20. Utility system tasks and system functions
20.1 General <\/td>\n<\/tr>\n
596<\/td>\n20.2 Simulation control system tasks
20.3 Simulation time system functions <\/td>\n<\/tr>\n
598<\/td>\n20.4 Timescale system tasks <\/td>\n<\/tr>\n
601<\/td>\n20.5 Conversion functions <\/td>\n<\/tr>\n
602<\/td>\n20.6 Data query functions <\/td>\n<\/tr>\n
604<\/td>\n20.7 Array querying functions <\/td>\n<\/tr>\n
606<\/td>\n20.8 Math functions <\/td>\n<\/tr>\n
608<\/td>\n20.9 Bit vector system functions <\/td>\n<\/tr>\n
609<\/td>\n20.10 Severity tasks <\/td>\n<\/tr>\n
610<\/td>\n20.11 Elaboration system tasks <\/td>\n<\/tr>\n
611<\/td>\n20.12 Assertion control system tasks <\/td>\n<\/tr>\n
618<\/td>\n20.13 Sampled value system functions <\/td>\n<\/tr>\n
619<\/td>\n20.14 Coverage system functions
20.15 Probabilistic distribution functions <\/td>\n<\/tr>\n
621<\/td>\n20.16 Stochastic analysis tasks and functions <\/td>\n<\/tr>\n
623<\/td>\n20.17 Programmable logic array modeling system tasks <\/td>\n<\/tr>\n
626<\/td>\n20.18 Miscellaneous tasks and functions <\/td>\n<\/tr>\n
628<\/td>\n21. Input\/output system tasks and system functions
21.1 General
21.2 Display system tasks <\/td>\n<\/tr>\n
639<\/td>\n21.3 File input\/output system tasks and system functions <\/td>\n<\/tr>\n
649<\/td>\n21.4 Loading memory array data from a file <\/td>\n<\/tr>\n
653<\/td>\n21.5 Writing memory array data to a file <\/td>\n<\/tr>\n
654<\/td>\n21.6 Command line input <\/td>\n<\/tr>\n
657<\/td>\n21.7 Value change dump (VCD) files <\/td>\n<\/tr>\n
678<\/td>\n22. Compiler directives
22.1 General
22.2 Overview
22.3 `resetall <\/td>\n<\/tr>\n
679<\/td>\n22.4 `include
22.5 `define, `undef, and `undefineall <\/td>\n<\/tr>\n
685<\/td>\n22.6 `ifdef, `else, `elsif, `endif, `ifndef <\/td>\n<\/tr>\n
688<\/td>\n22.7 `timescale <\/td>\n<\/tr>\n
689<\/td>\n22.8 `default_nettype <\/td>\n<\/tr>\n
690<\/td>\n22.9 `unconnected_drive and `nounconnected_drive
22.10 `celldefine and `endcelldefine
22.11 `pragma <\/td>\n<\/tr>\n
691<\/td>\n22.12 `line <\/td>\n<\/tr>\n
692<\/td>\n22.13 `__FILE__ and `__LINE__ <\/td>\n<\/tr>\n
693<\/td>\n22.14 `begin_keywords, `end_keywords <\/td>\n<\/tr>\n
699<\/td>\nPart Two: Hierarchy Constructs
\n <\/td>\n<\/tr>\n
700<\/td>\n23. Modules and hierarchy
23.1 General
23.2 Module definitions <\/td>\n<\/tr>\n
712<\/td>\n23.3 Module instances (hierarchy) <\/td>\n<\/tr>\n
723<\/td>\n23.4 Nested modules <\/td>\n<\/tr>\n
724<\/td>\n23.5 Extern modules <\/td>\n<\/tr>\n
725<\/td>\n23.6 Hierarchical names <\/td>\n<\/tr>\n
728<\/td>\n23.7 Member selects and hierarchical names <\/td>\n<\/tr>\n
729<\/td>\n23.8 Upwards name referencing <\/td>\n<\/tr>\n
732<\/td>\n23.9 Scope rules <\/td>\n<\/tr>\n
734<\/td>\n23.10 Overriding module parameters <\/td>\n<\/tr>\n
741<\/td>\n23.11 Binding auxiliary code to scopes or instances <\/td>\n<\/tr>\n
745<\/td>\n24. Programs
24.1 General
24.2 Overview
24.3 The program construct <\/td>\n<\/tr>\n
749<\/td>\n24.4 Eliminating testbench races
24.5 Blocking tasks in cycle\/event mode <\/td>\n<\/tr>\n
750<\/td>\n24.6 Programwide space and anonymous programs
24.7 Program control tasks <\/td>\n<\/tr>\n
751<\/td>\n25. Interfaces
25.1 General
25.2 Overview <\/td>\n<\/tr>\n
752<\/td>\n25.3 Interface syntax <\/td>\n<\/tr>\n
756<\/td>\n25.4 Ports in interfaces <\/td>\n<\/tr>\n
757<\/td>\n25.5 Modports <\/td>\n<\/tr>\n
763<\/td>\n25.6 Interfaces and specify blocks <\/td>\n<\/tr>\n
764<\/td>\n25.7 Tasks and functions in interfaces <\/td>\n<\/tr>\n
770<\/td>\n25.8 Parameterized interfaces <\/td>\n<\/tr>\n
772<\/td>\n25.9 Virtual interfaces <\/td>\n<\/tr>\n
777<\/td>\n25.10 Access to interface objects <\/td>\n<\/tr>\n
778<\/td>\n26. Packages
26.1 General
26.2 Package declarations <\/td>\n<\/tr>\n
779<\/td>\n26.3 Referencing data in packages <\/td>\n<\/tr>\n
783<\/td>\n26.4 Using packages in module headers <\/td>\n<\/tr>\n
784<\/td>\n26.5 Search order rules <\/td>\n<\/tr>\n
786<\/td>\n26.6 Exporting imported names from packages <\/td>\n<\/tr>\n
787<\/td>\n26.7 The std built-in package <\/td>\n<\/tr>\n
789<\/td>\n27. Generate constructs
27.1 General
27.2 Overview
27.3 Generate construct syntax <\/td>\n<\/tr>\n
791<\/td>\n27.4 Loop generate constructs <\/td>\n<\/tr>\n
795<\/td>\n27.5 Conditional generate constructs <\/td>\n<\/tr>\n
798<\/td>\n27.6 External names for unnamed generate blocks <\/td>\n<\/tr>\n
800<\/td>\n28. Gate-level and switch-level modeling
28.1 General
28.2 Overview
28.3 Gate and switch declaration syntax <\/td>\n<\/tr>\n
806<\/td>\n28.4 and, nand, nor, or, xor, and xnor gates <\/td>\n<\/tr>\n
807<\/td>\n28.5 buf and not gates <\/td>\n<\/tr>\n
808<\/td>\n28.6 bufif1, bufif0, notif1, and notif0 gates <\/td>\n<\/tr>\n
809<\/td>\n28.7 MOS switches <\/td>\n<\/tr>\n
810<\/td>\n28.8 Bidirectional pass switches <\/td>\n<\/tr>\n
811<\/td>\n28.9 CMOS switches <\/td>\n<\/tr>\n
812<\/td>\n28.10 pullup and pulldown sources
28.11 Logic strength modeling <\/td>\n<\/tr>\n
814<\/td>\n28.12 Strengths and values of combined signals <\/td>\n<\/tr>\n
826<\/td>\n28.13 Strength reduction by nonresistive devices
28.14 Strength reduction by resistive devices
28.15 Strengths of net types <\/td>\n<\/tr>\n
827<\/td>\n28.16 Gate and net delays <\/td>\n<\/tr>\n
831<\/td>\n29. User-defined primitives
29.1 General
29.2 Overview
29.3 UDP definition <\/td>\n<\/tr>\n
835<\/td>\n29.4 Combinational UDPs <\/td>\n<\/tr>\n
836<\/td>\n29.5 Level-sensitive sequential UDPs
29.6 Edge-sensitive sequential UDPs <\/td>\n<\/tr>\n
837<\/td>\n29.7 Sequential UDP initialization <\/td>\n<\/tr>\n
839<\/td>\n29.8 UDP instances <\/td>\n<\/tr>\n
840<\/td>\n29.9 Mixing level-sensitive and edge-sensitive descriptions <\/td>\n<\/tr>\n
841<\/td>\n29.10 Level-sensitive dominance <\/td>\n<\/tr>\n
842<\/td>\n30. Specify blocks
30.1 General
30.2 Overview
30.3 Specify block declaration <\/td>\n<\/tr>\n
843<\/td>\n30.4 Module path declarations <\/td>\n<\/tr>\n
852<\/td>\n30.5 Assigning delays to module paths <\/td>\n<\/tr>\n
856<\/td>\n30.6 Mixing module path delays and distributed delays <\/td>\n<\/tr>\n
857<\/td>\n30.7 Detailed control of pulse filtering behavior <\/td>\n<\/tr>\n
866<\/td>\n31. Timing checks
31.1 General
31.2 Overview <\/td>\n<\/tr>\n
869<\/td>\n31.3 Timing checks using a stability window <\/td>\n<\/tr>\n
876<\/td>\n31.4 Timing checks for clock and control signals <\/td>\n<\/tr>\n
885<\/td>\n31.5 Edge-control specifiers <\/td>\n<\/tr>\n
886<\/td>\n31.6 Notifiers: user-defined responses to timing violations <\/td>\n<\/tr>\n
888<\/td>\n31.7 Enabling timing checks with conditioned events <\/td>\n<\/tr>\n
889<\/td>\n31.8 Vector signals in timing checks <\/td>\n<\/tr>\n
890<\/td>\n31.9 Negative timing checks <\/td>\n<\/tr>\n
895<\/td>\n32. Backannotation using the standard delay format
32.1 General
32.2 Overview
32.3 The SDF annotator
32.4 Mapping of SDF constructs to SystemVerilog <\/td>\n<\/tr>\n
900<\/td>\n32.5 Multiple annotations <\/td>\n<\/tr>\n
901<\/td>\n32.6 Multiple SDF files
32.7 Pulse limit annotation <\/td>\n<\/tr>\n
902<\/td>\n32.8 SDF to SystemVerilog delay value mapping <\/td>\n<\/tr>\n
903<\/td>\n32.9 Loading timing data from an SDF file <\/td>\n<\/tr>\n
905<\/td>\n33. Configuring the contents of a design
33.1 General
33.2 Overview <\/td>\n<\/tr>\n
906<\/td>\n33.3 Libraries <\/td>\n<\/tr>\n
908<\/td>\n33.4 Configurations <\/td>\n<\/tr>\n
914<\/td>\n33.5 Using libraries and configs <\/td>\n<\/tr>\n
915<\/td>\n33.6 Configuration examples <\/td>\n<\/tr>\n
917<\/td>\n33.7 Displaying library binding information
33.8 Library mapping examples <\/td>\n<\/tr>\n
920<\/td>\n34. Protected envelopes
34.1 General
34.2 Overview
34.3 Processing protected envelopes <\/td>\n<\/tr>\n
922<\/td>\n34.4 Protect pragma directives <\/td>\n<\/tr>\n
924<\/td>\n34.5 Protect pragma keywords <\/td>\n<\/tr>\n
940<\/td>\nPart Three: Application Programming Interfaces
\n <\/td>\n<\/tr>\n
941<\/td>\n35. Direct programming interface
35.1 General
35.2 Overview <\/td>\n<\/tr>\n
942<\/td>\n35.3 Two layers of DPI <\/td>\n<\/tr>\n
943<\/td>\n35.4 Global name space of imported and exported functions <\/td>\n<\/tr>\n
944<\/td>\n35.5 Imported tasks and functions <\/td>\n<\/tr>\n
951<\/td>\n35.6 Calling imported functions <\/td>\n<\/tr>\n
953<\/td>\n35.7 Exported functions <\/td>\n<\/tr>\n
954<\/td>\n35.8 Exported tasks
35.9 Disabling DPI tasks and functions <\/td>\n<\/tr>\n
956<\/td>\n36. Programming language interface (PLI\/VPI) overview
36.1 General
36.2 PLI purpose and history <\/td>\n<\/tr>\n
957<\/td>\n36.3 User-defined system task and system function names <\/td>\n<\/tr>\n
958<\/td>\n36.4 User-defined system task and system function arguments
36.5 User-defined system task and system function types
36.6 User-supplied PLI applications
36.7 PLI include files
36.8 VPI sizetf, compiletf, and calltf routines <\/td>\n<\/tr>\n
959<\/td>\n36.9 PLI mechanism <\/td>\n<\/tr>\n
961<\/td>\n36.10 VPI access to SystemVerilog objects and simulation objects <\/td>\n<\/tr>\n
962<\/td>\n36.11 List of VPI routines by functional category <\/td>\n<\/tr>\n
964<\/td>\n36.12 VPI backwards compatibility features and limitations <\/td>\n<\/tr>\n
969<\/td>\n37. VPI object model diagrams
37.1 General
37.2 VPI Handles <\/td>\n<\/tr>\n
970<\/td>\n37.3 VPI object classifications <\/td>\n<\/tr>\n
976<\/td>\n37.4 Key to data model diagrams <\/td>\n<\/tr>\n
979<\/td>\n37.5 Module <\/td>\n<\/tr>\n
980<\/td>\n37.6 Interface
37.7 Modport
37.8 Interface task or function declaration <\/td>\n<\/tr>\n
981<\/td>\n37.9 Program <\/td>\n<\/tr>\n
982<\/td>\n37.10 Instance <\/td>\n<\/tr>\n
984<\/td>\n37.11 Instance arrays <\/td>\n<\/tr>\n
985<\/td>\n37.12 Scope <\/td>\n<\/tr>\n
986<\/td>\n37.13 IO declaration <\/td>\n<\/tr>\n
987<\/td>\n37.14 Ports <\/td>\n<\/tr>\n
988<\/td>\n37.15 Reference objects <\/td>\n<\/tr>\n
990<\/td>\n37.16 Nets <\/td>\n<\/tr>\n
994<\/td>\n37.17 Variables <\/td>\n<\/tr>\n
997<\/td>\n37.18 Packed array variables <\/td>\n<\/tr>\n
998<\/td>\n37.19 Variable select <\/td>\n<\/tr>\n
999<\/td>\n37.20 Memory
37.21 Variable drivers and loads <\/td>\n<\/tr>\n
1000<\/td>\n37.22 Object Range <\/td>\n<\/tr>\n
1001<\/td>\n37.23 Typespec <\/td>\n<\/tr>\n
1003<\/td>\n37.24 Structures and unions <\/td>\n<\/tr>\n
1004<\/td>\n37.25 Named events <\/td>\n<\/tr>\n
1005<\/td>\n37.26 Parameter, spec param, def param, param assign <\/td>\n<\/tr>\n
1006<\/td>\n37.27 Virtual interface <\/td>\n<\/tr>\n
1008<\/td>\n37.28 Interface typespec <\/td>\n<\/tr>\n
1009<\/td>\n37.29 Class definition <\/td>\n<\/tr>\n
1010<\/td>\n37.30 Class typespec <\/td>\n<\/tr>\n
1012<\/td>\n37.31 Class variables and class objects <\/td>\n<\/tr>\n
1014<\/td>\n37.32 Constraint, constraint ordering, distribution <\/td>\n<\/tr>\n
1015<\/td>\n37.33 Primitive, prim term <\/td>\n<\/tr>\n
1016<\/td>\n37.34 UDP
37.35 Intermodule path <\/td>\n<\/tr>\n
1017<\/td>\n37.36 Constraint expression <\/td>\n<\/tr>\n
1018<\/td>\n37.37 Module path, path term <\/td>\n<\/tr>\n
1019<\/td>\n37.38 Timing check <\/td>\n<\/tr>\n
1020<\/td>\n37.39 Task and function declaration <\/td>\n<\/tr>\n
1021<\/td>\n37.40 Task and function call <\/td>\n<\/tr>\n
1023<\/td>\n37.41 Frames <\/td>\n<\/tr>\n
1024<\/td>\n37.42 Threads
37.43 Delay terminals <\/td>\n<\/tr>\n
1025<\/td>\n37.44 Net drivers and loads <\/td>\n<\/tr>\n
1026<\/td>\n37.45 Continuous assignment <\/td>\n<\/tr>\n
1027<\/td>\n37.46 Clocking block <\/td>\n<\/tr>\n
1028<\/td>\n37.47 Assertion <\/td>\n<\/tr>\n
1029<\/td>\n37.48 Concurrent assertions <\/td>\n<\/tr>\n
1030<\/td>\n37.49 Property declaration <\/td>\n<\/tr>\n
1031<\/td>\n37.50 Property specification <\/td>\n<\/tr>\n
1032<\/td>\n37.51 Sequence declaration <\/td>\n<\/tr>\n
1033<\/td>\n37.52 Sequence expression <\/td>\n<\/tr>\n
1034<\/td>\n37.53 Immediate assertions <\/td>\n<\/tr>\n
1035<\/td>\n37.54 Multiclock sequence expression
37.55 Let <\/td>\n<\/tr>\n
1036<\/td>\n37.56 Simple expressions <\/td>\n<\/tr>\n
1037<\/td>\n37.57 Expressions <\/td>\n<\/tr>\n
1040<\/td>\n37.58 Atomic statement <\/td>\n<\/tr>\n
1041<\/td>\n37.59 Dynamic prefixing <\/td>\n<\/tr>\n
1042<\/td>\n37.60 Event statement
37.61 Process <\/td>\n<\/tr>\n
1043<\/td>\n37.62 Assignment
37.63 Event control <\/td>\n<\/tr>\n
1044<\/td>\n37.64 While, repeat
37.65 Waits
37.66 Delay control <\/td>\n<\/tr>\n
1045<\/td>\n37.67 Repeat control
37.68 Forever
37.69 If, if\u2013else <\/td>\n<\/tr>\n
1046<\/td>\n37.70 Case, pattern <\/td>\n<\/tr>\n
1047<\/td>\n37.71 Expect
37.72 For
37.73 Do-while, foreach <\/td>\n<\/tr>\n
1048<\/td>\n37.74 Alias statement
37.75 Disables
37.76 Return statement <\/td>\n<\/tr>\n
1049<\/td>\n37.77 Assign statement, deassign, force, release
37.78 Callback <\/td>\n<\/tr>\n
1050<\/td>\n37.79 Time queue
37.80 Active time format <\/td>\n<\/tr>\n
1051<\/td>\n37.81 Attribute <\/td>\n<\/tr>\n
1052<\/td>\n37.82 Iterator <\/td>\n<\/tr>\n
1053<\/td>\n37.83 Generates <\/td>\n<\/tr>\n
1055<\/td>\n38. VPI routine definitions
38.1 General
38.2 vpi_chk_error() <\/td>\n<\/tr>\n
1056<\/td>\n38.3 vpi_compare_objects() <\/td>\n<\/tr>\n
1058<\/td>\n38.4 vpi_control() <\/td>\n<\/tr>\n
1059<\/td>\n38.5 vpi_flush()
38.6 vpi_get() <\/td>\n<\/tr>\n
1060<\/td>\n38.7 vpi_get64()
38.8 vpi_get_cb_info() <\/td>\n<\/tr>\n
1061<\/td>\n38.9 vpi_get_data() <\/td>\n<\/tr>\n
1062<\/td>\n38.10 vpi_get_delays() <\/td>\n<\/tr>\n
1064<\/td>\n38.11 vpi_get_str() <\/td>\n<\/tr>\n
1065<\/td>\n38.12 vpi_get_systf_info() <\/td>\n<\/tr>\n
1066<\/td>\n38.13 vpi_get_time() <\/td>\n<\/tr>\n
1067<\/td>\n38.14 vpi_get_userdata()
38.15 vpi_get_value() <\/td>\n<\/tr>\n
1073<\/td>\n38.16 vpi_get_value_array() <\/td>\n<\/tr>\n
1077<\/td>\n38.17 vpi_get_vlog_info() <\/td>\n<\/tr>\n
1078<\/td>\n38.18 vpi_handle() <\/td>\n<\/tr>\n
1079<\/td>\n38.19 vpi_handle_by_index()
38.20 vpi_handle_by_multi_index() <\/td>\n<\/tr>\n
1080<\/td>\n38.21 vpi_handle_by_name() <\/td>\n<\/tr>\n
1081<\/td>\n38.22 vpi_handle_multi()
38.23 vpi_iterate() <\/td>\n<\/tr>\n
1082<\/td>\n38.24 vpi_mcd_close() <\/td>\n<\/tr>\n
1083<\/td>\n38.25 vpi_mcd_flush()
38.26 vpi_mcd_name() <\/td>\n<\/tr>\n
1084<\/td>\n38.27 vpi_mcd_open() <\/td>\n<\/tr>\n
1085<\/td>\n38.28 vpi_mcd_printf() <\/td>\n<\/tr>\n
1086<\/td>\n38.29 vpi_mcd_vprintf()
38.30 vpi_printf() <\/td>\n<\/tr>\n
1087<\/td>\n38.31 vpi_put_data() <\/td>\n<\/tr>\n
1089<\/td>\n38.32 vpi_put_delays() <\/td>\n<\/tr>\n
1092<\/td>\n38.33 vpi_put_userdata()
38.34 vpi_put_value() <\/td>\n<\/tr>\n
1095<\/td>\n38.35 vpi_put_value_array() <\/td>\n<\/tr>\n
1099<\/td>\n38.36 vpi_register_cb() <\/td>\n<\/tr>\n
1107<\/td>\n38.37 vpi_register_systf() <\/td>\n<\/tr>\n
1111<\/td>\n38.38 vpi_release_handle()
38.39 vpi_remove_cb() <\/td>\n<\/tr>\n
1112<\/td>\n38.40 vpi_scan() <\/td>\n<\/tr>\n
1113<\/td>\n38.41 vpi_vprintf() <\/td>\n<\/tr>\n
1114<\/td>\n39. Assertion API
39.1 General
39.2 Overview
39.3 Static information <\/td>\n<\/tr>\n
1115<\/td>\n39.4 Dynamic information <\/td>\n<\/tr>\n
1119<\/td>\n39.5 Control functions <\/td>\n<\/tr>\n
1123<\/td>\n40. Code coverage control and API
40.1 General
40.2 Overview <\/td>\n<\/tr>\n
1124<\/td>\n40.3 SystemVerilog real-time coverage access <\/td>\n<\/tr>\n
1129<\/td>\n40.4 FSM recognition <\/td>\n<\/tr>\n
1132<\/td>\n40.5 VPI coverage extensions <\/td>\n<\/tr>\n
1137<\/td>\n41. Data read API <\/td>\n<\/tr>\n
1138<\/td>\nPart Four: Annexes
\n <\/td>\n<\/tr>\n
1139<\/td>\nAnnex A (normative) Formal syntax
A.1 Source text <\/td>\n<\/tr>\n
1148<\/td>\nA.2 Declarations <\/td>\n<\/tr>\n
1159<\/td>\nA.3 Primitive instances <\/td>\n<\/tr>\n
1160<\/td>\nA.4 Instantiations <\/td>\n<\/tr>\n
1162<\/td>\nA.5 UDP declaration and instantiation <\/td>\n<\/tr>\n
1163<\/td>\nA.6 Behavioral statements <\/td>\n<\/tr>\n
1170<\/td>\nA.7 Specify section <\/td>\n<\/tr>\n
1174<\/td>\nA.8 Expressions <\/td>\n<\/tr>\n
1179<\/td>\nA.9 General <\/td>\n<\/tr>\n
1182<\/td>\nA.10 Footnotes (normative) <\/td>\n<\/tr>\n
1185<\/td>\nAnnex B (normative) Keywords <\/td>\n<\/tr>\n
1187<\/td>\nAnnex C (normative) Deprecation
C.1 General
C.2 Constructs that have been deprecated <\/td>\n<\/tr>\n
1188<\/td>\nC.3 Accellera SystemVerilog 3.1a-compatible access to packed data
C.4 Constructs identified for deprecation <\/td>\n<\/tr>\n
1191<\/td>\nAnnex D (informative) Optional system tasks and system functions
D.1 General
D.2 $countdrivers <\/td>\n<\/tr>\n
1192<\/td>\nD.3 $getpattern <\/td>\n<\/tr>\n
1193<\/td>\nD.4 $input
D.5 $key and $nokey
D.6 $list
D.7 $log and $nolog <\/td>\n<\/tr>\n
1194<\/td>\nD.8 $reset, $reset_count, and $reset_value <\/td>\n<\/tr>\n
1195<\/td>\nD.9 $save, $restart, and $incsave <\/td>\n<\/tr>\n
1196<\/td>\nD.10 $scale
D.11 $scope
D.12 $showscopes
D.13 $showvars
D.14 $sreadmemb and $sreadmemh <\/td>\n<\/tr>\n
1198<\/td>\nAnnex E (informative) Optional compiler directives
E.1 General
E.2 `default_decay_time
E.3 `default_trireg_strength <\/td>\n<\/tr>\n
1199<\/td>\nE.4 `delay_mode_distributed
E.5 `delay_mode_path
E.6 `delay_mode_unit
E.7 `delay_mode_zero <\/td>\n<\/tr>\n
1200<\/td>\nAnnex F (normative) Formal semantics of concurrent assertions
F.1 General
F.2 Overview <\/td>\n<\/tr>\n
1201<\/td>\nF.3 Abstract syntax <\/td>\n<\/tr>\n
1207<\/td>\nF.4 Rewriting algorithms <\/td>\n<\/tr>\n
1211<\/td>\nF.5 Semantics <\/td>\n<\/tr>\n
1220<\/td>\nF.6 Extended expressions
F.7 Recursive properties <\/td>\n<\/tr>\n
1222<\/td>\nAnnex G (normative) Std package
G.1 General
G.2 Overview
G.3 Semaphore
G.4 Mailbox <\/td>\n<\/tr>\n
1223<\/td>\nG.5 Randomize
G.6 Process <\/td>\n<\/tr>\n
1224<\/td>\nAnnex H (normative) DPI C layer
H.1 General
H.2 Overview <\/td>\n<\/tr>\n
1225<\/td>\nH.3 Naming conventions
H.4 Portability
H.5 svdpi.h include file <\/td>\n<\/tr>\n
1226<\/td>\nH.6 Semantic constraints <\/td>\n<\/tr>\n
1228<\/td>\nH.7 Data types <\/td>\n<\/tr>\n
1232<\/td>\nH.8 Argument passing modes <\/td>\n<\/tr>\n
1235<\/td>\nH.9 Context tasks and functions <\/td>\n<\/tr>\n
1239<\/td>\nH.10 Include files <\/td>\n<\/tr>\n
1242<\/td>\nH.11 Arrays <\/td>\n<\/tr>\n
1245<\/td>\nH.12 Open arrays <\/td>\n<\/tr>\n
1251<\/td>\nH.13 SV3.1a-compatible access to packed data (deprecated functionality) <\/td>\n<\/tr>\n
1257<\/td>\nAnnex I (normative) svdpi.h
I.1 General
I.2 Overview
I.3 Source code <\/td>\n<\/tr>\n
1266<\/td>\nAnnex J (normative) Inclusion of foreign language code
J.1 General
J.2 Overview <\/td>\n<\/tr>\n
1267<\/td>\nJ.3 Location independence
J.4 Object code inclusion <\/td>\n<\/tr>\n
1270<\/td>\nAnnex K (normative) vpi_user.h
K.1 General
K.2 Source code <\/td>\n<\/tr>\n
1287<\/td>\nAnnex L (normative) vpi_compatibility.h
L.1 General
L.2 Source code <\/td>\n<\/tr>\n
1290<\/td>\nAnnex M (normative) sv_vpi_user.h
M.1 General
M.2 Source code <\/td>\n<\/tr>\n
1300<\/td>\nAnnex N (normative) Algorithm for probabilistic distribution functions
N.1 General
N.2 Source code <\/td>\n<\/tr>\n
1308<\/td>\nAnnex O (informative) Encryption\/decryption flow
O.1 General
O.2 Overview
O.3 Tool vendor secret key encryption system <\/td>\n<\/tr>\n
1309<\/td>\nO.4 IP author secret key encryption system <\/td>\n<\/tr>\n
1310<\/td>\nO.5 Digital envelopes <\/td>\n<\/tr>\n
1312<\/td>\nAnnex P (informative) Glossary <\/td>\n<\/tr>\n
1315<\/td>\nAnnex Q (informative) Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard for SystemVerilog–Unified Hardware Design, Specification, and Verification Language<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n2012<\/td>\n1315<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":397720,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-397714","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/397714","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/397720"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=397714"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=397714"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=397714"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}