This part of IEC 62880 describes a constant temperature (isothermal) aging method for testing copper (Cu) metallization test structures on microelectronics wafers for susceptibility to stress-induced voiding (SIV). This method is to be conducted primarily at the wafer level of production during technology development, and the results are to be used for lifetime prediction and failure analysis. Under some conditions, the method can be applied to package-level testing. This method is not intended to check production lots for shipment, because of the long test time.<\/p>\n
Dual damascene Cu metallization systems usually have liners, such as tantalum (Ta) or tantalum nitride (TaN) on the bottom and sides of trenches etched into dielectric layers. Hence, for structures in which a single via contacts a wide line below it, a void under the via can cause an open circuit at almost the same time as any percentage resistance shift that would satisfy a failure criterion.<\/p>\n
| PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
|---|---|---|---|---|---|---|---|
| 2<\/td>\n | undefined <\/td>\n<\/tr>\n | ||||||
| 4<\/td>\n | CONTENTS <\/td>\n<\/tr>\n | ||||||
| 5<\/td>\n | FOREWORD <\/td>\n<\/tr>\n | ||||||
| 7<\/td>\n | 1 Scope 2 Normative references 3 Terms and definitions <\/td>\n<\/tr>\n | ||||||
| 9<\/td>\n | 4 Test method 4.1 Test structures <\/td>\n<\/tr>\n | ||||||
| 10<\/td>\n | Figures Figure 1 \u2013 SM test structure sketches <\/td>\n<\/tr>\n | ||||||
| 12<\/td>\n | Figure 2 \u2013 SM test structure sketches \u2013 Illustrative sketches ofproposed optional SM test structures <\/td>\n<\/tr>\n | ||||||
| 13<\/td>\n | 4.2 Test equipment 4.3 Test temperatures 4.4 Test conditions, sample size and measurements 4.5 Failure criteria 4.6 Passing criteria <\/td>\n<\/tr>\n | ||||||
| 14<\/td>\n | 5 Data to be reported <\/td>\n<\/tr>\n | ||||||
| 15<\/td>\n | Annex A (informative) Explanation for stress migration, stress induced voiding \u2013 Temperature, geometry dependence A.1 Stress-induced voids A.2 Stress temperature <\/td>\n<\/tr>\n | ||||||
| 16<\/td>\n | A.3 Geometry linewidth dependence of SIV risk Figure A.1 \u2013 Temperature dependent behaviour of SM MTF values of5 \u00b5m VIA chains in the range of 125 \u00baC \u2013 275 \u00baC <\/td>\n<\/tr>\n | ||||||
| 17<\/td>\n | Figure A.2 \u2013 Power-law relation of MTF vs linewidth <\/td>\n<\/tr>\n | ||||||
| 18<\/td>\n | A.4 VIA size dependence of SIV risk Figure A.3 \u2013 Median time-to-fail SM data as a function of VIA sizes Figure A.4 \u2013 Hydrostatic stress gradient at near roomtemperatures vs VIA size (area) <\/td>\n<\/tr>\n | ||||||
| 19<\/td>\n | A.5 SIV under multiple VIAs A.6 Metal thickness dependence of SIV risk Figure A.5 \u2013 FA images of two VIA case andMTF vs multiple VIA of SM <\/td>\n<\/tr>\n | ||||||
| 20<\/td>\n | A.7 SM lifetime model Figure A.6 \u2013 Metal thickness versus resistance increase under SM tests <\/td>\n<\/tr>\n | ||||||
| 21<\/td>\n | A.8 Sensitivity for test structure Figure A.7 \u2013 Stress profile of conventional and VIM VIA chains <\/td>\n<\/tr>\n | ||||||
| 22<\/td>\n | Figure A.8 \u2013 SM data of conventional and VIM VIA chains <\/td>\n<\/tr>\n | ||||||
| 23<\/td>\n | Annex B (informative) Example of geometry dependence for nose pattern B.1 General B.2 Geometry factor Figure B.1 \u2013 Representation of real product interconnect Figure B.2 \u2013 Representation of SM nose pattern <\/td>\n<\/tr>\n | ||||||
| 24<\/td>\n | Figure B.3 \u2013 Failure rate \u2013 Body area dependence with nose pattern <\/td>\n<\/tr>\n | ||||||
| 25<\/td>\n | Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Semiconductor devices. Stress migration test standard – Copper stress migration test standard<\/b><\/p>\n |