This document specifies test and measurement methods for EMC evaluation of Peripheral Sensor Interface 5 (PSI5) transceiver integrated circuits (ICs) under network condition. It defines test configurations, test conditions, test signals, failure criteria, test procedures, test setups and test boards. It is applicable for PSI5 satellite ICs (e.g. sensors) and ICs with embedded PSI5 transceivers (e.g. PSI5 Electronic control unit IC). The document covers – the emission of RF disturbances, – the immunity against RF disturbances, – the immunity against impulses and – the immunity against electrostatic discharges (ESD).<\/p>\n
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| 2<\/td>\n | undefined <\/td>\n<\/tr>\n | ||||||
| 5<\/td>\n | Annex ZA (normative)Normative references to international publicationswith their corresponding European publications <\/td>\n<\/tr>\n | ||||||
| 6<\/td>\n | Blank Page <\/td>\n<\/tr>\n | ||||||
| 7<\/td>\n | English CONTENTS <\/td>\n<\/tr>\n | ||||||
| 10<\/td>\n | FOREWORD <\/td>\n<\/tr>\n | ||||||
| 12<\/td>\n | 1 Scope 2 Normative references <\/td>\n<\/tr>\n | ||||||
| 13<\/td>\n | 3 Terms, definitions and abbreviated terms 3.1 Terms and definitions 3.2 Abbreviated terms 4 General <\/td>\n<\/tr>\n | ||||||
| 14<\/td>\n | Figures Figure 1 \u2013 PSI5 system overview Tables Table 1 \u2013 PSI5 physical layer electrical characteristics <\/td>\n<\/tr>\n | ||||||
| 15<\/td>\n | Figure 2 \u2013 Example PSI5 wiring diagram with a single sensor and equivalent model Table 2 \u2013 Overview of required measurements and tests <\/td>\n<\/tr>\n | ||||||
| 16<\/td>\n | 5 Test and operating conditions 5.1 Supply and ambient conditions 5.2 Test operation modes Table 3 \u2013 Supply and ambient conditions for functional operation <\/td>\n<\/tr>\n | ||||||
| 17<\/td>\n | Figure 3 \u2013 PSI5-A configuration with a single sensor connection with two wires Figure 4 \u2013 PSI5-P configuration with two sensor connection <\/td>\n<\/tr>\n | ||||||
| 18<\/td>\n | 5.3 Test configuration 5.3.1 General test configuration for functional test Figure 5 \u2013 General test configuration for tests in functional operation modes Table 4 \u2013 Sensor sink current specification <\/td>\n<\/tr>\n | ||||||
| 19<\/td>\n | 5.3.2 General test configuration for unpowered ESD test 5.3.3 Coupling ports for functional tests Figure 6 \u2013 General test configuration for unpowered ESD test of an ECU IC Figure 7 \u2013 General test configuration for unpowered ESD test of a satellite IC <\/td>\n<\/tr>\n | ||||||
| 20<\/td>\n | Figure 8 \u2013 Coupling ports for transceiver emission and immunity tests Table 5 \u2013 Definitions for component values of coupling portsfor transceiver emission and immunity tests <\/td>\n<\/tr>\n | ||||||
| 21<\/td>\n | 5.3.4 Coupling ports for unpowered ESD tests Figure 9 \u2013 Coupling ports for unpowered ESD tests <\/td>\n<\/tr>\n | ||||||
| 22<\/td>\n | 5.4 Test signals 5.4.1 General 5.4.2 Test signals for Asynchronous mode Table 6 \u2013 Definitions of coupling ports for unpowered ESD tests <\/td>\n<\/tr>\n | ||||||
| 23<\/td>\n | Table 7 \u2013 Communication test signal TX1 for Asynchronous mode (125 kbps) <\/td>\n<\/tr>\n | ||||||
| 24<\/td>\n | Table 8 \u2013 Communication test signal TX2 for Asynchronous mode (189 kbps) <\/td>\n<\/tr>\n | ||||||
| 25<\/td>\n | 5.4.3 Test signal for Synchronous parallel bus mode Table 9 \u2013 Communication test signal TX3 for Asynchronous low-power mode <\/td>\n<\/tr>\n | ||||||
| 26<\/td>\n | 5.5 Evaluation criteria 5.5.1 General Table 10 \u2013 Communication test signal TX4 for Synchronous parallel bus mode Table 11 \u2013 Communication test signal TX5 for Synchronous parallel bus mode <\/td>\n<\/tr>\n | ||||||
| 27<\/td>\n | 5.5.2 Evaluation criteria in functional operation modes during exposure to disturbances 5.5.3 Evaluation criteria in unpowered condition after exposure to disturbances Table 12 \u2013 Evaluation criteria for standalone and embedded PSI5transceiver IC in functional operation modes <\/td>\n<\/tr>\n | ||||||
| 28<\/td>\n | 6 Test and measurement 6.1 Emission of RF disturbances 6.1.1 Test method 6.1.2 Test setup Figure 10 \u2013 Example drawing of the maximum deviation on an IV characteristic <\/td>\n<\/tr>\n | ||||||
| 29<\/td>\n | Figure 11 \u2013 Test setup for measurement of RF disturbances <\/td>\n<\/tr>\n | ||||||
| 30<\/td>\n | 6.1.3 Test procedure and parameters 6.2 Immunity to RF disturbances 6.2.1 Test method 6.2.2 Test setup Table 13 \u2013 Parameters for emission measurements Table 14 \u2013 Settings of the RF measurement equipment <\/td>\n<\/tr>\n | ||||||
| 31<\/td>\n | Figure 12 \u2013 Test setup for DPI tests <\/td>\n<\/tr>\n | ||||||
| 32<\/td>\n | 6.2.3 Test procedure and parameters Table 15 \u2013 Specifications for DPI tests <\/td>\n<\/tr>\n | ||||||
| 33<\/td>\n | Table 16 \u2013 Required DPI tests for functional status class AIC evaluation of Standard PSI5 transceiver ICs and embedded PSI5 transceiver ICs Table 17 \u2013 Required DPI tests for functional status class CIC or DIC evaluation of standard PSI5 transceiver ICs and ICs with embedded PSI5 transceiver <\/td>\n<\/tr>\n | ||||||
| 34<\/td>\n | 6.3 Immunity to impulses 6.3.1 Test method 6.3.2 Test setup Figure 13 \u2013 Test setup for impulse immunity tests <\/td>\n<\/tr>\n | ||||||
| 35<\/td>\n | 6.3.3 Test procedure and parameters Table 18 \u2013 Specifications for impulse immunity tests <\/td>\n<\/tr>\n | ||||||
| 36<\/td>\n | Table 19 \u2013 Parameters for impulse immunity test Table 20 \u2013 Required impulse immunity tests for functional status class AIC evaluation of standard and embedded PSI5 transceiver ICs Table 21 \u2013 Required impulse immunity tests for functional status class CIC or DIC evaluation of Standard PSI5 transceiver ICs and ICs with embedded PSI transceiver <\/td>\n<\/tr>\n | ||||||
| 37<\/td>\n | 6.4 Electrostatic discharge (ESD) 6.4.1 Test method 6.4.2 Test setup <\/td>\n<\/tr>\n | ||||||
| 38<\/td>\n | Figure 14 \u2013 Test setup for direct ESD tests <\/td>\n<\/tr>\n | ||||||
| 39<\/td>\n | 6.4.3 Test procedure and parameters <\/td>\n<\/tr>\n | ||||||
| 40<\/td>\n | 7 Test report Table 22 \u2013 Specifications for direct ESD tests <\/td>\n<\/tr>\n | ||||||
| 41<\/td>\n | Annex A (normative)PSI5 test circuits A.1 General A.2 Test circuit for emission and immunity tests on a PSI5 ECU IC <\/td>\n<\/tr>\n | ||||||
| 43<\/td>\n | Figure A.1 \u2013 General circuit diagram of the PSI5 test networkfor emission and immunity tests on ECU IC <\/td>\n<\/tr>\n | ||||||
| 44<\/td>\n | A.3 Test circuit for emission and immunity tests on a PSI5 satellite IC <\/td>\n<\/tr>\n | ||||||
| 45<\/td>\n | Figure A.2 \u2013 General circuit diagram of the PSI5 test networkfor emission and immunity tests on Satellite IC <\/td>\n<\/tr>\n | ||||||
| 46<\/td>\n | A.4 Test circuit for an unpowered ESD test on a PSI5 IC Figure A.3 \u2013 General circuit diagram of the PSI5 ECU ICfor testing of direct ESD in unpowered mode <\/td>\n<\/tr>\n | ||||||
| 47<\/td>\n | Figure A.4 \u2013 General circuit diagram of the PSI5 sensor ICfor testing of direct ESD in unpowered mode <\/td>\n<\/tr>\n | ||||||
| 48<\/td>\n | Annex B (normative)Test circuit boards B.1 Test circuit board for emission and immunity tests B.2 ESD test Table B.1 \u2013 Parameter ESD test circuit board <\/td>\n<\/tr>\n | ||||||
| 49<\/td>\n | Annex C (informative)Examples of test limits for PSI5 transceiver in automotive applications C.1 General C.2 Emission of RF disturbances Figure C.1 \u2013 Example of limits for RF emission \u2013 PSI5 pins <\/td>\n<\/tr>\n | ||||||
| 50<\/td>\n | C.3 Immunity to RF disturbances Figure C.2 \u2013 Example of limits for RF emission \u2013 Other global pins <\/td>\n<\/tr>\n | ||||||
| 51<\/td>\n | Figure C.3 \u2013 Example of limits for RF immunity for functional status class AIC \u2013 PSI5 pins Figure C.4 \u2013 Example of limits for RF immunity for functional status class AIC \u2013 Other global pins <\/td>\n<\/tr>\n | ||||||
| 52<\/td>\n | Figure C.5 \u2013 Example of limits for RF immunity for functional status class CIC or DIC \u2013 PSI5 pins Figure C.6 \u2013 Example of limits for RF immunity for functional status class CIC or DIC \u2013 Other global pins <\/td>\n<\/tr>\n | ||||||
| 53<\/td>\n | C.4 Immunity to Impulses C.5 ESD Table C.1 \u2013 Example of limits for impulse immunity for functional status class CIC or DIC <\/td>\n<\/tr>\n | ||||||
| 54<\/td>\n | Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Integrated circuit. EMC evaluation of transceivers – PSI5 transceivers<\/b><\/p>\n |