{"id":418242,"date":"2024-10-20T06:20:06","date_gmt":"2024-10-20T06:20:06","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/bs-iec-62951-92022\/"},"modified":"2024-10-26T11:49:06","modified_gmt":"2024-10-26T11:49:06","slug":"bs-iec-62951-92022","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/bsi\/bs-iec-62951-92022\/","title":{"rendered":"BS IEC 62951-9:2022"},"content":{"rendered":"
PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
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2<\/td>\n | undefined <\/td>\n<\/tr>\n | ||||||
4<\/td>\n | CONTENTS <\/td>\n<\/tr>\n | ||||||
5<\/td>\n | FOREWORD <\/td>\n<\/tr>\n | ||||||
7<\/td>\n | 1 Scope 2 Normative references 3 Terms and definitions <\/td>\n<\/tr>\n | ||||||
9<\/td>\n | 4 Device under testing (DUT) <\/td>\n<\/tr>\n | ||||||
10<\/td>\n | 5 Test method 5.1 General 5.2 Test equipment and tools 5.2.1 General Figures Figure 1 \u2013 1T1R resistive memory cell <\/td>\n<\/tr>\n | ||||||
11<\/td>\n | 5.2.2 Read Figure 2 \u2013 Block diagram of the measurement setup of 1T1R resistive memory cells Figure 3 \u2013 Read operation of 1T1R resistive memory cell <\/td>\n<\/tr>\n | ||||||
12<\/td>\n | 5.2.3 Forming Figure 4 \u2013 Cumulative probability distribution of HRSand LRS of 1T1R resistive memory cells <\/td>\n<\/tr>\n | ||||||
13<\/td>\n | 5.2.4 SET programming Figure 5 \u2013 Forming operation of 1T1R resistive memory cell Figure 6 \u2013 Simulation test flow chart of the forming process <\/td>\n<\/tr>\n | ||||||
14<\/td>\n | 5.2.5 RESET programming Figure 7 \u2013 SET operation of 1T1R resistive memory cell Figure 8 \u2013 Simulation test flow chart of the SET operation of 1T1R resistive memory cell <\/td>\n<\/tr>\n | ||||||
15<\/td>\n | Figure 9 \u2013 RESET operation of 1T1R resistive memory cell Figure 10 \u2013 Simulation test flow chart of the RESET operationof 1T1R resistive memory cell <\/td>\n<\/tr>\n | ||||||
16<\/td>\n | 5.2.6 Endurance Figure 11 \u2013 Cumulative resistance distribution of 1T1R resistive memory <\/td>\n<\/tr>\n | ||||||
17<\/td>\n | Figure 12 \u2013 Simulation test flow chart of the endurance testof 1T1R resistive memory cell Figure 13 \u2013 Exemplary endurance data of a 1T1R resistive memory cell <\/td>\n<\/tr>\n | ||||||
18<\/td>\n | 5.2.7 Retention Figure 14 \u2013 Simulation test flow chart of retention propertyof 1T1R resistive memory cells Figure 15 \u2013 Exemplary retention characteristics of 1T1R resistive memory cells <\/td>\n<\/tr>\n | ||||||
19<\/td>\n | 5.3 Test report <\/td>\n<\/tr>\n | ||||||
20<\/td>\n | Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Semiconductor devices. Flexible and stretchable semiconductor devices – Performance testing methods of one transistor and one resistor (1T1R) resistive memory cells<\/b><\/p>\n |