{"id":79458,"date":"2024-10-17T18:34:39","date_gmt":"2024-10-17T18:34:39","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-960-1990\/"},"modified":"2024-10-24T19:40:12","modified_gmt":"2024-10-24T19:40:12","slug":"ieee-960-1990","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-960-1990\/","title":{"rendered":"IEEE 960 1990"},"content":{"rendered":"

Revision Standard – Inactive – Superseded. Mechanical, signal, electrical, and protocol specifications are given for a modular data bus system, which, while allowing equipment designers a wide choice of solutions, ensure compatibility of all designs that obey the mandatory parts of the specification. This standard applies to systems consisting of modular electronic instrument units that process or transfer data or signals, normally in association with computers or other automatic data processors.<\/p>\n

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
14<\/td>\nDaisy Chain Right
Terminated Restricted Use
Unterminated Restricted Use
User Defined Status
User Mode Bits
Miscellaneous0-
Test Result
User Status
Interrupt Destination <\/td>\n<\/tr>\n
22<\/td>\n1.1.6 Remote Sense
1.1.7 Regulation and Stability
1.1.8 Temperature Coefficient
1.1.9 Noise and Ripple <\/td>\n<\/tr>\n
24<\/td>\n1.1.15 Monitoring
1.1.16 Margining
External Breaker Trip Control
1.1.18 Switched ac Outlet
1.1.19 Front Panel <\/td>\n<\/tr>\n
25<\/td>\n1.1.20 Rack Mounting
1.1.21 Cooling
1.2 Low-Noise Power Supply
1.2.1 General
1.2.2 Efficiency
1.2.3 Ambient Temperature Range
1.2.4 Input
1.2.5 Output
1.2.6 Remote Sense
1.2.7 Regulation and Stability
1.2.8 Temperature Coefficient
1.2.9 Noise and fipple
Recovery Time and Turn-On and Turn-off Transients
Conducted and Radiated Noise
1.2.1 FASTBUS Signals <\/td>\n<\/tr>\n
26<\/td>\n1.2.12 Output Terminals
1.2.13 Voltage Adjustment Controls
1.2.14 Protection
1.2.15 Monitoring
1.2.16 Margining
External Breaker Trip Control
1.2.18 Switched ac Outlet
1.2.19 Front Panel
1.2.20 Rack Mounting
1.2.21 Cooling <\/td>\n<\/tr>\n
34<\/td>\n2.2.2 Definition of the Environment
2.2.3 Environment Identifier
2.2.4 Execution Modes <\/td>\n<\/tr>\n
35<\/td>\n2.2.5 A FASTBUS Session
2.2.6 Action Routines
2.2.7 Call Time and Execution Time
2.3 Naming Conventions <\/td>\n<\/tr>\n
36<\/td>\n2.4 Parameters to Routines: Type and Direction <\/td>\n<\/tr>\n
37<\/td>\n2.5 Buffer Parameters <\/td>\n<\/tr>\n
38<\/td>\n2.6 Categories of Routines <\/td>\n<\/tr>\n
44<\/td>\n3.1.2 Close FASTBUS Session
3.2 Environment Management Routines
3.2.1 Create an Immediate Execution Mode Environment <\/td>\n<\/tr>\n
47<\/td>\n4 FASTBUS Operations: Addressing
4 FASTBUS Operations: Addressing
4.1 Logical Addressing
Operational Parameters
3.3.5 Set an Environment
3.4 Delayed Execution and List Validation
3.4.1 Execute a List
4 Operational Parameters
4.1 Introduction
4.1.1 Operational Pa.rameters in Delayed Execution Mode
4.2 Defiaition of Operational Parameter
4.3.7 Pop Current 0perationa.l Pa.rameters off Stack <\/td>\n<\/tr>\n
48<\/td>\n4.3 Operational Parameter Routines
4.3.1 Initialize Operational Parameter
4.3.2 Set Operational Parameter
4.3.3 Get Operational Parameter <\/td>\n<\/tr>\n
49<\/td>\n4.2 Geographical Addressing
4.3.4 Read Operational Parameter
4.3.5 Write Operational Parameter <\/td>\n<\/tr>\n
50<\/td>\n4.3 Broadcast Addressing
4.3.1 Master\u2122s Control of a Broadcast
4.3.6 Push Current Operational Parameters onto Stack
4.4 Overall and Error Handling Operational Parameters
4.4.1 Controller Port Identifier <\/td>\n<\/tr>\n
51<\/td>\n4.4.2 Do Not Wait for Completion of Action(s)
4.4.3 Delay Execution
4.4.4 Environment Size
4.4.5 Limit Status Generation <\/td>\n<\/tr>\n
52<\/td>\n4.3.1 Master\u2122s Control of Broadcast
4.4.6 Return Code contains only the Severity
4.4.7 Error Handler Severity Threshold
4.4.8 Error Reporting Severity Threshold <\/td>\n<\/tr>\n
53<\/td>\n4.3.2 Slave Response to Broadcast Operations
4.3.2 Function Encoding for Broadcast Slave Response
4.4.9 Exception Severity Threshold
4.4.10 Message Severity Threshold
4.4.11 Report Terse Message <\/td>\n<\/tr>\n
54<\/td>\n4.4 Secondary Addressing
4.4.12 Report On Each Action
4.5 FASTBUS Protocol Timeout and Retry Operational Parameters
4.5.1 Arbitration Level <\/td>\n<\/tr>\n
55<\/td>\n4.5 Sparse Data Scan and Pattern Select Operation
4.5.2 Assured Access Arbitration Protocol
4.5.3 Prioritized Access Arbitration Protocol
4.5.4 Hold Mastership for Whole Block
4.5.5 FASTBUS Block Transfer Blocklet Size <\/td>\n<\/tr>\n
56<\/td>\n4.5.6 Pipelined Transfer
4.5.7 Pipelined Transfer Data Cycle Clock Time
4.5.8 Fixed NTA Device
4.5.9 Transfer Data as Short Words <\/td>\n<\/tr>\n
57<\/td>\nFASTBUS Operations: Timing Sequences and Responses
5 FASTBUS Operations: Timing Sequences and Responses
5.1 General Master\/Slave Timing Requirements
5 Handshaked Cycle Timing Sequence
Data Buffers
4.5.10 Short Word Size
4.5.11 Control of Parity Generation
4.5.12 Enable Geographic Addressing
4.5.13 No Arbitration Cycle
5 Data Buffers
5.1 Buffer Access Arguments
5.1.1 Buffer specified as a Variable or Array
5.1.2 Buffer specified as a Value
5.1.3 Buffer specified as a Sequential Buffer ID <\/td>\n<\/tr>\n
58<\/td>\n5.1.1 Master Signal Timing Requirements
5.2 Sequential Data Buffer Routines
5.2.1 Declare Internal Buffer
5.2.2 Declare External Buffer <\/td>\n<\/tr>\n
59<\/td>\n5.1.2 Slave Signal Timing Requirements
5.2.3 Release Internal Sequential Data Buffer
5.2.4 Read Sequential Buffer Pointer
5.2.5 Write Sequential Buffer Pointer <\/td>\n<\/tr>\n
60<\/td>\n5.1.3 Use of Wait (WT)
5.2.6 Displace Sequential Buffer Pointer <\/td>\n<\/tr>\n
61<\/td>\n5.2 Primary Address Cycles
5.2.1 Master Sequence for Asserting AS
5.2.2 Slave Response to AS(u) <\/td>\n<\/tr>\n
65<\/td>\n5.2.3 Master Response To AK(u)
5.2.1 Address Type Specification <\/td>\n<\/tr>\n
66<\/td>\n5.3 Operations
5.2.3 Address Time SS Response With AK(u) <\/td>\n<\/tr>\n
67<\/td>\n5.3.1 Master Sequence for Asserting DS <\/td>\n<\/tr>\n
71<\/td>\n5.3.2 Slave Response to DS(t)
5.3.3 Discussion of Slave Status Responses
5.3.1 MS Interpretation for Data Cycles <\/td>\n<\/tr>\n
72<\/td>\n5.3.2(a Slave Data Time SS Responses With DK(t)
5.3.2(b Slave SS Responses and Actions at DK(t) <\/td>\n<\/tr>\n
73<\/td>\n5.3.4 Master Response to DK(t)
5.4 Use of Reset Bus (RB)
5.4.1 Master Assertion of RB <\/td>\n<\/tr>\n
74<\/td>\n5.4.2 Device Response to RB
5.5 Device Response to POWER ON <\/td>\n<\/tr>\n
75<\/td>\n6 Bus Arbitration
6 Bus Arbitration
6.1 Bus Line Usage for the Arbitration Process
Simple Transaction Routines
6 Simple Transaction Routines
6.1 Conditions Governing Transaction and Compound Routines
6.1.1 Arbitration
6.1.2 Primary Address <\/td>\n<\/tr>\n
76<\/td>\n6.1 FASTBUS Arbitration Lines
6.1.3 Secondary Address Write Cycle <\/td>\n<\/tr>\n
77<\/td>\n6.1.6 Disconnection
6.2 Simple FASTBUS Transaction Routines <\/td>\n<\/tr>\n
78<\/td>\n6.2 The Arbitration Process
6.3 Arbitration Rules
Master Assertion of AR and Segment Interconnect Passing of AR
6.2.2 Block Transfer <\/td>\n<\/tr>\n
79<\/td>\n6.2.3 Secondary Address Routines <\/td>\n<\/tr>\n
80<\/td>\n6.3.2 ATC Assertion and Release of AI
6.3.3 ATC Assertion and Release of AG
6.3.4 Master Assertion and Release of AL
6.2.4 Read Length of Last Data Transfer <\/td>\n<\/tr>\n
81<\/td>\n6.3.5 Master Assertion and Release of GK <\/td>\n<\/tr>\n
82<\/td>\n6.4 System-Wide Arbitration <\/td>\n<\/tr>\n
83<\/td>\nAncillary Logic on a Segment
7 Ancillary Logic on a Segment
7.1 Arbitration Timing Control (ATC)
7.1.1 ATC Generation of AI
7.1.2 ATC Generation of AG
Compound Transaction Routines
7 Compound Transaction Routines
7.1 Access Segment Interconnect Route Table
7.2 Move Data between FASTBUS Devices <\/td>\n<\/tr>\n
84<\/td>\n7.2 Geographical Address Control
7.3 Read-Modify-Write a FASTBUS Location <\/td>\n<\/tr>\n
85<\/td>\n7.3 System Handshake Generation (Broadcast)
7.4 Data Gathering Routines
7.4.1 Read Data from Sequential Device Addresses <\/td>\n<\/tr>\n
86<\/td>\n7.5 Terminators
7.6 Ancillary Logic for Crate Segments
Read Data from Devices that Respond to a T-pin Scan
7.4.3 Allocate a FASTBUS Device <\/td>\n<\/tr>\n
87<\/td>\n7.7 Ancillary Logic for Cable Segments
7.4.4 Deallocate a FASTBUS Device
7.5 Send a FASTBUS Interrupt Message <\/td>\n<\/tr>\n
89<\/td>\nControl and Status Register Space
8 Control and Status Register Space
8.1 Selective Set and Clear Functions
Primitive FASTBUS Action Routines
8 Primitive FASTBUS Action Routines
8.1 Introduction
8.2 Parameters
8.3 Single Cycle Routines
8.3.1 Arbitrate
8.3.2 Release Bus Mastership <\/td>\n<\/tr>\n
90<\/td>\n8.2 Normal CSR Space Allocation
8.1 CSR Selective Set\/Clear Function Implementation
8.3.3 Primary Address Cycle <\/td>\n<\/tr>\n
91<\/td>\n8.2 Control\/Status Registers
8.3.4 Disconnect
8.3.5 Single Word Transfers <\/td>\n<\/tr>\n
92<\/td>\n8.3 CSR Register
8.3.1 Device IDS and Their Allocation
8.4 FASTBUS Line Access <\/td>\n<\/tr>\n
93<\/td>\n8.3.2 Control and Status Bit Allocation
8.3.2(a CSR Register 0 Bit Assignments
8.4.1 Read Single Bus Line(s) <\/td>\n<\/tr>\n
94<\/td>\n8.3.2(b Definition of CSR#O Bits
8.4.3 Read Internal line(s) <\/td>\n<\/tr>\n
95<\/td>\n8.4 CSR Register
8.5 CSR Register <\/td>\n<\/tr>\n
96<\/td>\n8.5(a CSR Register 2 Bit Assignments <\/td>\n<\/tr>\n
97<\/td>\n8.5(b Definition of CSR#2 Bits <\/td>\n<\/tr>\n
98<\/td>\n8.6 CSR Register
8.7 CSR Register
8.8 CSR Register
8.9 CSR Register
8.10 CSR Register <\/td>\n<\/tr>\n
99<\/td>\n8.11 CSR Register
8.12 CSR Register 9 and CSR Registers 1Ch to 1Fh
8.12 Timer Control Register <\/td>\n<\/tr>\n
100<\/td>\n8.13 CSR Registers Ah to Fh
8.14 CSR Registers 20h to 3Fh
8.15 CSR Registers 70h to 81h
8.16 CSR Registers AOh to AFh BOh to BFh and COh to CFh
8.17 CSR Registers 8000 OOOOh to BFFF FFFFh Parameter Space <\/td>\n<\/tr>\n
102<\/td>\n8.17(a CSR Parameter Space Address Allocation
8.17(b Definition of Terms Used in Table 8.17(a <\/td>\n<\/tr>\n
103<\/td>\n8.18 Clearing of CSR Bits
8.18 Clearing of CSR Bits <\/td>\n<\/tr>\n
105<\/td>\n9 Interrupts
9 Interrupts
9.1 Interrupt Operation
FASTBUS SR and Interrupt Message Routines
9 FASTBUS SR and Interrupt Message Routines
9.1 Introduction
9.2 FASTBUS Service Request
9.2.1 Clearing the SR Assertion <\/td>\n<\/tr>\n
106<\/td>\n9.2 The Service Request Line
9.2.4 Enable SR Connections <\/td>\n<\/tr>\n
107<\/td>\n9.2.5 Disable SR Connections
9.3 FASTBUS Interrupt Message Routines
9.3.1 Connect Routine to FIR <\/td>\n<\/tr>\n
108<\/td>\n9.3.2 Disconnect Routine from FIR
9.3.3 Enable FIR Connections <\/td>\n<\/tr>\n
109<\/td>\n10 Interconnection of Segments
10 Interconnection of Segments
Synchronization Syatem Resource and Port Routines
10 Synchronbation System Resource and Port Routines
10.1 Synchronization Tools
10.1.1 Wait for Completion of Operation
10.1.2 Check Completion State <\/td>\n<\/tr>\n
110<\/td>\n10.1 Types of Segment Interconnects
10.2 Operation Passing
10.3 Contention Resolution
10.1.3 Connect Completion Routine
10.1.4 Disconnect a Completion Routine
10.2 Reset FASTBUS Port <\/td>\n<\/tr>\n
111<\/td>\n10.4 Route Tables
10.3.1 Allocate FASTBUS Port
10.3.2 Deallocate FASTBUS Port
10.4 Get Version Numbers <\/td>\n<\/tr>\n
112<\/td>\n10.5 Control and Status Registers
10.5 Report a Port FASTBUS Error
10.6 Generate a Port Error Message <\/td>\n<\/tr>\n
113<\/td>\n10.5.1 CSR#O ID Status and Control
Bit Assignments in an SI <\/td>\n<\/tr>\n
114<\/td>\n10.5.l(b)Definition of CSR#O Bits <\/td>\n<\/tr>\n
115<\/td>\n10.5.2 CSR#1 Far-side Arbitration Level
10.5.3 CSR#8 Near-side Arbitration Level <\/td>\n<\/tr>\n
116<\/td>\n10.5.4 CSR#9 Timer Control Register
10.5.5 CSR#40h Route Table Address Register
10.5.6 CSR#4lh Route Table Data Register
10.5.7 CSR#42h Near-side Geographical Address <\/td>\n<\/tr>\n
117<\/td>\n10.5.8 CSR#43h Far-side Geographical Address
Effect of Various Actions on CSR Bits in SIs
10.6 Route Tables
10.6.1 Pass Destination and Base Information
10.5.9 Effect of Various Actions on Bits in SIs <\/td>\n<\/tr>\n
118<\/td>\n10.6.2 Generation Rules
10.7 SI Actions
10.7.1 Address Recognition <\/td>\n<\/tr>\n
119<\/td>\n10.7.2 SI Arbitration ‘:
10.7.3 Contention Resolution <\/td>\n<\/tr>\n
120<\/td>\n10.7.4 Negative Responses <\/td>\n<\/tr>\n
121<\/td>\n10.7.5 Modification of Geographical and Broadcast Addresses
10.7.6 Operation Passing <\/td>\n<\/tr>\n
123<\/td>\n10.7.7 SI Use and Generation of Parity
10.7.6 SI Response to Addresses <\/td>\n<\/tr>\n
124<\/td>\n10.7.8 Segment Interconnect Response to RB
10.7.9 Timing Requirements
10.8 Base Address Register <\/td>\n<\/tr>\n
125<\/td>\n11 Block and Pipelined Transfers
11 Block and Pipelined Transfers
11.1 Block and Pipelined Transfer Termination
Status and Error Handling
11 Status and Error Handling
11.1 Introduction
11.2 Error and Return Codes
11.3 Summary and Supplementary Status <\/td>\n<\/tr>\n
126<\/td>\n11.2 Block Transfer Internal Address Incrementation
11.4 Restricting Generation of Status Information
11.5 Delayed Mode Execution Status
11.6 Severity
11.6.1 FB-SEVSUCCESS (FSSUCC)
11.6.2 FB-SEVINFO (FSINFO)
11.6.3 FB-SEV-WARNING (FSWARN) <\/td>\n<\/tr>\n
127<\/td>\n11.3 FIFOs and Data Transfer Errors
11.6.4 FB-SEV-ERROR (FSERR)
11.6.5 FB-SEV-FATAL (FSFTL)
11.6.6 FB-SEV-NEVER (FSNEV)
11.7 Set the Severity of an Error Code
11.8 Response to Errors in Execution <\/td>\n<\/tr>\n
129<\/td>\n12 Signal Characteristics
12 Signal Characteristics
12.1 SignalLevels
Error Codes
12 Error Codes
12.1 Standard Set of Error Codes <\/td>\n<\/tr>\n
131<\/td>\n13 Modules
13 Modules
13.1 Module Circuit Board <\/td>\n<\/tr>\n
135<\/td>\n13.1.1 Grounding Area For Static Charge Discharge
13.1.2 Stiffener Bars
13.2 Connectors
13.2.1 Segment Connector <\/td>\n<\/tr>\n
136<\/td>\n13.2.1 Segment Connector Contact Assignments <\/td>\n<\/tr>\n
137<\/td>\n13.2.2 Module Auxiliary Connector <\/td>\n<\/tr>\n
139<\/td>\n13.2.3 Other Connectors
13.2.4 Segment and Auxiliary Connector Contact Designations
13.3 Temperature Considerations and Power Dissipation
13.3.1 Die and Module Temperatures
13.3.2 Power Dissipation
13.3.3 Cooling <\/td>\n<\/tr>\n
140<\/td>\n13.4 Front Panel
13.5 Module Activity Indicators <\/td>\n<\/tr>\n
141<\/td>\n13.6 Labeling of Power Requirements
13.7 Transients <\/td>\n<\/tr>\n
143<\/td>\n14 Crates
14 Crates
14.1 Crate Construction
14.2 Crate Backplane
14.2.1 Crate Segment Connector and Associated Wiring <\/td>\n<\/tr>\n
147<\/td>\n14.2.2 Crate Auxiliary Connector <\/td>\n<\/tr>\n
148<\/td>\n14.2.3 Connector Guides <\/td>\n<\/tr>\n
149<\/td>\n14.2.4 Backplane Current Requirements <\/td>\n<\/tr>\n
150<\/td>\n14.2.5 Other Backplane Items
14.3 Cooling
14.4 Run\/Halt Switch Assembly
14.5 Circuit Boards Mounted at Rear of Backplane <\/td>\n<\/tr>\n
151<\/td>\n14.6 Crate Markings <\/td>\n<\/tr>\n
152<\/td>\n14.7 Contacts for Static Charge Discharge <\/td>\n<\/tr>\n
153<\/td>\n15 Power
15 Power <\/td>\n<\/tr>\n
155<\/td>\n16 Cable Segment
16 Cable Segment
16.1 Signals on a Cable Segment
16.2 Cable Segment Connectors and Contact Assignments
16.1 Cable Segment Signals <\/td>\n<\/tr>\n
156<\/td>\n16.2(a Cable Segment Connector Contact Assignments <\/td>\n<\/tr>\n
158<\/td>\nRecommended Utilization of Auxiliary Connector for Cable Segment Implementations <\/td>\n<\/tr>\n
159<\/td>\nRequirements for Various Implementations
A Requirements for Various Implementations
A.l ECL Implementation
A.l.l ECL Connections and Signal Level Details
Summary of Routine Names and Parameters <\/td>\n<\/tr>\n
160<\/td>\nA.l.l Resistance Ranges for Stranded Copper Wire <\/td>\n<\/tr>\n
161<\/td>\nA.1.2 ECL Timing Details
A.1.3 Retry Period
A.1.4 Response Times
A.1.5 Terminators
A.1.6 GA Logic Generating Circuit Requirements
A.1.7 Differential Die Temperatures
A.1.8 Module Distribution in Crate Segments
Routine sorted by Short Name <\/td>\n<\/tr>\n
162<\/td>\nA.1.2 Characteristic Times for ECL Implementations <\/td>\n<\/tr>\n
163<\/td>\nRoutines sorted by Long Name <\/td>\n<\/tr>\n
172<\/td>\nIA <\/td>\n<\/tr>\n
177<\/td>\nExamples of Type A Crate Implementation
G Examples of Type A Crate Implementation
G.l.l Type A Crate Construction
G.1.2 Type A Crate Backplane
Example of Type A Crate Implementation
G.3 Mounting Provision for Rear-Mounted Circuit Boards <\/td>\n<\/tr>\n
178<\/td>\n6.1.4 Datacycles
6.1.5 Block Transfers <\/td>\n<\/tr>\n
187<\/td>\n1 Introduction And General Information
Typical Power Supplies
I Typical Power Supplies
High Efficiency Power Supply
1.1.1 General
1.1.2 Efficiency
Ambient Temperature Range
1.1.4 Input
1.1.5 Output
Introduction
1.1 Scope and Object
Interpretation of this Standard
1.3 Document Overview
1.4 References <\/td>\n<\/tr>\n
189<\/td>\nRecovery Time and Turn-On and Turn-off Transients
Conducted and Radiated Noise
1.1.12 Output Terminals
1.1.13 Voltage Adjustment Controls
1.1.14 Protection <\/td>\n<\/tr>\n
193<\/td>\nNon-Zero Status Handling Procedures
Non-Zero Status Handling Procedures
J.l Address-Time Errors
Time-out at Address Time
Parity Error at Address Time
SS=1 at Address Time – Network Busy
at Address Time – Network Failure
at Address Time – Network Abort
SS=2 or SS=3 SI Responses – General <\/td>\n<\/tr>\n
203<\/td>\nSystem and Circuit Protection <\/td>\n<\/tr>\n
214<\/td>\n3.1 Open and Close FASTBUS Session <\/td>\n<\/tr>\n
215<\/td>\nF Pins (free use not bussed)
Reserved
INTEGER *
INTEGER *
INTEGER *
INTEGER *
INTEGER *
INTEGER *
INTEGER *
INTEGER *
INTEGER *
INTEGER *
INTEGER *
INTEGER *
INTEGER *
INTEGER * <\/td>\n<\/tr>\n
219<\/td>\n8.3.6 Block Transfers <\/td>\n<\/tr>\n
221<\/td>\n10.3 FASTBUS Port Allocation <\/td>\n<\/tr>\n
235<\/td>\nConventions Definitions Abbreviations Symbols and References
Basic Concepts
2 Basic Concepts
2.1 Terminology
2.2 Environment
2.2.1 Overview <\/td>\n<\/tr>\n
241<\/td>\nSignals Signal Lines and Pins
Environment Management and Delayed Action
Environment Management and Delayed Action
3.1.1 Open FASTBUS Session
3.4.2 Validate a List <\/td>\n<\/tr>\n
243<\/td>\n3.3 Create a Delayed Execution Mode Environment
3.3.1 Release Environment <\/td>\n<\/tr>\n
244<\/td>\n3.3.24 TX RX Serial Network Lines A. Master or Slave)
3.3.26 UR Unterminated Restricted Use Lines
3.3.27 Other Lines and Pins
3.4 Bus Loading
Voltage and Current Limits for Signal Lines and F Pins
3.3.2 Reset Environment
3.3.3 Copy an Environment
3.3.4 Get an Environment <\/td>\n<\/tr>\n
300<\/td>\n11.8.1 FB-RESPJGNORE
11.8.2 FB-RESP-ABORT
11.8.3 FB-RESP-RETRYABORT
11.8.4 FB-RESP-RETRYJGNORE <\/td>\n<\/tr>\n
301<\/td>\n11.8.5 FB-RESP-ABORTACTION
11.8.6 FB-RESP-RETRYABORTACTION
11.8.7 Severity of Error Codes generated with Associated Error Response
11.8.8 Specify and Determine Response to an Error <\/td>\n<\/tr>\n
303<\/td>\n11.9.1 Connect User Error Handling Routine
Disconnect User Error Handling Routine
11.9.3 Details of User Error Handling Routine <\/td>\n<\/tr>\n
304<\/td>\n11.1O.lDecode Summary Status
11.11Access to Supplementary Status Information <\/td>\n<\/tr>\n
305<\/td>\n11.11.1 Decode Supplementary Status Information
11.11.2Decode Supplementary Status from Execution of a List <\/td>\n<\/tr>\n
306<\/td>\n11.11.3Find Supplementary Status Information
11.11.4Find Specific Supplementary Status within a List <\/td>\n<\/tr>\n
307<\/td>\n11.12Routines for the Manipulation of Error Codes
11.12.1Check Severity of an Error Code
11.12.2 Test Status Code in Error Code
11.12.3Test Severity in an Error Code <\/td>\n<\/tr>\n
308<\/td>\n11.12.4Return Error Code of Specified Severity
11.13Report a FASTBUS Error
11.14Generate an Error Message <\/td>\n<\/tr>\n
331<\/td>\nTA
TA
Timer Control1- <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard FASTBUS Modular High-Speed Data Acquisition and Control System and IEEE FASTBUS Standard Routines<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n1990<\/td>\n339<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":79459,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-79458","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/79458","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/79459"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=79458"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=79458"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=79458"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}