{"id":79708,"date":"2024-10-17T18:37:08","date_gmt":"2024-10-17T18:37:08","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1076-1-1999\/"},"modified":"2024-10-24T19:41:03","modified_gmt":"2024-10-24T19:41:03","slug":"ieee-1076-1-1999","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1076-1-1999\/","title":{"rendered":"IEEE 1076.1 1999"},"content":{"rendered":"

New IEEE Standard – Inactive – Superseded. Superseded by IEEE Std 1076.1-2007. This standard defines the IEEE 1076.1 language, a hardware description language for the description and the simulation of analog, digital, and mixed-signal systems. The language, also informally known as VHDL-AMS, is bu<\/p>\n

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
1<\/td>\nTitle Page <\/td>\n<\/tr>\n
3<\/td>\nIntroduction <\/td>\n<\/tr>\n
4<\/td>\nParticipants <\/td>\n<\/tr>\n
8<\/td>\nCONTENTS <\/td>\n<\/tr>\n
11<\/td>\n0. Overview
0.1 Purpose and scope
0.2 Standards used as references <\/td>\n<\/tr>\n
12<\/td>\n0.3 Structure and terminology of this document <\/td>\n<\/tr>\n
15<\/td>\n1. Design entities and configurations
1.1 Entity declarations <\/td>\n<\/tr>\n
20<\/td>\n1.2 Architecture bodies <\/td>\n<\/tr>\n
22<\/td>\n1.3 Configuration declarations <\/td>\n<\/tr>\n
28<\/td>\n2. Subprograms and packages
2.1 Subprogram declarations <\/td>\n<\/tr>\n
31<\/td>\n2.2 Subprogram bodies <\/td>\n<\/tr>\n
33<\/td>\n2.3 Subprogram overloading <\/td>\n<\/tr>\n
36<\/td>\n2.4 Resolution functions <\/td>\n<\/tr>\n
37<\/td>\n2.5 Package declarations <\/td>\n<\/tr>\n
38<\/td>\n2.6 Package bodies <\/td>\n<\/tr>\n
39<\/td>\n2.7 Conformance rules <\/td>\n<\/tr>\n
40<\/td>\n3. Types and natures <\/td>\n<\/tr>\n
41<\/td>\n3.1 Scalar Types <\/td>\n<\/tr>\n
47<\/td>\n3.2 Composite types <\/td>\n<\/tr>\n
52<\/td>\n3.3 Access types <\/td>\n<\/tr>\n
54<\/td>\n3.4 File types <\/td>\n<\/tr>\n
57<\/td>\n3.5 Natures <\/td>\n<\/tr>\n
60<\/td>\n4. Declarations
4.1 Type declarations <\/td>\n<\/tr>\n
61<\/td>\n4.2 Subtype declarations <\/td>\n<\/tr>\n
62<\/td>\n4.3 Objects <\/td>\n<\/tr>\n
80<\/td>\n4.4 Attribute declarations <\/td>\n<\/tr>\n
81<\/td>\n4.5 Component declarations
4.6 Group template declarations <\/td>\n<\/tr>\n
82<\/td>\n4.7 Group declarations
4.8 Nature declaration <\/td>\n<\/tr>\n
83<\/td>\n5. Specifications <\/td>\n<\/tr>\n
84<\/td>\n5.1 Attribute specification <\/td>\n<\/tr>\n
86<\/td>\n5.2 Configuration specification <\/td>\n<\/tr>\n
93<\/td>\n5.3 Disconnection specification <\/td>\n<\/tr>\n
95<\/td>\n5.4 Step limit specification <\/td>\n<\/tr>\n
98<\/td>\n6. Names
6.1 Names <\/td>\n<\/tr>\n
99<\/td>\n6.2 Simple names <\/td>\n<\/tr>\n
100<\/td>\n6.3 Selected names <\/td>\n<\/tr>\n
102<\/td>\n6.4 Indexed names
6.5 Slice names <\/td>\n<\/tr>\n
103<\/td>\n6.6 Attribute names <\/td>\n<\/tr>\n
104<\/td>\n7. Expressions
7.1 Rules for expressions <\/td>\n<\/tr>\n
105<\/td>\n7.2 Operators <\/td>\n<\/tr>\n
113<\/td>\n7.3 Operands <\/td>\n<\/tr>\n
119<\/td>\n7.4 Static expressions <\/td>\n<\/tr>\n
122<\/td>\n7.5 Universal expressions
7.6 Linear Forms <\/td>\n<\/tr>\n
125<\/td>\n8. Sequential statements
8.1 Wait statement <\/td>\n<\/tr>\n
127<\/td>\n8.2 Assertion statement <\/td>\n<\/tr>\n
128<\/td>\n8.3 Report statement
8.4 Signal assignment statement <\/td>\n<\/tr>\n
133<\/td>\n8.5 Variable assignment statement <\/td>\n<\/tr>\n
134<\/td>\n8.6 Procedure call statement <\/td>\n<\/tr>\n
135<\/td>\n8.7 If statement
8.8 Case statement <\/td>\n<\/tr>\n
136<\/td>\n8.9 Loop statement <\/td>\n<\/tr>\n
137<\/td>\n8.10 Next statement
8.11 Exit statement <\/td>\n<\/tr>\n
138<\/td>\n8.12 Return statement
8.13 Null statement <\/td>\n<\/tr>\n
139<\/td>\n8.14 Break statement <\/td>\n<\/tr>\n
140<\/td>\n9. Concurrent statements
9.1 Block statement <\/td>\n<\/tr>\n
141<\/td>\n9.2 Process statement <\/td>\n<\/tr>\n
142<\/td>\n9.3 Concurrent procedure call statements <\/td>\n<\/tr>\n
143<\/td>\n9.4 Concurrent assertion statements <\/td>\n<\/tr>\n
144<\/td>\n9.5 Concurrent signal assignment statements <\/td>\n<\/tr>\n
148<\/td>\n9.6 Component instantiation statements <\/td>\n<\/tr>\n
154<\/td>\n9.7 Generate statements <\/td>\n<\/tr>\n
155<\/td>\n9.8 Concurrent break statement <\/td>\n<\/tr>\n
157<\/td>\n10. Scope and visibility
10.1 Declarative region
10.2 Scope of declarations <\/td>\n<\/tr>\n
158<\/td>\n10.3 Visibility <\/td>\n<\/tr>\n
161<\/td>\n10.4 Use clauses <\/td>\n<\/tr>\n
162<\/td>\n10.5 The context of overload resolution <\/td>\n<\/tr>\n
164<\/td>\n11. Design units and their analysis
11.1 Design units
11.2 Design libraries <\/td>\n<\/tr>\n
165<\/td>\n11.3 Context clauses <\/td>\n<\/tr>\n
166<\/td>\n11.4 Order of analysis <\/td>\n<\/tr>\n
167<\/td>\n12. Elaboration and execution
12.1 Elaboration of a design hierarchy <\/td>\n<\/tr>\n
169<\/td>\n12.2 Elaboration of a block header <\/td>\n<\/tr>\n
170<\/td>\n12.3 Elaboration of a declarative part <\/td>\n<\/tr>\n
174<\/td>\n12.4 Elaboration of a statement part <\/td>\n<\/tr>\n
177<\/td>\n12.5 Dynamic elaboration <\/td>\n<\/tr>\n
178<\/td>\n12.6 Execution of a model <\/td>\n<\/tr>\n
189<\/td>\n12.7 Time and the analog solver <\/td>\n<\/tr>\n
190<\/td>\n12.8 Frequency and noise calculation <\/td>\n<\/tr>\n
192<\/td>\n13. Lexical elements
13.1 Character set <\/td>\n<\/tr>\n
195<\/td>\n13.2 Lexical elements, separators, and delimiters <\/td>\n<\/tr>\n
196<\/td>\n13.3 Identifiers <\/td>\n<\/tr>\n
197<\/td>\n13.4 Abstract literals <\/td>\n<\/tr>\n
198<\/td>\n13.5 Character literals <\/td>\n<\/tr>\n
199<\/td>\n13.6 String literals
13.7 Bit string literals <\/td>\n<\/tr>\n
200<\/td>\n13.8 Comments <\/td>\n<\/tr>\n
202<\/td>\n13.9 Reserved words <\/td>\n<\/tr>\n
203<\/td>\n13.10 Allowable replacements of characters <\/td>\n<\/tr>\n
204<\/td>\n14. Predefined language environment
14.1 Predefined attributes <\/td>\n<\/tr>\n
225<\/td>\n14.2 Package STANDARD <\/td>\n<\/tr>\n
231<\/td>\n14.3 Package TEXTIO <\/td>\n<\/tr>\n
235<\/td>\n15. Simultaneous statements
15.1 Simple simultaneous statement <\/td>\n<\/tr>\n
236<\/td>\n15.2 Simultaneous if statement
15.3 Simultaneous case statement <\/td>\n<\/tr>\n
237<\/td>\n15.4 Simultaneous procedural statement <\/td>\n<\/tr>\n
240<\/td>\n15.5 Simultaneous null statement <\/td>\n<\/tr>\n
241<\/td>\nAnnex A\u2014Syntax summary <\/td>\n<\/tr>\n
257<\/td>\nAnnex B\u2014Glossary <\/td>\n<\/tr>\n
277<\/td>\nAnnex C\u2014Potentially nonportable constructs <\/td>\n<\/tr>\n
278<\/td>\nAnnex D\u2014Changes from IEEE Std 1076-1987 <\/td>\n<\/tr>\n
279<\/td>\nAnnex E\u2014Bibliography <\/td>\n<\/tr>\n
280<\/td>\nINDEX <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard VHDL Analog and Mixed-Signal Extensions<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n1999<\/td>\n298<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":79709,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-79708","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/79708","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/79709"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=79708"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=79708"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=79708"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}