{"id":79812,"date":"2024-10-17T18:38:10","date_gmt":"2024-10-17T18:38:10","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1149-1-1990\/"},"modified":"2024-10-24T19:41:27","modified_gmt":"2024-10-24T19:41:27","slug":"ieee-1149-1-1990","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1149-1-1990\/","title":{"rendered":"IEEE 1149.1 1990"},"content":{"rendered":"

Revision Standard – Inactive – Superseded. Circuitry that may be built into an integrated circuit to assist in the test, maintenance, and support of assembled printed circuit boards is defined. The circuitry includes a standard interface through which instructions and test data are communicated. A set of test features is defined, including a boundary-scan register, such that the component is able to respond to a minimum set of instructions designed to assist with testing of assembled printed circuit boards.<\/p>\n

PDF Catalog<\/h4>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
1<\/td>\nTitle Page <\/td>\n<\/tr>\n
3<\/td>\nForeword
Participants <\/td>\n<\/tr>\n
11<\/td>\nCONTENTS <\/td>\n<\/tr>\n
13<\/td>\n1. Introduction
1.1 Background Reading
1.2 An Overview of the Operation of IEEE Std 1149.1 <\/td>\n<\/tr>\n
14<\/td>\n1.3 The Use of IEEE Std 1149.1 to Test an Assembled Product <\/td>\n<\/tr>\n
17<\/td>\n1.4 The Use of IEEE Std 1149.1 to Achieve Other Test Goals
2. General Information
2.1 Document Outline <\/td>\n<\/tr>\n
18<\/td>\n2.2 Conventions
2.3 Definitions <\/td>\n<\/tr>\n
21<\/td>\n2.4 References
3. The Test Access Port (TAP)
3.1 Connections That Form the Test Access Port (TAP)
3.2 The Test Clock Input\u2014TCK <\/td>\n<\/tr>\n
22<\/td>\n3.3 The Test Mode Select Input\u2014TMS <\/td>\n<\/tr>\n
23<\/td>\n3.4 The Test Data Input\u2014TDI
3.5 The Test Data Output\u2014TDO <\/td>\n<\/tr>\n
24<\/td>\n3.6 The Test Reset Input\u2014TRST* <\/td>\n<\/tr>\n
25<\/td>\n3.7 Interconnection of Components Compatible With This Standard <\/td>\n<\/tr>\n
26<\/td>\n3.8 Subordination of This Standard Within a Higher Level Test Strategy <\/td>\n<\/tr>\n
27<\/td>\n4. Test Logic Architecture <\/td>\n<\/tr>\n
28<\/td>\n4.1 Test Logic Design <\/td>\n<\/tr>\n
29<\/td>\n4.2 Test Logic Realization <\/td>\n<\/tr>\n
30<\/td>\n5. The TAP Controller
5.1 TAP Controller State Diagram <\/td>\n<\/tr>\n
35<\/td>\n5.2 TAP Controller Operation <\/td>\n<\/tr>\n
43<\/td>\n5.3 TAP Controller Initialization <\/td>\n<\/tr>\n
44<\/td>\n6. The Instruction Register
6.1 Design and Construction of the Instruction Register <\/td>\n<\/tr>\n
45<\/td>\n6.2 Instruction Register Operation <\/td>\n<\/tr>\n
47<\/td>\n7. Instructions
7.1 Response of the Test Logic to Instructions <\/td>\n<\/tr>\n
48<\/td>\n7.2 Public Instructions <\/td>\n<\/tr>\n
49<\/td>\n7.3 Private Instructions
7.4 The <\/td>\n<\/tr>\n
50<\/td>\n7.5 Boundary-Scan Register Instructions <\/td>\n<\/tr>\n
54<\/td>\n7.6 The <\/td>\n<\/tr>\n
55<\/td>\n7.7 The <\/td>\n<\/tr>\n
60<\/td>\n7.8 The <\/td>\n<\/tr>\n
64<\/td>\n7.9 The <\/td>\n<\/tr>\n
66<\/td>\n7.10 The <\/td>\n<\/tr>\n
67<\/td>\n7.11 Device Identification Register Instructions
7.12 The <\/td>\n<\/tr>\n
68<\/td>\n7.13 The <\/td>\n<\/tr>\n
69<\/td>\n7.14 The <\/td>\n<\/tr>\n
70<\/td>\n8. Test Data Registers <\/td>\n<\/tr>\n
71<\/td>\n8.1 Provision of Test Data Registers <\/td>\n<\/tr>\n
73<\/td>\n8.2 Design and Construction of Test Data Registers <\/td>\n<\/tr>\n
74<\/td>\n8.3 Test Data Register Operation <\/td>\n<\/tr>\n
76<\/td>\n9. The Bypass Register
9.1 Design and Operation of the Bypass Register <\/td>\n<\/tr>\n
77<\/td>\n10. The Boundary-Scan Register <\/td>\n<\/tr>\n
78<\/td>\n10.1 Introduction to This Chapter <\/td>\n<\/tr>\n
82<\/td>\n10.2 Register Design <\/td>\n<\/tr>\n
84<\/td>\n10.3 Register Operation <\/td>\n<\/tr>\n
85<\/td>\n10.4 General Rules Regarding Cell Provision <\/td>\n<\/tr>\n
88<\/td>\n10.5 Provision and Operation of Cells at System Logic Inputs <\/td>\n<\/tr>\n
96<\/td>\n10.6 Provision and Operation of Cells at System Logic Outputs <\/td>\n<\/tr>\n
111<\/td>\n10.7 Bidirectional Signals <\/td>\n<\/tr>\n
116<\/td>\n10.8 Redundant Cells <\/td>\n<\/tr>\n
117<\/td>\n10.9 Special Cases <\/td>\n<\/tr>\n
119<\/td>\n11. The Device Identification Register <\/td>\n<\/tr>\n
120<\/td>\n11.1 Design and Operation of the Device Identification Register <\/td>\n<\/tr>\n
122<\/td>\n11.2 Manufacturer Identity Code <\/td>\n<\/tr>\n
123<\/td>\n11.3 Part-Number Code
11.4 Version Code
12. Conformance and Documentation Requirements
12.1 Claiming Conformance to This Standard <\/td>\n<\/tr>\n
124<\/td>\n12.2 Prime and Second Source Components <\/td>\n<\/tr>\n
125<\/td>\n12.3 Documentation Requirements <\/td>\n<\/tr>\n
128<\/td>\nAnnex A An Example Implementation Using Level-Sensitive Design Techniques <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard Test Access Port and Boundary-Scan Architecture<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n1990<\/td>\n139<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":79813,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-79812","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/79812","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/79813"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=79812"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=79812"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=79812"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}