{"id":79993,"date":"2024-10-17T18:39:52","date_gmt":"2024-10-17T18:39:52","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1284-3-2001\/"},"modified":"2024-10-24T19:42:03","modified_gmt":"2024-10-24T19:42:03","slug":"ieee-1284-3-2001","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1284-3-2001\/","title":{"rendered":"IEEE 1284.3 2001"},"content":{"rendered":"
New IEEE Standard – Inactive – Withdrawn. Administratively Withdrawn February 2006 System extensions consistent with the implementation and functionality of IEEE Std 1284-2000 are covered. Multiport expansion architectures, daisy chains, an application and devicedriver programming interface architecture, and data link layer services are explored.<\/p>\n
PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
---|---|---|---|---|---|---|---|
1<\/td>\n | Title Page <\/td>\n<\/tr>\n | ||||||
3<\/td>\n | Introduction Participants <\/td>\n<\/tr>\n | ||||||
5<\/td>\n | CONTENTS <\/td>\n<\/tr>\n | ||||||
7<\/td>\n | 1. Overview 1.1 Scope 1.2 Purpose <\/td>\n<\/tr>\n | ||||||
8<\/td>\n | 2. References 3. Definitions 3.1 General terminology <\/td>\n<\/tr>\n | ||||||
10<\/td>\n | 3.2 Acronyms 3.3 Communication modes 4. Features and compliance 4.1 Overview <\/td>\n<\/tr>\n | ||||||
11<\/td>\n | 4.2 Multiport (MP) <\/td>\n<\/tr>\n | ||||||
12<\/td>\n | 4.3 Service provider interface (SPI) features 4.4 Data link layer features <\/td>\n<\/tr>\n | ||||||
13<\/td>\n | 4.5 Physical interface 4.6 Compliance <\/td>\n<\/tr>\n | ||||||
14<\/td>\n | 5. Port-sharing protocols 5.1 Overview 5.2 Command packet protocol (CPP) <\/td>\n<\/tr>\n | ||||||
20<\/td>\n | 5.3 DC architecture <\/td>\n<\/tr>\n | ||||||
35<\/td>\n | 5.4 Multiplexor architecture <\/td>\n<\/tr>\n | ||||||
50<\/td>\n | 5.5 Global reset 6. Service provider interface (SPI) 6.1 Overview <\/td>\n<\/tr>\n | ||||||
51<\/td>\n | 6.2 SPI Client interface definition <\/td>\n<\/tr>\n | ||||||
57<\/td>\n | 6.3 SPI hardware interface definition <\/td>\n<\/tr>\n | ||||||
59<\/td>\n | 7. Data link layer 7.1 Overview 7.2 Data link SPI <\/td>\n<\/tr>\n | ||||||
61<\/td>\n | 7.3 Wire protocol <\/td>\n<\/tr>\n | ||||||
63<\/td>\n | 8. Additional IEEE 1284 modes 8.1 Bounded extended capabilities port (BECP) mode 8.2 Channelized nibble mode <\/td>\n<\/tr>\n | ||||||
65<\/td>\n | Annex A (informative) – Enhanced parallel port (EPP) BIOS <\/td>\n<\/tr>\n | ||||||
70<\/td>\n | Annex B (informative) – SPI usage examples <\/td>\n<\/tr>\n | ||||||
74<\/td>\n | Annex C (informative) – Bibliography <\/td>\n<\/tr>\n | ||||||
75<\/td>\n | Annex D (normative) – Signal transition events <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" IEEE Standard for Interface and Protocol Extensions to IEEE Std 1284 Compliant Peripherals and Host Adapters<\/b><\/p>\n |