{"id":80107,"date":"2024-10-17T18:41:00","date_gmt":"2024-10-17T18:41:00","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1394-1996\/"},"modified":"2024-10-24T19:42:28","modified_gmt":"2024-10-24T19:42:28","slug":"ieee-1394-1996","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1394-1996\/","title":{"rendered":"IEEE 1394 1996"},"content":{"rendered":"

New IEEE Standard – Inactive – Superseded. A high-speed serial bus that interates well with most IEEE standard 32-bit and 64-bit parallel buses, as well as such nonbus interconnects as the IEEE Std 1596-1992, Scalable Coherent Interface, is specified. It is intended to provide a low-cost interconnect between cards on the same backplane, cards on other backplanes, and external peripherals. This standard follows the IEEE Std 1212-1991 Command and Status Register (CSR) architecture.<\/p>\n

PDF Catalog<\/h4>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
1<\/td>\nTitle Page <\/td>\n<\/tr>\n
3<\/td>\nIntroduction <\/td>\n<\/tr>\n
4<\/td>\nParticipants <\/td>\n<\/tr>\n
7<\/td>\nCONTENTS <\/td>\n<\/tr>\n
9<\/td>\n1. Overview
1.1 Scope
1.2 References <\/td>\n<\/tr>\n
10<\/td>\n1.3 Document organization
1.4 Serial Bus applications <\/td>\n<\/tr>\n
11<\/td>\n1.5 Service model <\/td>\n<\/tr>\n
12<\/td>\n1.6 Document notation <\/td>\n<\/tr>\n
19<\/td>\n1.7 Compliance <\/td>\n<\/tr>\n
20<\/td>\n2. Definitions and abbreviations
2.1 Conformance glossary
2.2 Technical glossary <\/td>\n<\/tr>\n
24<\/td>\n3. Summary description <\/td>\n<\/tr>\n
25<\/td>\n3.1 Node and module architectures
3.2 Topology <\/td>\n<\/tr>\n
27<\/td>\n3.3 Addressing
3.4 Protocol architecture <\/td>\n<\/tr>\n
29<\/td>\n3.5 Transaction layer <\/td>\n<\/tr>\n
32<\/td>\n3.6 Link layer <\/td>\n<\/tr>\n
39<\/td>\n3.7 Physical layer <\/td>\n<\/tr>\n
53<\/td>\n3.8 Bus management <\/td>\n<\/tr>\n
54<\/td>\n4. Cable PHY specification
4.1 Cable PHY services <\/td>\n<\/tr>\n
58<\/td>\n4.2 Cable physical connection specification <\/td>\n<\/tr>\n
89<\/td>\n4.3 Cable PHY facilities <\/td>\n<\/tr>\n
100<\/td>\n4.4 Cable PHY operation <\/td>\n<\/tr>\n
123<\/td>\n5. Backplane PHY specification
5.1 Backplane PHY services <\/td>\n<\/tr>\n
127<\/td>\n5.2 Backplane physical connection specification <\/td>\n<\/tr>\n
136<\/td>\n5.3 Backplane PHY facilities <\/td>\n<\/tr>\n
139<\/td>\n5.4 Backplane PHY operation <\/td>\n<\/tr>\n
146<\/td>\n5.5 Backplane initialization and reset <\/td>\n<\/tr>\n
147<\/td>\n6. Link layer specification
6.1 Link layer services <\/td>\n<\/tr>\n
153<\/td>\n6.2 Link layer facilities <\/td>\n<\/tr>\n
174<\/td>\n6.3 Link layer operation <\/td>\n<\/tr>\n
183<\/td>\n6.4 Link layer reference code <\/td>\n<\/tr>\n
185<\/td>\n7. Transaction layer specification
7.1 Transaction layer services <\/td>\n<\/tr>\n
188<\/td>\n7.2 Transaction facilities <\/td>\n<\/tr>\n
189<\/td>\n7.3 Transaction operation <\/td>\n<\/tr>\n
211<\/td>\n7.4 CSR Architecture transactions mapped to Serial Bus
8. Serial Bus management specification
8.1 Serial Bus management summary <\/td>\n<\/tr>\n
212<\/td>\n8.2 Serial Bus management services <\/td>\n<\/tr>\n
215<\/td>\n8.3 Serial Bus management facilities <\/td>\n<\/tr>\n
242<\/td>\n8.4 Serial Bus management operations <\/td>\n<\/tr>\n
252<\/td>\n8.5 Bus configuration state machines (cable environment) <\/td>\n<\/tr>\n
258<\/td>\nAnnex A Cable environment system properties <\/td>\n<\/tr>\n
267<\/td>\nAnnex B External connector positive retention <\/td>\n<\/tr>\n
269<\/td>\nAnnex C Internal device physical interface <\/td>\n<\/tr>\n
299<\/td>\nAnnex D Backplane PHY timing formulas <\/td>\n<\/tr>\n
309<\/td>\nAnnex E Cable operation and implementation examples <\/td>\n<\/tr>\n
328<\/td>\nAnnex F Backplane physical implementation example <\/td>\n<\/tr>\n
334<\/td>\nAnnex G Backplane isochronous resource manager selection <\/td>\n<\/tr>\n
336<\/td>\nAnnex H Serial Bus configuration in the cable environment <\/td>\n<\/tr>\n
344<\/td>\nAnnex I Socket PCB terminal patterns and mounting <\/td>\n<\/tr>\n
350<\/td>\nAnnex J PHY-link interface specification <\/td>\n<\/tr>\n
368<\/td>\nAnnex K Serial Bus cable test procedures <\/td>\n<\/tr>\n
387<\/td>\nAnnex L Shielding effectiveness and transfer impedance testing <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard for a High Performance Serial Bus<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n1996<\/td>\n392<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":80108,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-80107","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/80107","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/80108"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=80107"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=80107"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=80107"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}