{"id":80269,"date":"2024-10-17T18:42:39","date_gmt":"2024-10-17T18:42:39","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1596-4-1996\/"},"modified":"2024-10-24T19:42:58","modified_gmt":"2024-10-24T19:42:58","slug":"ieee-1596-4-1996","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1596-4-1996\/","title":{"rendered":"IEEE 1596.4 1996"},"content":{"rendered":"
New IEEE Standard – Inactive – Withdrawn. A high-bandwidth interface optimized for interchanging data between a memory controller and one or more dynamic RAMs is specified. RamLink is an applicable interface for other RAM-like devices as well. You will receive an email from Customer Service with the URL needed to access this publication online.<\/p>\n
PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
---|---|---|---|---|---|---|---|
1<\/td>\n | Title Page <\/td>\n<\/tr>\n | ||||||
3<\/td>\n | Introduction <\/td>\n<\/tr>\n | ||||||
4<\/td>\n | Participants <\/td>\n<\/tr>\n | ||||||
6<\/td>\n | CONTENTS <\/td>\n<\/tr>\n | ||||||
8<\/td>\n | 1. Overview 1.1 Scope <\/td>\n<\/tr>\n | ||||||
9<\/td>\n | 1.2 Purpose 1.3 Document structure <\/td>\n<\/tr>\n | ||||||
10<\/td>\n | 1.4 Objectives <\/td>\n<\/tr>\n | ||||||
11<\/td>\n | 1.5 Expected applications <\/td>\n<\/tr>\n | ||||||
14<\/td>\n | 2. References 3. Definitions 3.1 Conformance levels 3.2 Definitions of RAM and interconnect-related terms <\/td>\n<\/tr>\n | ||||||
17<\/td>\n | 3.3 Bit and byte ordering within packets <\/td>\n<\/tr>\n | ||||||
18<\/td>\n | 3.4 Bit and byte ordering within CSRs 3.5 Field notation (italics and bold usage) 3.6 Numerical values <\/td>\n<\/tr>\n | ||||||
19<\/td>\n | 3.7 Signaling layers <\/td>\n<\/tr>\n | ||||||
20<\/td>\n | 4. RamLink configurations 4.1 Simple topologies 4.2 Hierarchical topologies <\/td>\n<\/tr>\n | ||||||
21<\/td>\n | 4.3 Hybrid signaling <\/td>\n<\/tr>\n | ||||||
22<\/td>\n | 4.4 Wide (9-bit) data transfers <\/td>\n<\/tr>\n | ||||||
23<\/td>\n | 4.5 DRAM error-checking options <\/td>\n<\/tr>\n | ||||||
25<\/td>\n | 4.6 Link error-checking <\/td>\n<\/tr>\n | ||||||
26<\/td>\n | 5. RamLink operation 5.1 Split-response transactions <\/td>\n<\/tr>\n | ||||||
27<\/td>\n | 5.2 Response scheduling 5.3 Retried transactions 5.4 RamLink address space <\/td>\n<\/tr>\n | ||||||
28<\/td>\n | 5.5 Address errors <\/td>\n<\/tr>\n | ||||||
29<\/td>\n | 5.6 Request queue sizes 5.7 Request ordering <\/td>\n<\/tr>\n | ||||||
30<\/td>\n | 5.8 Refresh operations <\/td>\n<\/tr>\n | ||||||
31<\/td>\n | 5.9 Rate adjustments <\/td>\n<\/tr>\n | ||||||
32<\/td>\n | 6. Packet formats 6.1 Packet components <\/td>\n<\/tr>\n | ||||||
36<\/td>\n | 6.2 Request packet formats <\/td>\n<\/tr>\n | ||||||
38<\/td>\n | 6.3 Copy packet <\/td>\n<\/tr>\n | ||||||
39<\/td>\n | 6.4 Event packets <\/td>\n<\/tr>\n | ||||||
42<\/td>\n | 6.5 Response packets <\/td>\n<\/tr>\n | ||||||
44<\/td>\n | 6.6 Retry packet format 6.7 Idle packets <\/td>\n<\/tr>\n | ||||||
45<\/td>\n | 6.8 Special initialization packets <\/td>\n<\/tr>\n | ||||||
46<\/td>\n | 7. RamLink initialization 7.1 standBy mode 7.2 shutDown mode <\/td>\n<\/tr>\n | ||||||
47<\/td>\n | 7.3 shutOff recovery <\/td>\n<\/tr>\n | ||||||
48<\/td>\n | 7.4 Self test and initialize <\/td>\n<\/tr>\n | ||||||
49<\/td>\n | Annex A Bibliography <\/td>\n<\/tr>\n | ||||||
50<\/td>\n | Annex B RingLink signaling <\/td>\n<\/tr>\n | ||||||
58<\/td>\n | Annex C SyncLink signals <\/td>\n<\/tr>\n | ||||||
63<\/td>\n | Annex D Control and status <\/td>\n<\/tr>\n | ||||||
74<\/td>\n | Annex E I\/O extensions <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" IEEE Standard for High-Bandwidth Memory Interface Based on Scalable Coherent Interface (SCI) Signaling Technology (RamLink)<\/b><\/p>\n |