{"id":82713,"date":"2024-10-18T03:08:06","date_gmt":"2024-10-18T03:08:06","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-696-1983\/"},"modified":"2024-10-24T19:51:09","modified_gmt":"2024-10-24T19:51:09","slug":"ieee-696-1983","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-696-1983\/","title":{"rendered":"IEEE 696 1983"},"content":{"rendered":"

New IEEE Standard – Inactive – Withdrawn. This standard applies to interface systems for computer system components interconnected by way of a 100-line parallel backplane commonly known as the S-100 bus. It applies to microprocessor computer systems, or portions of them, where: (1) Data exchanged among the interconnected devices is digital. (2) A maximum of 22 devices are interconnected. (3) The total transmission path length among interconnected devices is less than or equal to 25 in (63.5 cm). (4) The maximum switching rate of any signal on the bus is less than or equal to 6 MHz Withdrawn standard<\/p>\n

PDF Catalog<\/h4>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
8<\/td>\nGeneral
1.1 Scope
1.2 Object
1.3 Definitions
1.3.1 General-System Terms
1.3.2 Signals and Paths <\/td>\n<\/tr>\n
9<\/td>\nState Diagram Notation <\/td>\n<\/tr>\n
10<\/td>\n1.5 Logical and Electrical State Relationships
Table 1 Active High Signals
Table2 ActiveLowSignals <\/td>\n<\/tr>\n
11<\/td>\nInterface System Overview
Interface System Objective
Fundamental Communication Capabilities
1.6.3 Message Paths and Bus Structure
Functional Specifications
2.1 Functional Partition
Table 3 Bus Structures <\/td>\n<\/tr>\n
12<\/td>\n2.2 SignalLines
2.2.1 General
2.2.2 Address Bus
Table 4 Address Usage for Different Bus Cycles
Fig <\/td>\n<\/tr>\n
13<\/td>\n2.2.3 Status Bus
Table 5 Status Usage Chart
Fig <\/td>\n<\/tr>\n
14<\/td>\n2.2.4 DataBus
Control Output Bus
2.2.6 Control Input Bus <\/td>\n<\/tr>\n
15<\/td>\nTable 6 IEEE Std 696 Bus Pin List <\/td>\n<\/tr>\n
18<\/td>\n2.2.7 TMA Control Bus
2.2.8 Vectored Interrupt Bus
2.2.9 System Utilities <\/td>\n<\/tr>\n
19<\/td>\n2.2.10 PinList
2.3 The Permanent Master Interface
2.3.1 General <\/td>\n<\/tr>\n
20<\/td>\nPermanent Master State Diagram
2.3.3 Permanent Master State Descriptions
Permanent Master State Diagram <\/td>\n<\/tr>\n
21<\/td>\nRequired Signals for Permanent Masters
2.3.5 Dummy Mastering
The Temporary Master Interface
2.4.1 General
Temporary Master State Diagram
Temporary Master State Descriptions
Temporary Master State Diagram <\/td>\n<\/tr>\n
22<\/td>\nRequired Signals For Temporary Masters
2.5 The Slave Interface
2.5.1 Slave-Interface State Diagram
2.5.2 Slave-State Definitions
Slave Interface State Diagram <\/td>\n<\/tr>\n
23<\/td>\nRequired Signals for Slave Interfaces
2.6 8\/16-bit Data Transfer Control
2.6.1 General
2.6.2 8-bit Data Paths
2.6.3 l6-bit Data Paths
2.6.4 Memory Organization <\/td>\n<\/tr>\n
24<\/td>\n8\/16 Bit-Memory Organization
8\/16 Bit Address + Data Usage <\/td>\n<\/tr>\n
25<\/td>\n2.6.5 Sixteen Acknowledge (SIXTN*)
2.7 Fundamental Bus-Cycle Timing
2.7.1 General
2.7.2 Address and Status Buses
Bus-Cycle Fundamental Timing Relationships <\/td>\n<\/tr>\n
26<\/td>\n2.7.3 Ready and Sixteen Acknowledge Lines
2.7.4 Read Cycles
2.7.5 Writecycles <\/td>\n<\/tr>\n
27<\/td>\nSpecial Bus Operations
2.8.1 General
2.8.2 Bus Transfer Protocol
Bus-Transfer State Diagram <\/td>\n<\/tr>\n
28<\/td>\nTMATiming
Table 7 Control Output Line Levels <\/td>\n<\/tr>\n
29<\/td>\n2.8.3 Bus Arbitration Protocol
Arbitration Diagram <\/td>\n<\/tr>\n
30<\/td>\nBus Arbitration Example <\/td>\n<\/tr>\n
31<\/td>\nBus Arbitration Timing Diagrams <\/td>\n<\/tr>\n
32<\/td>\n2.8.4 Summary of Arbitration Protocol
2.9 Interrupt Protocol
2.9.1 Vectored Interrupts <\/td>\n<\/tr>\n
33<\/td>\nNonmaskable Interrupt (NMI*)
2.10 Special Condition Lines
2.10.1 Power-fail Pending (PWRFAIL”)
2.10.2 ERROR*
3 Electrical Specifications
3.1 Application
3.2 PowerDistribution
3.2.1 +8 V Specification
3.2.2 +16 V Specification
3.2.3 –
3.2.3 – 16 V Specification <\/td>\n<\/tr>\n
34<\/td>\n3.3 General Signal Discipline
3.4 Driver Requirements
3.4.1 Driver Types
3.4.2 Driver Specifications
3.5 Receiver Specifications
3.6 Bidirectional Signals
3.7 Card-Level Bus Loading
Read Cycle Timing Specification
Write-Cycle Timing Specification <\/td>\n<\/tr>\n
35<\/td>\nRead-Cycle Timing Diagram
Write-Cycle Timing Diagram <\/td>\n<\/tr>\n
36<\/td>\nTable 8 Read and Write Cycle Timing Parameters <\/td>\n<\/tr>\n
37<\/td>\n3.10 Ready and Sixteen Request Timing Specification
3.1 1 Bus Transfer Timing Specification
3.12 PHANTOM* Timing Specification
Timing of RDY XRDY and SIXTN* During Read and Write Cycles
Overlap of PHANTOM* and Read and Write Strobes
Table 9 Bus Transfer Timing Parameters <\/td>\n<\/tr>\n
38<\/td>\nMechanical Specifications
4.1 Application
4.2 ConnectorType
4.2.1 Electrical Considerations
4.2.2 Connector Spacing
4.3 Board Size Specification
Fig 16 IEEE Std 696 Board Mechanical Parameters <\/td>\n<\/tr>\n
40<\/td>\nQuick Reference IEEE Std 696 Bus Layout <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard 696 Interface Devices<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n1983<\/td>\n40<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":82714,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-82713","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/82713","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/82714"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=82713"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=82713"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=82713"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}