{"id":454135,"date":"2024-10-20T09:33:53","date_gmt":"2024-10-20T09:33:53","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/bs-iec-61523-42023\/"},"modified":"2024-10-26T17:45:28","modified_gmt":"2024-10-26T17:45:28","slug":"bs-iec-61523-42023","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/bsi\/bs-iec-61523-42023\/","title":{"rendered":"BS IEC 61523-4:2023"},"content":{"rendered":"
PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
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2<\/td>\n | undefined <\/td>\n<\/tr>\n | ||||||
4<\/td>\n | Contents <\/td>\n<\/tr>\n | ||||||
17<\/td>\n | 1. Overview 1.1 Scope 1.2 Purpose 1.3 Key characteristics of the Unified Power Format <\/td>\n<\/tr>\n | ||||||
19<\/td>\n | 1.4 Contents of this standard <\/td>\n<\/tr>\n | ||||||
20<\/td>\n | 2. Normative references 3. Definitions, acronyms, and abbreviations 3.1 Definitions <\/td>\n<\/tr>\n | ||||||
26<\/td>\n | 3.2 Acronyms and abbreviations <\/td>\n<\/tr>\n | ||||||
27<\/td>\n | 4. Concepts 4.1 Introduction <\/td>\n<\/tr>\n | ||||||
28<\/td>\n | 4.2 Design structure 4.3 Design representation <\/td>\n<\/tr>\n | ||||||
32<\/td>\n | 4.4 Power architecture <\/td>\n<\/tr>\n | ||||||
35<\/td>\n | 4.5 Power distribution <\/td>\n<\/tr>\n | ||||||
43<\/td>\n | 4.6 Power management <\/td>\n<\/tr>\n | ||||||
48<\/td>\n | 4.7 Supply states and power states <\/td>\n<\/tr>\n | ||||||
55<\/td>\n | 4.8 Simstates <\/td>\n<\/tr>\n | ||||||
56<\/td>\n | 4.9 Power intent specification <\/td>\n<\/tr>\n | ||||||
62<\/td>\n | 5. Language basics 5.1 UPF is Tcl <\/td>\n<\/tr>\n | ||||||
63<\/td>\n | 5.2 Conventions used <\/td>\n<\/tr>\n | ||||||
65<\/td>\n | 5.3 Lexical elements <\/td>\n<\/tr>\n | ||||||
69<\/td>\n | 5.4 Boolean expressions <\/td>\n<\/tr>\n | ||||||
71<\/td>\n | 5.5 Object declaration 5.6 Attributes of objects <\/td>\n<\/tr>\n | ||||||
76<\/td>\n | 5.7 Precedence <\/td>\n<\/tr>\n | ||||||
79<\/td>\n | 5.8 Generic UPF command semantics <\/td>\n<\/tr>\n | ||||||
80<\/td>\n | 5.9 effective_element_list semantics <\/td>\n<\/tr>\n | ||||||
83<\/td>\n | 5.10 Command refinement <\/td>\n<\/tr>\n | ||||||
84<\/td>\n | 5.11 Error handling 5.12 Units 5.13 SystemC language basic <\/td>\n<\/tr>\n | ||||||
85<\/td>\n | 6. Power intent commands 6.1 Introduction 6.2 Categories <\/td>\n<\/tr>\n | ||||||
86<\/td>\n | 6.3 add_parameter <\/td>\n<\/tr>\n | ||||||
87<\/td>\n | 6.4 add_port_state (legacy) <\/td>\n<\/tr>\n | ||||||
88<\/td>\n | 6.5 add_power_state <\/td>\n<\/tr>\n | ||||||
95<\/td>\n | 6.6 add_pst_state (legacy) <\/td>\n<\/tr>\n | ||||||
96<\/td>\n | 6.7 add_state_transition <\/td>\n<\/tr>\n | ||||||
98<\/td>\n | 6.8 add_supply_state <\/td>\n<\/tr>\n | ||||||
99<\/td>\n | 6.9 apply_power_model <\/td>\n<\/tr>\n | ||||||
101<\/td>\n | 6.10 associate_supply_set <\/td>\n<\/tr>\n | ||||||
103<\/td>\n | 6.11 begin_power_model (legacy) <\/td>\n<\/tr>\n | ||||||
104<\/td>\n | 6.12 bind_checker <\/td>\n<\/tr>\n | ||||||
106<\/td>\n | 6.13 connect_logic_net <\/td>\n<\/tr>\n | ||||||
108<\/td>\n | 6.14 connect_supply_net <\/td>\n<\/tr>\n | ||||||
110<\/td>\n | 6.15 connect_supply_set <\/td>\n<\/tr>\n | ||||||
111<\/td>\n | 6.16 create_composite_domain <\/td>\n<\/tr>\n | ||||||
113<\/td>\n | 6.17 create_hdl2upf_vct <\/td>\n<\/tr>\n | ||||||
114<\/td>\n | 6.18 create_logic_net <\/td>\n<\/tr>\n | ||||||
115<\/td>\n | 6.19 create_logic_port <\/td>\n<\/tr>\n | ||||||
116<\/td>\n | 6.20 create_power_domain <\/td>\n<\/tr>\n | ||||||
123<\/td>\n | 6.21 create_power_state_group <\/td>\n<\/tr>\n | ||||||
125<\/td>\n | 6.22 create_power_switch <\/td>\n<\/tr>\n | ||||||
132<\/td>\n | 6.23 create_pst (legacy) <\/td>\n<\/tr>\n | ||||||
133<\/td>\n | 6.24 create_supply_net <\/td>\n<\/tr>\n | ||||||
137<\/td>\n | 6.25 create_supply_port <\/td>\n<\/tr>\n | ||||||
138<\/td>\n | 6.26 create_supply_set <\/td>\n<\/tr>\n | ||||||
140<\/td>\n | 6.27 create_upf2hdl_vct <\/td>\n<\/tr>\n | ||||||
141<\/td>\n | 6.28 define_power_model <\/td>\n<\/tr>\n | ||||||
143<\/td>\n | 6.29 describe_state_transition (deprecated) 6.30 end_power_model (legacy) <\/td>\n<\/tr>\n | ||||||
144<\/td>\n | 6.31 find_objects <\/td>\n<\/tr>\n | ||||||
148<\/td>\n | 6.32 load_simstate_behavior <\/td>\n<\/tr>\n | ||||||
149<\/td>\n | 6.33 load_upf <\/td>\n<\/tr>\n | ||||||
150<\/td>\n | 6.34 load_upf_protected (deprecated) 6.35 map_power_switch <\/td>\n<\/tr>\n | ||||||
151<\/td>\n | 6.36 map_repeater_cell <\/td>\n<\/tr>\n | ||||||
152<\/td>\n | 6.37 map_retention_cell <\/td>\n<\/tr>\n | ||||||
156<\/td>\n | 6.38 name_format <\/td>\n<\/tr>\n | ||||||
157<\/td>\n | 6.39 save_upf <\/td>\n<\/tr>\n | ||||||
158<\/td>\n | 6.40 set_correlated <\/td>\n<\/tr>\n | ||||||
159<\/td>\n | 6.41 set_design_attributes <\/td>\n<\/tr>\n | ||||||
160<\/td>\n | 6.42 set_design_top <\/td>\n<\/tr>\n | ||||||
161<\/td>\n | 6.43 set_domain_supply_net (legacy) <\/td>\n<\/tr>\n | ||||||
162<\/td>\n | 6.44 set_equivalent <\/td>\n<\/tr>\n | ||||||
164<\/td>\n | 6.45 set_isolation <\/td>\n<\/tr>\n | ||||||
171<\/td>\n | 6.46 set_level_shifter <\/td>\n<\/tr>\n | ||||||
177<\/td>\n | 6.47 set_partial_on_translation <\/td>\n<\/tr>\n | ||||||
179<\/td>\n | 6.48 set_port_attributes <\/td>\n<\/tr>\n | ||||||
185<\/td>\n | 6.49 set_repeater <\/td>\n<\/tr>\n | ||||||
189<\/td>\n | 6.50 set_retention <\/td>\n<\/tr>\n | ||||||
193<\/td>\n | 6.51 set_retention_elements <\/td>\n<\/tr>\n | ||||||
194<\/td>\n | 6.52 set_scope <\/td>\n<\/tr>\n | ||||||
195<\/td>\n | 6.53 set_simstate_behavior <\/td>\n<\/tr>\n | ||||||
198<\/td>\n | 6.54 set_variation <\/td>\n<\/tr>\n | ||||||
199<\/td>\n | 6.55 sim_assertion_control <\/td>\n<\/tr>\n | ||||||
201<\/td>\n | 6.56 sim_corruption_control <\/td>\n<\/tr>\n | ||||||
204<\/td>\n | 6.57 sim_replay_control <\/td>\n<\/tr>\n | ||||||
206<\/td>\n | 6.58 upf_version <\/td>\n<\/tr>\n | ||||||
207<\/td>\n | 6.59 use_interface_cell <\/td>\n<\/tr>\n | ||||||
209<\/td>\n | 7. Power-management cell definition commands 7.1 Introduction <\/td>\n<\/tr>\n | ||||||
210<\/td>\n | 7.2 define_always_on_cell <\/td>\n<\/tr>\n | ||||||
211<\/td>\n | 7.3 define_diode_clamp <\/td>\n<\/tr>\n | ||||||
212<\/td>\n | 7.4 define_isolation_cell <\/td>\n<\/tr>\n | ||||||
215<\/td>\n | 7.5 define_level_shifter_cell <\/td>\n<\/tr>\n | ||||||
220<\/td>\n | 7.6 define_power_switch_cell <\/td>\n<\/tr>\n | ||||||
222<\/td>\n | 7.7 define_retention_cell <\/td>\n<\/tr>\n | ||||||
224<\/td>\n | 8. UPF processing 8.1 Overview <\/td>\n<\/tr>\n | ||||||
225<\/td>\n | 8.2 Data requirements 8.3 Processing phases <\/td>\n<\/tr>\n | ||||||
229<\/td>\n | 8.4 Error checking 9. Simulation semantics 9.1 Supply network creation <\/td>\n<\/tr>\n | ||||||
231<\/td>\n | 9.2 Supply network simulation <\/td>\n<\/tr>\n | ||||||
232<\/td>\n | 9.3 Power state simulation <\/td>\n<\/tr>\n | ||||||
235<\/td>\n | 9.4 Power state transition detection <\/td>\n<\/tr>\n | ||||||
236<\/td>\n | 9.5 Simstate simulation <\/td>\n<\/tr>\n | ||||||
238<\/td>\n | 9.6 Transitioning from one simstate state to another <\/td>\n<\/tr>\n | ||||||
239<\/td>\n | 9.7 Simulation of retention <\/td>\n<\/tr>\n | ||||||
245<\/td>\n | 9.8 Simulation of isolation <\/td>\n<\/tr>\n | ||||||
246<\/td>\n | 9.9 Simulation of level-shifting 9.10 Simulation of repeaters 10. UPF information model 10.1 Overview <\/td>\n<\/tr>\n | ||||||
247<\/td>\n | 10.2 Components of UPF information model <\/td>\n<\/tr>\n | ||||||
248<\/td>\n | 10.3 Identifiers in information model (IDs) <\/td>\n<\/tr>\n | ||||||
251<\/td>\n | 10.4 Classification of objects <\/td>\n<\/tr>\n | ||||||
257<\/td>\n | 10.5 Example of design hierarchy <\/td>\n<\/tr>\n | ||||||
258<\/td>\n | 10.6 Object definitions <\/td>\n<\/tr>\n | ||||||
317<\/td>\n | 11. Information model application programmable interface (API) 11.1 Tcl interface <\/td>\n<\/tr>\n | ||||||
327<\/td>\n | 11.2 HDL interface <\/td>\n<\/tr>\n | ||||||
391<\/td>\n | Annex A (informative) Bibliography <\/td>\n<\/tr>\n | ||||||
392<\/td>\n | Annex B (normative) Value conversion tables B.1 Overview B.2 VHDL_SL2UPF B.3 UPF2VHDL_SL B.4 VHDL_SL2UPF_GNDZERO <\/td>\n<\/tr>\n | ||||||
393<\/td>\n | B.5 UPF_GNDZERO2VHDL_SL B.6 SV_LOGIC2UPF B.7 UPF2SV_LOGIC B.8 SV_LOGIC2UPF_GNDZERO B.9 UPF_GNDZERO2SV_LOGIC <\/td>\n<\/tr>\n | ||||||
394<\/td>\n | B.10 VHDL_TIED_HI B.11 SV_TIED_HI B.12 VHDL_TIED_LO B.13 SV_TIED_LO <\/td>\n<\/tr>\n | ||||||
395<\/td>\n | Annex C (informative) UPF query examples C.1 Overview C.2 Utility procs <\/td>\n<\/tr>\n | ||||||
396<\/td>\n | C.3 High-level procs <\/td>\n<\/tr>\n | ||||||
398<\/td>\n | C.4 Superseded UPF queries <\/td>\n<\/tr>\n | ||||||
400<\/td>\n | Annex D (informative) Replacing deprecated and legacy commands and options D.1 Overview D.2 Deprecated and legacy constructs <\/td>\n<\/tr>\n | ||||||
402<\/td>\n | D.3 Recommendations for replacing deprecated and legacy constructs <\/td>\n<\/tr>\n | ||||||
405<\/td>\n | Annex E (informative) Low-power design methodology E.1 Overview E.2 Simple System on Chip (SoC) example design <\/td>\n<\/tr>\n | ||||||
408<\/td>\n | E.3 Design, verification, and implementation flow <\/td>\n<\/tr>\n | ||||||
411<\/td>\n | E.4 Power intent of the example design <\/td>\n<\/tr>\n | ||||||
432<\/td>\n | Annex F (informative) Power-management cell definitions in UPF and Liberty F.1 Introduction F.2 define_always_on_cell <\/td>\n<\/tr>\n | ||||||
434<\/td>\n | F.3 define_diode_clamp <\/td>\n<\/tr>\n | ||||||
435<\/td>\n | F.4 define_isolation_cell <\/td>\n<\/tr>\n | ||||||
438<\/td>\n | F.5 define_level_shifter_cell <\/td>\n<\/tr>\n | ||||||
440<\/td>\n | F.6 define_power_switch_cell <\/td>\n<\/tr>\n | ||||||
442<\/td>\n | F.7 define_retention_cell <\/td>\n<\/tr>\n | ||||||
446<\/td>\n | Annex G (informative) Power-management cell modeling examples G.1 Overview G.2 Modeling always-on cells <\/td>\n<\/tr>\n | ||||||
452<\/td>\n | G.3 Modeling cells with internal diodes <\/td>\n<\/tr>\n | ||||||
454<\/td>\n | G.4 Modeling isolation cells <\/td>\n<\/tr>\n | ||||||
471<\/td>\n | G.5 Modeling level-shifters <\/td>\n<\/tr>\n | ||||||
488<\/td>\n | G.6 Modeling power-switch cells <\/td>\n<\/tr>\n | ||||||
498<\/td>\n | G.7 Modeling state retention cells <\/td>\n<\/tr>\n | ||||||
510<\/td>\n | Annex H (informative) IP power modeling for system-level design H.1 Introduction H.2 Overview of system-level IP power models <\/td>\n<\/tr>\n | ||||||
511<\/td>\n | H.3 Content of system-level IP power models <\/td>\n<\/tr>\n | ||||||
512<\/td>\n | H.4 Power calculation using power functions <\/td>\n<\/tr>\n | ||||||
514<\/td>\n | H.5 Power model structure <\/td>\n<\/tr>\n | ||||||
515<\/td>\n | H.6 Power model instantiation\u2014example approach <\/td>\n<\/tr>\n | ||||||
517<\/td>\n | Annex I (normative) Switching Activity Interchange Format <\/td>\n<\/tr>\n | ||||||
518<\/td>\n | I.1 Syntactic conventions <\/td>\n<\/tr>\n | ||||||
519<\/td>\n | I.2 Lexical conventions <\/td>\n<\/tr>\n | ||||||
522<\/td>\n | I.3 Backward SAIF file <\/td>\n<\/tr>\n | ||||||
538<\/td>\n | I.4 Library forward SAIF file <\/td>\n<\/tr>\n | ||||||
546<\/td>\n | I.5 RTL forward SAIF file <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Delay and power calculation standards – Design and Verification of Low-Power, Energy-Aware Electronic Systems<\/b><\/p>\n |