{"id":80965,"date":"2024-10-17T18:49:51","date_gmt":"2024-10-17T18:49:51","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1394-1-2005\/"},"modified":"2024-10-24T19:45:16","modified_gmt":"2024-10-24T19:45:16","slug":"ieee-1394-1-2005","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1394-1-2005\/","title":{"rendered":"IEEE 1394.1 2005"},"content":{"rendered":"

Revision Standard – Active. The model, definition, and behaviors of High Performance Serial Bus bridges, which are devices that can be used to interconnect two separately enumerable buses, are specified.<\/p>\n

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
1<\/td>\nIEEE Standard for High Performance Serial Bus Bridges <\/td>\n<\/tr>\n
3<\/td>\nTitle page <\/td>\n<\/tr>\n
5<\/td>\nIntroduction <\/td>\n<\/tr>\n
6<\/td>\nNotice to users <\/td>\n<\/tr>\n
7<\/td>\nParticipants <\/td>\n<\/tr>\n
9<\/td>\nCONTENTS <\/td>\n<\/tr>\n
11<\/td>\n1. Overview
1.1 Scope
1.2 Purpose <\/td>\n<\/tr>\n
13<\/td>\n2. Normative references <\/td>\n<\/tr>\n
15<\/td>\n3. Definitions and notation
3.1 Conformance
3.2 Technical <\/td>\n<\/tr>\n
19<\/td>\n3.3 Document notation
3.3.1 Size notation <\/td>\n<\/tr>\n
20<\/td>\n3.3.2 Numerical values <\/td>\n<\/tr>\n
21<\/td>\n3.3.3 Packet formats
3.3.4 C pseudocode notation <\/td>\n<\/tr>\n
22<\/td>\n3.3.5 CSR, ROM, and field notation <\/td>\n<\/tr>\n
23<\/td>\n3.3.6 Register specification format <\/td>\n<\/tr>\n
24<\/td>\n3.3.7 Reserved CSR fields <\/td>\n<\/tr>\n
25<\/td>\n4. Bridge model (informative) <\/td>\n<\/tr>\n
26<\/td>\n4.1 Global node IDs <\/td>\n<\/tr>\n
27<\/td>\n4.2 Remote time-out <\/td>\n<\/tr>\n
28<\/td>\n4.3 Clan affinity and net update <\/td>\n<\/tr>\n
30<\/td>\n4.4 Cycle time distribution and synchronization <\/td>\n<\/tr>\n
32<\/td>\n4.5 Universal time <\/td>\n<\/tr>\n
34<\/td>\n4.6 Stream connection management <\/td>\n<\/tr>\n
41<\/td>\n5. Bridge portal and bridge-aware node facilities
5.1 Configuration ROM
5.1.1 Bus information block <\/td>\n<\/tr>\n
42<\/td>\n5.1.2 Node_Capabilities entry
5.1.3 Bus_Dependent_Info entry
5.1.4 Bridge_Capabilities entry <\/td>\n<\/tr>\n
43<\/td>\n5.2 Control and status registers <\/td>\n<\/tr>\n
45<\/td>\n5.2.1 QUARANTINE register <\/td>\n<\/tr>\n
46<\/td>\n5.2.2 VIRTUAL_ID_MAP register <\/td>\n<\/tr>\n
47<\/td>\n5.2.3 ROUTE_MAP register <\/td>\n<\/tr>\n
48<\/td>\n5.2.4 CLAN_EUI_64 register <\/td>\n<\/tr>\n
49<\/td>\n5.2.5 CLAN_INFO register <\/td>\n<\/tr>\n
51<\/td>\n6. Packet formats
6.1 Self-ID packet zero
6.2 Cycle master adjustment packet <\/td>\n<\/tr>\n
52<\/td>\n6.3 Response packet <\/td>\n<\/tr>\n
54<\/td>\n6.4 Global asynchronous stream packets (GASP) <\/td>\n<\/tr>\n
55<\/td>\n6.5 Net management message interception <\/td>\n<\/tr>\n
56<\/td>\n6.6 Net management messages <\/td>\n<\/tr>\n
58<\/td>\n6.6.1 TIMEOUT message <\/td>\n<\/tr>\n
59<\/td>\n6.6.2 TIME OFFSET message <\/td>\n<\/tr>\n
60<\/td>\n6.6.3 Stream management messages <\/td>\n<\/tr>\n
62<\/td>\n6.6.3.1 JOIN message
6.6.3.2 LEAVE message <\/td>\n<\/tr>\n
63<\/td>\n6.6.3.3 LISTEN message
6.6.3.4 RENEW message
6.6.3.5 TEARDOWN message
6.6.3.6 STREAM STATUS message <\/td>\n<\/tr>\n
64<\/td>\n6.6.4 Net update messages
6.6.4.1 MUTE message
6.6.4.2 BUS ID message
6.6.4.3 BUS ID ANNOUNCEMENT message <\/td>\n<\/tr>\n
65<\/td>\n6.6.4.4 PANIC message
6.7 UPDATE ROUTES message <\/td>\n<\/tr>\n
67<\/td>\n7. Transaction routing and operations
7.1 Source bus (initial entry portal) <\/td>\n<\/tr>\n
68<\/td>\n7.2 Intermediate buses <\/td>\n<\/tr>\n
69<\/td>\n7.2.1 Packet reception (intermediate entry portal)
7.2.2 Packet transmission (intermediate exit portal) <\/td>\n<\/tr>\n
70<\/td>\n7.3 Destination bus (terminal exit portal) <\/td>\n<\/tr>\n
71<\/td>\n7.4 Maximum forward time <\/td>\n<\/tr>\n
72<\/td>\n7.5 Congestion management <\/td>\n<\/tr>\n
75<\/td>\n8. Stream operations and routing
8.1 Cycle timer synchronization
8.1.1 Alpha portal regulation of the local cycle master <\/td>\n<\/tr>\n
77<\/td>\n8.1.2 Cycle master adjustment <\/td>\n<\/tr>\n
78<\/td>\n8.2 Net time <\/td>\n<\/tr>\n
79<\/td>\n8.3 GASP routing and operations <\/td>\n<\/tr>\n
80<\/td>\n8.4 Listening portal operations (isochronous streams)
8.5 Talking portal operations (isochronous streams)
8.6 Isochronous stream connection management <\/td>\n<\/tr>\n
82<\/td>\n8.6.1 JOIN request processing <\/td>\n<\/tr>\n
86<\/td>\n8.6.2 LISTEN request processing <\/td>\n<\/tr>\n
88<\/td>\n8.6.3 LEAVE request processing <\/td>\n<\/tr>\n
90<\/td>\n8.6.4 RENEW request processing <\/td>\n<\/tr>\n
91<\/td>\n8.6.5 TEARDOWN request processing <\/td>\n<\/tr>\n
93<\/td>\n8.6.6 Autonomous connection teardown <\/td>\n<\/tr>\n
96<\/td>\n8.7 Common Isochronous Packet (CIP) format headers <\/td>\n<\/tr>\n
99<\/td>\n9. Operations in a bridged environment
9.1 CSR architecture assumptions
9.2 Bridge-aware devices
9.2.1 Configuration ROM bus information block <\/td>\n<\/tr>\n
100<\/td>\n9.2.2 Remote time-out
9.2.3 Bus reset and quarantine <\/td>\n<\/tr>\n
101<\/td>\n9.2.4 Serial Bus event indication (SB_EVENT.indication)
9.2.5 Lock operations
9.3 Legacy devices
9.4 TIMEOUT message operations <\/td>\n<\/tr>\n
103<\/td>\n9.5 Modifications to the BUS_TIME and CYCLE_TIME registers
9.6 Remote access to core and bus-dependent CSRs <\/td>\n<\/tr>\n
105<\/td>\n10. Net update
10.1 Power reset initialization
10.2 Bus reset operations <\/td>\n<\/tr>\n
106<\/td>\n10.2.1 Quarantine <\/td>\n<\/tr>\n
107<\/td>\n10.2.2 Loop detection and elimination <\/td>\n<\/tr>\n
108<\/td>\n10.2.3 Clan allocation maps <\/td>\n<\/tr>\n
110<\/td>\n10.2.4 Net allocation map <\/td>\n<\/tr>\n
111<\/td>\n10.2.5 Net update completion
10.3 Coherency during net update <\/td>\n<\/tr>\n
112<\/td>\n10.4 Mute bridge portals <\/td>\n<\/tr>\n
113<\/td>\n10.5 Route map updates <\/td>\n<\/tr>\n
115<\/td>\n10.5.1 UPDATE ROUTES message received from the coordinator <\/td>\n<\/tr>\n
116<\/td>\n10.5.2 UPDATE ROUTES message received from co-portal <\/td>\n<\/tr>\n
117<\/td>\n10.6 Net panic <\/td>\n<\/tr>\n
119<\/td>\n11. Global node ID management
11.1 Virtual ID management <\/td>\n<\/tr>\n
121<\/td>\n11.2 Bus ID management <\/td>\n<\/tr>\n
125<\/td>\nAnnex A (normative) Net correctness properties <\/td>\n<\/tr>\n
127<\/td>\nAnnex B (normative) Minimum Serial Bus capabilities for bridge portals <\/td>\n<\/tr>\n
129<\/td>\nAnnex C (normative) Pseudocode data structures and constants
C.1 Configuration ROM and control and status registers <\/td>\n<\/tr>\n
132<\/td>\nC.2 Message and packet formats <\/td>\n<\/tr>\n
133<\/td>\nC.3 Global portal variables and external procedures <\/td>\n<\/tr>\n
137<\/td>\nAnnex D (normative) Transaction routing
D.1 Bridge-bound subactions <\/td>\n<\/tr>\n
139<\/td>\nD.2 Bus-bound subactions <\/td>\n<\/tr>\n
141<\/td>\nD.3 Transaction routing functions <\/td>\n<\/tr>\n
145<\/td>\nAnnex E (normative) Discovery and enumeration protocol (DEP)
E.1 Message formats <\/td>\n<\/tr>\n
147<\/td>\nE.1.1 EUI-64 discovery request <\/td>\n<\/tr>\n
148<\/td>\nE.1.2 Keyword discovery request <\/td>\n<\/tr>\n
149<\/td>\nE.1.3 Client ID request
E.1.4 Configuration ROM announcement <\/td>\n<\/tr>\n
150<\/td>\nE.1.5 DEP responses <\/td>\n<\/tr>\n
151<\/td>\nE.2 Proxy functions
E.2.1 Discovery proxy <\/td>\n<\/tr>\n
152<\/td>\nE.2.2 Service proxy
E.3 Implementation requirements <\/td>\n<\/tr>\n
153<\/td>\nAnnex F (normative) Plug control registers <\/td>\n<\/tr>\n
154<\/td>\nF.1 OUTPUT_MASTER_PLUG register <\/td>\n<\/tr>\n
155<\/td>\nF.2 OUTPUT_PLUG registers <\/td>\n<\/tr>\n
157<\/td>\nF.3 INPUT_MASTER_PLUG register <\/td>\n<\/tr>\n
158<\/td>\nF.4 INPUT_PLUG registers <\/td>\n<\/tr>\n
159<\/td>\nAnnex G (informative) Bus topology analysis <\/td>\n<\/tr>\n
160<\/td>\nG.1 Topology analysis after power reset <\/td>\n<\/tr>\n
164<\/td>\nG.2 Topology analysis when the root changes <\/td>\n<\/tr>\n
167<\/td>\nG.3 Topology analysis when a node is inserted <\/td>\n<\/tr>\n
169<\/td>\nAnnex H (informative) Sample configuration ROM <\/td>\n<\/tr>\n
171<\/td>\nAnnex I (informative) Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard for High Performance Serial Bus Bridges<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n2005<\/td>\n171<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":80966,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-80965","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/80965","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/80966"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=80965"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=80965"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=80965"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}