{"id":194619,"date":"2024-10-19T12:20:59","date_gmt":"2024-10-19T12:20:59","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1012-2016\/"},"modified":"2024-10-25T04:51:58","modified_gmt":"2024-10-25T04:51:58","slug":"ieee-1012-2016","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1012-2016\/","title":{"rendered":"IEEE 1012 2016"},"content":{"rendered":"
Revision Standard – Active. Verification and validation (V&V) processes are used to determine whethere the development products of a given activity conform to the requirements of that activity and whethere the product satisfies its intended use and user needs. V&V life cycle process requirements are specified for different integrity levels. The scope of V&V processes encompasses systems, software, and hardware, and it includes their interfaces. This standard applies to systems, software, and hardware being developed, maintained, or reused (legacy, commercial off-the-shelf [COTS], non-developmental items). The term software also includes firmware and microcode, and each of the terms system, software, and hardware includes documentation. V&V processes include the analysis, evaluation, review, inspection, assessment, and testing of products.<\/p>\n
PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
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1<\/td>\n | IEEE Std 1012\u2122-2016 Front Cover <\/td>\n<\/tr>\n | ||||||
2<\/td>\n | Title page <\/td>\n<\/tr>\n | ||||||
4<\/td>\n | Important Notices and Disclaimers Concerning IEEE Standards Documents <\/td>\n<\/tr>\n | ||||||
7<\/td>\n | Participants IEEE Std 1012-2016 <\/td>\n<\/tr>\n | ||||||
9<\/td>\n | Participants IEEE Std 1012-2016\/Cor1-2017 <\/td>\n<\/tr>\n | ||||||
11<\/td>\n | Introduction <\/td>\n<\/tr>\n | ||||||
13<\/td>\n | Contents <\/td>\n<\/tr>\n | ||||||
16<\/td>\n | 1. Overview 1.1 Scope <\/td>\n<\/tr>\n | ||||||
17<\/td>\n | 1.2 Purpose <\/td>\n<\/tr>\n | ||||||
18<\/td>\n | 1.3 Field of application <\/td>\n<\/tr>\n | ||||||
19<\/td>\n | 1.4 V&V objectives 1.5 Organization of the standard <\/td>\n<\/tr>\n | ||||||
22<\/td>\n | 1.6 Audience 1.7 Conformance 1.8 Disclaimer <\/td>\n<\/tr>\n | ||||||
23<\/td>\n | 2. Normative references 3. Definitions and acronyms 3.1 Definitions <\/td>\n<\/tr>\n | ||||||
27<\/td>\n | 3.2 Acronyms <\/td>\n<\/tr>\n | ||||||
28<\/td>\n | 4. Relationships between verification and validation (V&V) and life cycle processes <\/td>\n<\/tr>\n | ||||||
33<\/td>\n | 5. Integrity levels <\/td>\n<\/tr>\n | ||||||
35<\/td>\n | 6. V&V process overview 6.1 General <\/td>\n<\/tr>\n | ||||||
36<\/td>\n | 6.2 V&V testing <\/td>\n<\/tr>\n | ||||||
38<\/td>\n | 7. Common V&V processes 7.1 V&V management process <\/td>\n<\/tr>\n | ||||||
39<\/td>\n | 7.2 Acquisition Support V&V process <\/td>\n<\/tr>\n | ||||||
40<\/td>\n | 7.3 Supply Planning V&V process 7.4 Project Planning V&V process <\/td>\n<\/tr>\n | ||||||
41<\/td>\n | 7.5 Configuration Management V&V process <\/td>\n<\/tr>\n | ||||||
51<\/td>\n | 8. System V&V processes 8.1 Business or Mission Analysis V&V process 8.2 Stakeholder Needs and Requirements Definition V&V process <\/td>\n<\/tr>\n | ||||||
52<\/td>\n | 8.3 System Requirements Definition V&V process <\/td>\n<\/tr>\n | ||||||
53<\/td>\n | 8.4 Architecture definition V&V process <\/td>\n<\/tr>\n | ||||||
54<\/td>\n | 8.5 Design Definition V&V process <\/td>\n<\/tr>\n | ||||||
55<\/td>\n | 8.6 System analysis V&V process <\/td>\n<\/tr>\n | ||||||
56<\/td>\n | 8.7 Implementation V&V process <\/td>\n<\/tr>\n | ||||||
57<\/td>\n | 8.8 Integration V&V process <\/td>\n<\/tr>\n | ||||||
58<\/td>\n | 8.9 Verification process <\/td>\n<\/tr>\n | ||||||
59<\/td>\n | 8.10 Transition V&V process <\/td>\n<\/tr>\n | ||||||
60<\/td>\n | 8.11 Validation process 8.12 Operation V&V process <\/td>\n<\/tr>\n | ||||||
61<\/td>\n | 8.13 Maintenance V&V process <\/td>\n<\/tr>\n | ||||||
62<\/td>\n | 8.14 Disposal V&V process <\/td>\n<\/tr>\n | ||||||
95<\/td>\n | 9. Software V&V processes 9.1 Software Concept V&V process 9.2 Software Requirements Analysis V&V process <\/td>\n<\/tr>\n | ||||||
96<\/td>\n | 9.3 Software Design V&V process <\/td>\n<\/tr>\n | ||||||
97<\/td>\n | 9.4 Software Construction V&V process <\/td>\n<\/tr>\n | ||||||
99<\/td>\n | 9.5 Software Integration V&V process 9.6 Software Qualification Testing V&V process <\/td>\n<\/tr>\n | ||||||
100<\/td>\n | 9.7 Software Acceptance Testing V&V process <\/td>\n<\/tr>\n | ||||||
101<\/td>\n | 9.8 Software Verification process 9.9 Software Installation and Checkout V&V process <\/td>\n<\/tr>\n | ||||||
102<\/td>\n | 9.10 Software Validation process <\/td>\n<\/tr>\n | ||||||
103<\/td>\n | 9.11 Software Operation V&V process 9.12 Software Maintenance V&V process <\/td>\n<\/tr>\n | ||||||
105<\/td>\n | 9.13 Software Disposal V&V process <\/td>\n<\/tr>\n | ||||||
140<\/td>\n | 10. Hardware V&V processes 10.1 Hardware Concept V&V process <\/td>\n<\/tr>\n | ||||||
141<\/td>\n | 10.2 Hardware Requirements Analysis V&V process 10.3 Hardware Design V&V process <\/td>\n<\/tr>\n | ||||||
142<\/td>\n | 10.4 Hardware Fabrication V&V process <\/td>\n<\/tr>\n | ||||||
144<\/td>\n | 10.5 Hardware Integration V&V process 10.6 Hardware Qualification Testing V&V process <\/td>\n<\/tr>\n | ||||||
145<\/td>\n | 10.7 Hardware Acceptance Testing V&V process <\/td>\n<\/tr>\n | ||||||
146<\/td>\n | 10.8 Hardware Verification process 10.9 Hardware Transition V&V process <\/td>\n<\/tr>\n | ||||||
147<\/td>\n | 10.10 Hardware Validation process <\/td>\n<\/tr>\n | ||||||
148<\/td>\n | 10.11 Hardware Operation V&V process 10.12 Hardware Maintenance V&V process <\/td>\n<\/tr>\n | ||||||
149<\/td>\n | 10.13 Hardware Disposal V&V process <\/td>\n<\/tr>\n | ||||||
178<\/td>\n | 11. V&V reporting, administrative, and documentation requirements 11.1 V&V reporting requirements <\/td>\n<\/tr>\n | ||||||
182<\/td>\n | 11.2 V&V administrative requirements 11.3 V&V documentation requirements <\/td>\n<\/tr>\n | ||||||
183<\/td>\n | 12. V&V plan 12.1 Overview <\/td>\n<\/tr>\n | ||||||
184<\/td>\n | 12.2 VVP Section 1: Purpose 12.3 VVP Section 2: Referenced documents 12.4 VVP Section 3: Definitions 12.5 VVP Section 4: V&V overview <\/td>\n<\/tr>\n | ||||||
185<\/td>\n | 12.6 VVP Section 5: V&V processes <\/td>\n<\/tr>\n | ||||||
186<\/td>\n | 12.7 VVP Section 6: V&V reporting requirements 12.8 VVP Section 7: V&V administrative requirements <\/td>\n<\/tr>\n | ||||||
187<\/td>\n | 12.9 VVP Section 8: V&V test documentation requirements <\/td>\n<\/tr>\n | ||||||
188<\/td>\n | Annex A (informative) Mapping of IEEE 1012 verification and validation (V&V) activities and tasks A.1 Mapping of ISO\/IEC\/IEEE 15288 activities to IEEE 1012 V&V activities and tasks <\/td>\n<\/tr>\n | ||||||
191<\/td>\n | A.2 Mapping of IEEE 1012 V&V activities to ISO\/IEC\/IEEE 15288 system life cycle processes and activities <\/td>\n<\/tr>\n | ||||||
193<\/td>\n | A.3 Mapping of ISO\/IEC 12207 V&V activities to IEEE 1012 V&V activities and tasks <\/td>\n<\/tr>\n | ||||||
195<\/td>\n | A.4 Mapping of IEEE 1012 V&V activities to ISO\/IEC 12207 software life cycle processes and activities <\/td>\n<\/tr>\n | ||||||
197<\/td>\n | Annex B (informative) A risk-based integrity level schema <\/td>\n<\/tr>\n | ||||||
199<\/td>\n | Annex C (informative) Definition of independent verification and validation (IV&V) C.1 Independence parameters C.1.1 Introduction C.1.2 Technical independence C.1.3 Managerial independence C.1.4 Financial independence C.2 Forms of independence C.2.1 Introduction <\/td>\n<\/tr>\n | ||||||
200<\/td>\n | C.2.2 Classical IV&V C.2.3 Modified IV&V C.2.4 Integrated IV&V <\/td>\n<\/tr>\n | ||||||
201<\/td>\n | C.2.5 Internal IV&V C.2.6 Embedded V&V <\/td>\n<\/tr>\n | ||||||
202<\/td>\n | Annex D (informative) V&V of reuse software D.1 Purpose D.2 V&V of software developed in a reuse process D.2.1 Introduction <\/td>\n<\/tr>\n | ||||||
203<\/td>\n | D.2.2 V&V of assets in development D.2.3 V&V of reused assets D.3 V&V of software developed and reused outside of a reuse process <\/td>\n<\/tr>\n | ||||||
208<\/td>\n | Annex E (informative) Verification and validation (V&V) measures E.1 Introduction E.2 Measures for evaluating anomaly density <\/td>\n<\/tr>\n | ||||||
209<\/td>\n | E.3 Measures for evaluating V&V effectiveness E.4 Measures for evaluating V&V efficiency <\/td>\n<\/tr>\n | ||||||
211<\/td>\n | Annex F (informative) Example of verification and validation (V&V) relationships to other project responsibilities <\/td>\n<\/tr>\n | ||||||
212<\/td>\n | Annex G (informative) Optional verification and validation (V&V) tasks <\/td>\n<\/tr>\n | ||||||
218<\/td>\n | Annex H (informative) Environmental factors consideration H.1 Introduction H.2 In the agreement processes <\/td>\n<\/tr>\n | ||||||
219<\/td>\n | H.3 In the organizational project-enabling processes H.4 In the project processes H.5 In the technical processes <\/td>\n<\/tr>\n | ||||||
221<\/td>\n | Annex I (informative) Verification and validation (V&V) of system, software, and hardware integration I.1 Introduction <\/td>\n<\/tr>\n | ||||||
222<\/td>\n | I.2 Examples of system failures caused by integration issues I.2.1 Introduction I.2.2 Year 2000 system integration issue I.2.3 System architecture integration issues <\/td>\n<\/tr>\n | ||||||
223<\/td>\n | I.2.4 System, software, and hardware interaction issues <\/td>\n<\/tr>\n | ||||||
226<\/td>\n | Annex J (informative) Hazard, security, and risk analysis J.1 Introduction <\/td>\n<\/tr>\n | ||||||
227<\/td>\n | J.2 Hazard analysis <\/td>\n<\/tr>\n | ||||||
228<\/td>\n | J.3 Security analysis J.3.1 Summary <\/td>\n<\/tr>\n | ||||||
229<\/td>\n | J.3.2 Threat-based security analysis J.3.2.1 Overview <\/td>\n<\/tr>\n | ||||||
230<\/td>\n | J.3.2.2 Typical threats <\/td>\n<\/tr>\n | ||||||
233<\/td>\n | J.3.2.3 Typical vulnerabilities <\/td>\n<\/tr>\n | ||||||
235<\/td>\n | J.3.3 Process assurance consideration in system life cycle <\/td>\n<\/tr>\n | ||||||
236<\/td>\n | J.4 Risk analysis J.4.1 Risk analysis objectives J.4.2 Risk analysis context <\/td>\n<\/tr>\n | ||||||
237<\/td>\n | J.4.3 V&V risk analysis J.4.3.1 Risk identification <\/td>\n<\/tr>\n | ||||||
238<\/td>\n | J.4.3.2 Risk estimation J.4.3.3 Risk evaluation <\/td>\n<\/tr>\n | ||||||
239<\/td>\n | Annex K (informative) Example of assigning and changing the system integrity level of \u201csupporting system functions\u201d <\/td>\n<\/tr>\n | ||||||
241<\/td>\n | Annex L (informative) Mapping of ISO\/IEC\/IEEE 15288 and ISO\/IEC 12207 process outcomes to verification and validation (V&V) tasks <\/td>\n<\/tr>\n | ||||||
256<\/td>\n | Annex M (informative) Verification and validation (V&V) of nth of a kind systems <\/td>\n<\/tr>\n | ||||||
258<\/td>\n | Annex N (informative) Bibliography <\/td>\n<\/tr>\n | ||||||
260<\/td>\n | Back Cover <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" IEEE Standard for System, Software, and Hardware Verification and Validation<\/b><\/p>\n |