{"id":80071,"date":"2024-10-17T18:40:39","date_gmt":"2024-10-17T18:40:39","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1364-2001\/"},"modified":"2024-10-24T19:42:20","modified_gmt":"2024-10-24T19:42:20","slug":"ieee-1364-2001","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1364-2001\/","title":{"rendered":"IEEE 1364 2001"},"content":{"rendered":"

Revision Standard – Inactive – Superseded. Supersedes 1364-1995.<\/p>\n

PDF Catalog<\/h4>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
1<\/td>\nCover Page <\/td>\n<\/tr>\n
2<\/td>\nTitle Page <\/td>\n<\/tr>\n
4<\/td>\nAbout IEEE Std 1364-2001 Version C and the Errata <\/td>\n<\/tr>\n
5<\/td>\nParticipants\u2014Version C and Errata <\/td>\n<\/tr>\n
6<\/td>\nIntroduction <\/td>\n<\/tr>\n
8<\/td>\nParticipants <\/td>\n<\/tr>\n
10<\/td>\nCONTENTS <\/td>\n<\/tr>\n
24<\/td>\n1. Overview
1.1 Objectives of this standard
1.2 Conventions used in this standard <\/td>\n<\/tr>\n
25<\/td>\n1.3 Syntactic description
1.4 Contents of this standard <\/td>\n<\/tr>\n
27<\/td>\n1.5 Header file listings <\/td>\n<\/tr>\n
28<\/td>\n1.6 Examples
1.7 Prerequisites <\/td>\n<\/tr>\n
29<\/td>\n2. Lexical conventions
2.1 Lexical tokens
2.2 White space
2.3 Comments
2.4 Operators
2.5 Numbers <\/td>\n<\/tr>\n
30<\/td>\n2.5.1 Integer constants <\/td>\n<\/tr>\n
33<\/td>\n2.5.2 Real constants
2.5.3 Conversion
2.6 Strings <\/td>\n<\/tr>\n
34<\/td>\n2.6.1 String variable declaration
2.6.2 String manipulation
2.6.3 Special characters in strings <\/td>\n<\/tr>\n
35<\/td>\n2.7 Identifiers, keywords, and system names
2.7.1 Escaped identifiers <\/td>\n<\/tr>\n
36<\/td>\n2.7.2 Generated identifiers
2.7.3 Keywords
2.7.4 System tasks and functions <\/td>\n<\/tr>\n
37<\/td>\n2.7.5 Compiler directives
2.8 Attributes <\/td>\n<\/tr>\n
38<\/td>\n2.8.1 Examples <\/td>\n<\/tr>\n
39<\/td>\n2.8.2 Syntax <\/td>\n<\/tr>\n
43<\/td>\n3. Data types
3.1 Value set
3.2 Nets and variables
3.2.1 Net declarations <\/td>\n<\/tr>\n
45<\/td>\n3.2.2 Variable declarations <\/td>\n<\/tr>\n
46<\/td>\n3.3 Vectors
3.3.1 Specifying vectors <\/td>\n<\/tr>\n
47<\/td>\n3.3.2 Vector net accessibility
3.4 Strengths
3.4.1 Charge strength
3.4.2 Drive strength <\/td>\n<\/tr>\n
48<\/td>\n3.5 Implicit declarations
3.6 Net initialization
3.7 Net types
3.7.1 Wire and tri nets <\/td>\n<\/tr>\n
49<\/td>\n3.7.2 Wired nets
3.7.3 Trireg net <\/td>\n<\/tr>\n
50<\/td>\n3.7.3.1 Capacitive networks <\/td>\n<\/tr>\n
53<\/td>\n3.7.3.2 Ideal capacitive state and charge decay
3.7.4 Tri0 and tri1 nets <\/td>\n<\/tr>\n
54<\/td>\n3.7.5 Supply nets
3.8 Regs
3.9 Integers, reals, times, and realtimes <\/td>\n<\/tr>\n
55<\/td>\n3.9.1 Operators and real numbers
3.9.2 Conversion <\/td>\n<\/tr>\n
56<\/td>\n3.10 Arrays
3.10.1 Net arrays
3.10.2 reg and variable arrays
3.10.3 Memories <\/td>\n<\/tr>\n
57<\/td>\n3.10.3.1 Array examples
3.10.3.1.1 Array declarations
3.10.3.1.2 Assignment to array elements
3.10.3.1.3 Memory differences
3.11 Parameters <\/td>\n<\/tr>\n
58<\/td>\n3.11.1 Module parameters <\/td>\n<\/tr>\n
59<\/td>\n3.11.2 Local parameters – localparam <\/td>\n<\/tr>\n
60<\/td>\n3.11.3 Specify parameters <\/td>\n<\/tr>\n
61<\/td>\n3.12 Name spaces <\/td>\n<\/tr>\n
63<\/td>\n4. Expressions
4.1 Operators <\/td>\n<\/tr>\n
64<\/td>\n4.1.1 Operators with real operands <\/td>\n<\/tr>\n
65<\/td>\n4.1.2 Operator precedence <\/td>\n<\/tr>\n
66<\/td>\n4.1.3 Using integer numbers in expressions
4.1.4 Expression evaluation order <\/td>\n<\/tr>\n
67<\/td>\n4.1.5 Arithmetic operators <\/td>\n<\/tr>\n
68<\/td>\n4.1.6 Arithmetic expressions with regs and integers <\/td>\n<\/tr>\n
69<\/td>\n4.1.7 Relational operators
4.1.8 Equality operators <\/td>\n<\/tr>\n
70<\/td>\n4.1.9 Logical operators
4.1.10 Bit-wise operators <\/td>\n<\/tr>\n
71<\/td>\n4.1.11 Reduction operators <\/td>\n<\/tr>\n
72<\/td>\n4.1.12 Shift operators <\/td>\n<\/tr>\n
73<\/td>\n4.1.13 Conditional operator <\/td>\n<\/tr>\n
74<\/td>\n4.1.14 Concatenations <\/td>\n<\/tr>\n
75<\/td>\n4.1.15 Event or
4.2 Operands
4.2.1 Vector bit-select and part-select addressing <\/td>\n<\/tr>\n
77<\/td>\n4.2.2 Array and memory addressing <\/td>\n<\/tr>\n
78<\/td>\n4.2.3 Strings <\/td>\n<\/tr>\n
79<\/td>\n4.2.3.1 String operations
4.2.3.2 String value padding and potential problems <\/td>\n<\/tr>\n
80<\/td>\n4.2.3.3 Null string handling
4.3 Minimum, typical, and maximum delay expressions <\/td>\n<\/tr>\n
82<\/td>\n4.4 Expression bit lengths
4.4.1 Rules for expression bit lengths <\/td>\n<\/tr>\n
83<\/td>\n4.4.2 An example of an expression bit-length problem <\/td>\n<\/tr>\n
84<\/td>\n4.4.3 Example of self-determined expressions <\/td>\n<\/tr>\n
85<\/td>\n4.5 Signed expressions
4.5.1 Rules for expression types
4.5.2 Steps for evaluating an expression <\/td>\n<\/tr>\n
86<\/td>\n4.5.3 Steps for evaluating an assignment
4.5.4 Handling X and Z in signed expressions <\/td>\n<\/tr>\n
87<\/td>\n5. Scheduling semantics
5.1 Execution of a model
5.2 Event simulation
5.3 The stratified event queue <\/td>\n<\/tr>\n
88<\/td>\n5.4 The Verilog simulation reference model <\/td>\n<\/tr>\n
89<\/td>\n5.4.1 Determinism
5.4.2 Nondeterminism
5.5 Race conditions
5.6 Scheduling implication of assignments <\/td>\n<\/tr>\n
90<\/td>\n5.6.1 Continuous assignment
5.6.2 Procedural continuous assignment
5.6.3 Blocking assignment
5.6.4 Nonblocking assignment
5.6.5 Switch (transistor) processing <\/td>\n<\/tr>\n
91<\/td>\n5.6.6 Port connections
5.6.7 Functions and tasks <\/td>\n<\/tr>\n
92<\/td>\n6. Assignments
6.1 Continuous assignments <\/td>\n<\/tr>\n
93<\/td>\n6.1.1 The net declaration assignment
6.1.2 The continuous assignment statement <\/td>\n<\/tr>\n
95<\/td>\n6.1.3 Delays
6.1.4 Strength <\/td>\n<\/tr>\n
96<\/td>\n6.2 Procedural assignments
6.2.1 Variable declaration assignment <\/td>\n<\/tr>\n
97<\/td>\n6.2.2 Variable declaration syntax <\/td>\n<\/tr>\n
98<\/td>\n7. Gate and switch level modeling
7.1 Gate and switch declaration syntax <\/td>\n<\/tr>\n
100<\/td>\n7.1.1 The gate type specification
7.1.2 The drive strength specification <\/td>\n<\/tr>\n
101<\/td>\n7.1.3 The delay specification
7.1.4 The primitive instance identifier
7.1.5 The range specification <\/td>\n<\/tr>\n
102<\/td>\n7.1.6 Primitive instance connection list <\/td>\n<\/tr>\n
104<\/td>\n7.2 and, nand, nor, or, xor, and xnor gates <\/td>\n<\/tr>\n
105<\/td>\n7.3 buf and not gates <\/td>\n<\/tr>\n
106<\/td>\n7.4 bufif1, bufif0, notif1, and notif0 gates <\/td>\n<\/tr>\n
107<\/td>\n7.5 MOS switches <\/td>\n<\/tr>\n
109<\/td>\n7.6 Bidirectional pass switches
7.7 CMOS switches <\/td>\n<\/tr>\n
110<\/td>\n7.8 pullup and pulldown sources <\/td>\n<\/tr>\n
111<\/td>\n7.9 Logic strength modeling <\/td>\n<\/tr>\n
112<\/td>\n7.10 Strengths and values of combined signals
7.10.1 Combined signals of unambiguous strength <\/td>\n<\/tr>\n
113<\/td>\n7.10.2 Ambiguous strengths: sources and combinations <\/td>\n<\/tr>\n
118<\/td>\n7.10.3 Ambiguous strength signals and unambiguous signals <\/td>\n<\/tr>\n
122<\/td>\n7.10.4 Wired logic net types <\/td>\n<\/tr>\n
125<\/td>\n7.11 Strength reduction by nonresistive devices
7.12 Strength reduction by resistive devices
7.13 Strengths of net types
7.13.1 tri0 and tri1 net strengths
7.13.2 trireg strength
7.13.3 supply0 and supply1 net strengths <\/td>\n<\/tr>\n
126<\/td>\n7.14 Gate and net delays <\/td>\n<\/tr>\n
127<\/td>\n7.14.1 min:typ:max delays <\/td>\n<\/tr>\n
128<\/td>\n7.14.2 trireg net charge decay
7.14.2.1 The charge decay process
7.14.2.2 The delay specification for charge decay time <\/td>\n<\/tr>\n
130<\/td>\n8. User-defined primitives (UDPs)
8.1 UDP definition <\/td>\n<\/tr>\n
132<\/td>\n8.1.1 UDP header
8.1.2 UDP port declarations
8.1.3 Sequential UDP initial statement
8.1.4 UDP state table <\/td>\n<\/tr>\n
133<\/td>\n8.1.5 Z values in UDP
8.1.6 Summary of symbols <\/td>\n<\/tr>\n
134<\/td>\n8.2 Combinational UDPs <\/td>\n<\/tr>\n
135<\/td>\n8.3 Level-sensitive sequential UDPs
8.4 Edge-sensitive sequential UDPs <\/td>\n<\/tr>\n
136<\/td>\n8.5 Sequential UDP initialization <\/td>\n<\/tr>\n
138<\/td>\n8.6 UDP instances <\/td>\n<\/tr>\n
139<\/td>\n8.7 Mixing level-sensitive and edge-sensitive descriptions <\/td>\n<\/tr>\n
140<\/td>\n8.8 Level-sensitive dominance <\/td>\n<\/tr>\n
141<\/td>\n9. Behavioral modeling
9.1 Behavioral model overview <\/td>\n<\/tr>\n
142<\/td>\n9.2 Procedural assignments
9.2.1 Blocking procedural assignments <\/td>\n<\/tr>\n
144<\/td>\n9.2.2 The nonblocking procedural assignment <\/td>\n<\/tr>\n
147<\/td>\n9.3 Procedural continuous assignments <\/td>\n<\/tr>\n
148<\/td>\n9.3.1 The assign and deassign procedural statements <\/td>\n<\/tr>\n
149<\/td>\n9.3.2 The force and release procedural statements <\/td>\n<\/tr>\n
150<\/td>\n9.4 Conditional statement <\/td>\n<\/tr>\n
151<\/td>\n9.4.1 If-else-if construct <\/td>\n<\/tr>\n
153<\/td>\n9.5 Case statement <\/td>\n<\/tr>\n
156<\/td>\n9.5.1 Case statement with don\u2019t-cares
9.5.2 Constant expression in case statement <\/td>\n<\/tr>\n
157<\/td>\n9.6 Looping statements <\/td>\n<\/tr>\n
159<\/td>\n9.7 Procedural timing controls <\/td>\n<\/tr>\n
160<\/td>\n9.7.1 Delay control <\/td>\n<\/tr>\n
161<\/td>\n9.7.2 Event control
9.7.3 Named events <\/td>\n<\/tr>\n
162<\/td>\n9.7.4 Event or operator <\/td>\n<\/tr>\n
163<\/td>\n9.7.5 Implicit event_expression list <\/td>\n<\/tr>\n
164<\/td>\n9.7.6 Level sensitive event control <\/td>\n<\/tr>\n
165<\/td>\n9.7.7 Intra-assignment timing controls <\/td>\n<\/tr>\n
169<\/td>\n9.8 Block statements
9.8.1 Sequential blocks <\/td>\n<\/tr>\n
170<\/td>\n9.8.2 Parallel blocks <\/td>\n<\/tr>\n
171<\/td>\n9.8.3 Block names
9.8.4 Start and finish times <\/td>\n<\/tr>\n
172<\/td>\n9.9 Structured procedures <\/td>\n<\/tr>\n
173<\/td>\n9.9.1 Initial construct
9.9.2 Always construct <\/td>\n<\/tr>\n
175<\/td>\n10. Tasks and functions
10.1 Distinctions between tasks and functions
10.2 Tasks and task enabling <\/td>\n<\/tr>\n
176<\/td>\n10.2.1 Task declarations <\/td>\n<\/tr>\n
177<\/td>\n10.2.2 Task enabling and argument passing <\/td>\n<\/tr>\n
179<\/td>\n10.2.3 Task memory usage and concurrent activation <\/td>\n<\/tr>\n
180<\/td>\n10.3 Functions and function calling <\/td>\n<\/tr>\n
181<\/td>\n10.3.1 Function declarations <\/td>\n<\/tr>\n
182<\/td>\n10.3.2 Returning a value from a function <\/td>\n<\/tr>\n
183<\/td>\n10.3.3 Calling a function
10.3.4 Function rules <\/td>\n<\/tr>\n
184<\/td>\n10.3.5 Use of constant functions <\/td>\n<\/tr>\n
186<\/td>\n11. Disabling of named blocks and tasks <\/td>\n<\/tr>\n
189<\/td>\n12. Hierarchical structures
12.1 Modules <\/td>\n<\/tr>\n
191<\/td>\n12.1.1 Top level modules
12.1.2 Module instantiation <\/td>\n<\/tr>\n
193<\/td>\n12.1.3 Generated instantiation <\/td>\n<\/tr>\n
196<\/td>\n12.1.3.1 genvar – generate statement index variable
12.1.3.2 generate-loop <\/td>\n<\/tr>\n
200<\/td>\n12.1.3.3 generate-conditional <\/td>\n<\/tr>\n
201<\/td>\n12.1.3.4 generate-case <\/td>\n<\/tr>\n
203<\/td>\n12.2 Overriding module parameter values <\/td>\n<\/tr>\n
205<\/td>\n12.2.1 defparam statement <\/td>\n<\/tr>\n
206<\/td>\n12.2.2 Module instance parameter value assignment
12.2.2.1 Parameter value assignment by ordered list <\/td>\n<\/tr>\n
207<\/td>\n12.2.2.2 Parameter value assignment by name <\/td>\n<\/tr>\n
208<\/td>\n12.2.3 Parameter dependence
12.3 Ports
12.3.1 Port definition
12.3.2 List of ports <\/td>\n<\/tr>\n
209<\/td>\n12.3.3 Port declarations <\/td>\n<\/tr>\n
211<\/td>\n12.3.4 List of ports declarations
12.3.5 Connecting module instance ports by ordered list <\/td>\n<\/tr>\n
212<\/td>\n12.3.6 Connecting module instance ports by name <\/td>\n<\/tr>\n
213<\/td>\n12.3.7 Real numbers in port connections <\/td>\n<\/tr>\n
214<\/td>\n12.3.8 Connecting dissimilar ports
12.3.9 Port connection rules
12.3.9.1 Rule 1
12.3.9.2 Rule 2 <\/td>\n<\/tr>\n
215<\/td>\n12.3.10 Net types resulting from dissimilar port connections
12.3.10.1 Net type resolution rule
12.3.10.2 Net type table <\/td>\n<\/tr>\n
216<\/td>\n12.3.11 Connecting signed values via ports
12.4 Hierarchical names <\/td>\n<\/tr>\n
219<\/td>\n12.5 Upwards name referencing <\/td>\n<\/tr>\n
221<\/td>\n12.6 Scope rules <\/td>\n<\/tr>\n
223<\/td>\n13. Configuring the contents of a design
13.1 Introduction
13.1.1 Library notation <\/td>\n<\/tr>\n
224<\/td>\n13.1.2 Basic configuration elements
13.2 Libraries
13.2.1 Specifying libraries – the library map file <\/td>\n<\/tr>\n
225<\/td>\n13.2.1.1 File path resolution <\/td>\n<\/tr>\n
226<\/td>\n13.2.2 Using multiple library mapping files
13.2.3 Mapping source files to libraries
13.3 Configurations
13.3.1 Basic configuration syntax <\/td>\n<\/tr>\n
227<\/td>\n13.3.1.1 Design statement
13.3.1.2 The default clause
13.3.1.3 The instance clause <\/td>\n<\/tr>\n
228<\/td>\n13.3.1.4 The cell clause
13.3.1.5 The liblist clause <\/td>\n<\/tr>\n
229<\/td>\n13.3.1.6 The use clause
13.3.2 Hierarchical configurations <\/td>\n<\/tr>\n
230<\/td>\n13.4 Using libraries and configs
13.4.1 Precompiling in a single-pass use-model
13.4.2 Elaboration-time compiling in a single-pass use-model
13.4.3 Precompiling using a separate compilation tool
13.4.4 Command line considerations <\/td>\n<\/tr>\n
231<\/td>\n13.5 Configuration examples
13.5.1 Default configuration from library map file
13.5.2 Using the default clause <\/td>\n<\/tr>\n
232<\/td>\n13.5.3 Using the cell clause
13.5.4 Using the instance clause
13.5.5 Using a hierarchical config <\/td>\n<\/tr>\n
233<\/td>\n13.6 Displaying library binding information
13.7 Library mapping examples
13.7.1 Using the command line to control library searching
13.7.2 File path specification examples <\/td>\n<\/tr>\n
234<\/td>\n13.7.3 Resolving multiple path specifications <\/td>\n<\/tr>\n
235<\/td>\n14. Specify blocks
14.1 Specify block declaration <\/td>\n<\/tr>\n
236<\/td>\n14.2 Module path declarations <\/td>\n<\/tr>\n
237<\/td>\n14.2.1 Module path restrictions
14.2.2 Simple module paths <\/td>\n<\/tr>\n
238<\/td>\n14.2.3 Edge-sensitive paths <\/td>\n<\/tr>\n
239<\/td>\n14.2.4 State-dependent paths
14.2.4.1 Conditional expression <\/td>\n<\/tr>\n
240<\/td>\n14.2.4.2 Simple state-dependent paths <\/td>\n<\/tr>\n
241<\/td>\n14.2.4.3 Edge-sensitive state-dependent paths <\/td>\n<\/tr>\n
242<\/td>\n14.2.4.4 The ifnone condition <\/td>\n<\/tr>\n
243<\/td>\n14.2.5 Full connection and parallel connection paths <\/td>\n<\/tr>\n
244<\/td>\n14.2.6 Declaring multiple module paths in a single statement <\/td>\n<\/tr>\n
245<\/td>\n14.2.7 Module path polarity
14.2.7.1 Unknown polarity
14.2.7.2 Positive polarity <\/td>\n<\/tr>\n
246<\/td>\n14.2.7.3 Negative polarity
14.3 Assigning delays to module paths <\/td>\n<\/tr>\n
247<\/td>\n14.3.1 Specifying transition delays on module paths <\/td>\n<\/tr>\n
248<\/td>\n14.3.2 Specifying x transition delays <\/td>\n<\/tr>\n
249<\/td>\n14.3.3 Delay selection <\/td>\n<\/tr>\n
250<\/td>\n14.4 Mixing module path delays and distributed delays <\/td>\n<\/tr>\n
251<\/td>\n14.5 Driving wired logic <\/td>\n<\/tr>\n
252<\/td>\n14.6 Detailed control of pulse filtering behavior <\/td>\n<\/tr>\n
253<\/td>\n14.6.1 Specify block control of pulse limit values <\/td>\n<\/tr>\n
254<\/td>\n14.6.2 Global control of pulse limit values
14.6.3 SDF annotation of pulse limit values <\/td>\n<\/tr>\n
255<\/td>\n14.6.4 Detailed pulse control capabilities
14.6.4.1 On-event versus on-detect pulse filtering <\/td>\n<\/tr>\n
256<\/td>\n14.6.4.2 Negative pulse detection <\/td>\n<\/tr>\n
261<\/td>\n15. Timing checks
15.1 Overview <\/td>\n<\/tr>\n
264<\/td>\n15.2 Timing checks using a stability window <\/td>\n<\/tr>\n
265<\/td>\n15.2.1 $setup
15.2.2 $hold <\/td>\n<\/tr>\n
266<\/td>\n15.2.3 $setuphold <\/td>\n<\/tr>\n
268<\/td>\n15.2.4 $removal <\/td>\n<\/tr>\n
269<\/td>\n15.2.5 $recovery <\/td>\n<\/tr>\n
270<\/td>\n15.2.6 $recrem <\/td>\n<\/tr>\n
272<\/td>\n15.3 Timing checks for clock and control signals <\/td>\n<\/tr>\n
273<\/td>\n15.3.1 $skew <\/td>\n<\/tr>\n
274<\/td>\n15.3.2 $timeskew <\/td>\n<\/tr>\n
276<\/td>\n15.3.3 $fullskew <\/td>\n<\/tr>\n
278<\/td>\n15.3.4 $width <\/td>\n<\/tr>\n
279<\/td>\n15.3.5 $period <\/td>\n<\/tr>\n
280<\/td>\n15.3.6 $nochange <\/td>\n<\/tr>\n
281<\/td>\n15.4 Edge-control specifiers <\/td>\n<\/tr>\n
283<\/td>\n15.5 Notifiers: user-defined responses to timing violations <\/td>\n<\/tr>\n
285<\/td>\n15.5.1 Requirements for accurate simulation <\/td>\n<\/tr>\n
287<\/td>\n15.5.2 Conditions in negative timing checks <\/td>\n<\/tr>\n
289<\/td>\n15.5.3 Notifiers in negative timing checks
15.5.4 Option behavior
15.6 Enabling timing checks with conditioned events <\/td>\n<\/tr>\n
290<\/td>\n15.7 Vector signals in timing checks <\/td>\n<\/tr>\n
291<\/td>\n15.8 Negative timing checks <\/td>\n<\/tr>\n
293<\/td>\n16. Backannotation using the Standard Delay Format (SDF)
16.1 The SDF annotator
16.2 Mapping of SDF constructs to Verilog
16.2.1 Mapping of SDF delay constructs to Verilog declarations <\/td>\n<\/tr>\n
295<\/td>\n16.2.2 Mapping of SDF timing check constructs to Verilog <\/td>\n<\/tr>\n
296<\/td>\n16.2.3 SDF annotation of specparams <\/td>\n<\/tr>\n
297<\/td>\n16.2.4 SDF annotation of interconnect delays <\/td>\n<\/tr>\n
298<\/td>\n16.3 Multiple annotations <\/td>\n<\/tr>\n
299<\/td>\n16.4 Multiple SDF files
16.5 Pulse limit annotation <\/td>\n<\/tr>\n
300<\/td>\n16.6 SDF to Verilog delay value mapping <\/td>\n<\/tr>\n
301<\/td>\n17. System tasks and functions
17.1 Display system tasks <\/td>\n<\/tr>\n
302<\/td>\n17.1.1 The display and write tasks
17.1.1.1 Escape sequences for special characters <\/td>\n<\/tr>\n
303<\/td>\n17.1.1.2 Format specifications <\/td>\n<\/tr>\n
305<\/td>\n17.1.1.3 Size of displayed data <\/td>\n<\/tr>\n
306<\/td>\n17.1.1.4 Unknown and high impedance values <\/td>\n<\/tr>\n
307<\/td>\n17.1.1.5 Strength format <\/td>\n<\/tr>\n
309<\/td>\n17.1.1.6 Hierarchical name format
17.1.1.7 String format
17.1.2 Strobed monitoring <\/td>\n<\/tr>\n
310<\/td>\n17.1.3 Continuous monitoring
17.2 File input-output system tasks and functions
17.2.1 Opening and closing files <\/td>\n<\/tr>\n
312<\/td>\n17.2.2 File output system tasks <\/td>\n<\/tr>\n
313<\/td>\n17.2.3 Formatting data to a string <\/td>\n<\/tr>\n
314<\/td>\n17.2.4 Reading data from a file
17.2.4.1 Reading a character at a time
17.2.4.2 Reading a line at a time
17.2.4.3 Reading formatted data <\/td>\n<\/tr>\n
317<\/td>\n17.2.4.4 Reading binary data <\/td>\n<\/tr>\n
318<\/td>\n17.2.5 File positioning
17.2.6 Flushing output
17.2.7 I\/O error status <\/td>\n<\/tr>\n
319<\/td>\n17.2.8 Loading memory data from a file <\/td>\n<\/tr>\n
320<\/td>\n17.2.9 Loading timing data from an SDF file <\/td>\n<\/tr>\n
321<\/td>\n17.3 Timescale system tasks
17.3.1 $printtimescale <\/td>\n<\/tr>\n
322<\/td>\n17.3.2 $timeformat <\/td>\n<\/tr>\n
325<\/td>\n17.4 Simulation control system tasks
17.4.1 $finish
17.4.2 $stop <\/td>\n<\/tr>\n
326<\/td>\n17.5 PLA modeling system tasks
17.5.1 Array types <\/td>\n<\/tr>\n
327<\/td>\n17.5.2 Array logic types
17.5.3 Logic array personality declaration and loading
17.5.4 Logic array personality formats <\/td>\n<\/tr>\n
330<\/td>\n17.6 Stochastic analysis tasks
17.6.1 $q_initialize <\/td>\n<\/tr>\n
331<\/td>\n17.6.2 $q_add
17.6.3 $q_remove
17.6.4 $q_full
17.6.5 $q_exam <\/td>\n<\/tr>\n
332<\/td>\n17.6.6 Status codes
17.7 Simulation time system functions
17.7.1 $time <\/td>\n<\/tr>\n
333<\/td>\n17.7.2 $stime
17.7.3 $realtime <\/td>\n<\/tr>\n
334<\/td>\n17.8 Conversion functions <\/td>\n<\/tr>\n
335<\/td>\n17.9 Probabilistic distribution functions
17.9.1 $random function <\/td>\n<\/tr>\n
336<\/td>\n17.9.2 $dist_ functions <\/td>\n<\/tr>\n
337<\/td>\n17.9.3 Algorithm for probabilistic distribution functions <\/td>\n<\/tr>\n
344<\/td>\n17.10 Command line input <\/td>\n<\/tr>\n
345<\/td>\n17.10.1 $test$plusargs (string)
17.10.2 $value$plusargs (user_string, variable) <\/td>\n<\/tr>\n
348<\/td>\n18. Value change dump (VCD) files
18.1 Creating the four state value change dump file
18.1.1 Specifying the name of the dump file ($dumpfile) <\/td>\n<\/tr>\n
349<\/td>\n18.1.2 Specifying the variables to be dumped ($dumpvars) <\/td>\n<\/tr>\n
350<\/td>\n18.1.3 Stopping and resuming the dump ($dumpoff\/$dumpon) <\/td>\n<\/tr>\n
351<\/td>\n18.1.4 Generating a checkpoint ($dumpall)
18.1.5 Limiting the size of the dump file ($dumplimit) <\/td>\n<\/tr>\n
352<\/td>\n18.1.6 Reading the dump file during simulation ($dumpflush) <\/td>\n<\/tr>\n
353<\/td>\n18.2 Format of the four state VCD file
18.2.1 Syntax of the four state VCD file <\/td>\n<\/tr>\n
355<\/td>\n18.2.2 Formats of variable values <\/td>\n<\/tr>\n
356<\/td>\n18.2.3 Description of keyword commands
18.2.3.1 $comment
18.2.3.2 $date <\/td>\n<\/tr>\n
357<\/td>\n18.2.3.3 $enddefinitions
18.2.3.4 $scope <\/td>\n<\/tr>\n
358<\/td>\n18.2.3.5 $timescale
18.2.3.6 $upscope
18.2.3.7 $version <\/td>\n<\/tr>\n
359<\/td>\n18.2.3.8 $var <\/td>\n<\/tr>\n
360<\/td>\n18.2.3.9 $dumpall
18.2.3.10 $dumpoff
18.2.3.11 $dumpon <\/td>\n<\/tr>\n
361<\/td>\n18.2.3.12 $dumpvars <\/td>\n<\/tr>\n
362<\/td>\n18.2.4 Four state VCD file format example <\/td>\n<\/tr>\n
363<\/td>\n18.3 Creating the extended value change dump file
18.3.1 Specifying the dumpfile name and the ports to be dumped ($dumpports) <\/td>\n<\/tr>\n
364<\/td>\n18.3.2 Stopping and resuming the dump ($dumpportsoff\/$dumpportson) <\/td>\n<\/tr>\n
365<\/td>\n18.3.3 Generating a checkpoint ($dumpportsall)
18.3.4 Limiting the size of the dump file ($dumpportslimit) <\/td>\n<\/tr>\n
366<\/td>\n18.3.5 Reading the dump file during simulation ($dumpportsflush)
18.3.6 Description of keyword commands
18.3.6.1 $vcdclose <\/td>\n<\/tr>\n
367<\/td>\n18.3.7 General rules for extended VCD system tasks
18.4 Format of the extended VCD file
18.4.1 Syntax of the extended VCD file <\/td>\n<\/tr>\n
369<\/td>\n18.4.2 Extended VCD node information <\/td>\n<\/tr>\n
371<\/td>\n18.4.3 Value changes
18.4.3.1 State characters <\/td>\n<\/tr>\n
372<\/td>\n18.4.3.2 Drivers
18.4.4 Extended VCD file format example <\/td>\n<\/tr>\n
374<\/td>\n19. Compiler directives
19.1 `celldefine and `endcelldefine
19.2 `default_nettype <\/td>\n<\/tr>\n
375<\/td>\n19.3 `define and `undef
19.3.1 `define <\/td>\n<\/tr>\n
377<\/td>\n19.3.2 `undef
19.4 `ifdef, `else, `elsif, `endif, `ifndef <\/td>\n<\/tr>\n
381<\/td>\n19.5 `include
19.6 `resetall
19.7 `line <\/td>\n<\/tr>\n
382<\/td>\n19.8 `timescale <\/td>\n<\/tr>\n
384<\/td>\n19.9 `unconnected_drive and `nounconnected_drive <\/td>\n<\/tr>\n
385<\/td>\n20. PLI overview
20.1 PLI purpose and history (informative)
20.2 User-defined system task or function names <\/td>\n<\/tr>\n
386<\/td>\n20.3 User-defined system task or function types
20.4 Overriding built-in system task and function names
20.5 User-supplied PLI applications
20.6 PLI interface mechanism <\/td>\n<\/tr>\n
387<\/td>\n20.7 User-defined system task and function arguments
20.8 PLI include files
20.9 PLI Memory Restrictions <\/td>\n<\/tr>\n
388<\/td>\n21. PLI TF and ACC interface mechanism
21.1 User-supplied PLI applications
21.1.1 The sizetf class of PLI applications
21.1.2 The checktf class of PLI applications <\/td>\n<\/tr>\n
389<\/td>\n21.1.3 The calltf class of PLI applications
21.1.4 The misctf class of PLI applications
21.1.5 The consumer class of PLI applications
21.2 Associating PLI applications to a class and system task\/function name <\/td>\n<\/tr>\n
390<\/td>\n21.3 PLI application arguments
21.3.1 The data C argument
21.3.2 The reason C argument <\/td>\n<\/tr>\n
391<\/td>\n21.3.3 The paramvc C argument <\/td>\n<\/tr>\n
392<\/td>\n22. Using ACC routines
22.1 ACC routine definition
22.2 The handle data type <\/td>\n<\/tr>\n
393<\/td>\n22.3 Using ACC routines
22.3.1 Header files
22.3.2 Initializing ACC routines
22.3.3 Exiting ACC routines
22.4 List of ACC routines by major category <\/td>\n<\/tr>\n
394<\/td>\n22.4.1 Fetch routines <\/td>\n<\/tr>\n
395<\/td>\n22.4.2 Handle routines <\/td>\n<\/tr>\n
396<\/td>\n22.4.3 Next routines <\/td>\n<\/tr>\n
398<\/td>\n22.4.4 Modify routines
22.4.5 Miscellaneous routines <\/td>\n<\/tr>\n
399<\/td>\n22.4.6 VCL routines
22.5 Accessible objects <\/td>\n<\/tr>\n
401<\/td>\n22.5.1 ACC routines that operate on module instances
22.5.2 ACC routines that operate on module ports <\/td>\n<\/tr>\n
402<\/td>\n22.5.3 ACC routines that operate on bits of a port
22.5.4 ACC routines that operate on module paths or data paths <\/td>\n<\/tr>\n
403<\/td>\n22.5.5 ACC routines that operate on intermodule paths
22.5.6 ACC routines that operate on top-level modules
22.5.7 ACC routines that operate on primitive instances <\/td>\n<\/tr>\n
404<\/td>\n22.5.8 ACC routines that operate on primitive terminals
22.5.9 ACC routines that operate on nets <\/td>\n<\/tr>\n
405<\/td>\n22.5.10 ACC routines that operate on reg types
22.5.11 ACC routines that operate on integer, real, and time variables
22.5.12 ACC routines that operate on named events <\/td>\n<\/tr>\n
406<\/td>\n22.5.13 ACC routines that operate on parameters and specparams
22.5.14 ACC routines that operate on timing checks
22.5.15 ACC routines that operate on timing check terminals <\/td>\n<\/tr>\n
407<\/td>\n22.5.16 ACC routines that operate on user-defined system task\/function arguments
22.6 ACC routine types and fulltypes <\/td>\n<\/tr>\n
410<\/td>\n22.7 Error handling <\/td>\n<\/tr>\n
411<\/td>\n22.7.1 Suppressing error messages
22.7.2 Enabling warnings
22.7.3 Testing for errors
22.7.4 Example <\/td>\n<\/tr>\n
412<\/td>\n22.7.5 Exception values
22.8 Reading and writing delay values <\/td>\n<\/tr>\n
413<\/td>\n22.8.1 Number of delays for Verilog HDL objects
22.8.2 ACC routine configuration <\/td>\n<\/tr>\n
414<\/td>\n22.8.3 Determining the number of arguments for ACC delay routines
22.8.3.1 Single delay value mode <\/td>\n<\/tr>\n
415<\/td>\n22.8.3.2 Min:typ:max delay value mode <\/td>\n<\/tr>\n
417<\/td>\n22.8.3.3 Calculating turn-off delays from rise and fall delays <\/td>\n<\/tr>\n
418<\/td>\n22.9 String handling
22.9.1 ACC routines share an internal string buffer <\/td>\n<\/tr>\n
419<\/td>\n22.9.2 String buffer reset
22.9.2.1 The buffer reset warning <\/td>\n<\/tr>\n
420<\/td>\n22.9.3 Preserving string values
22.9.4 Example of preserving string values
22.10 Using VCL ACC routines <\/td>\n<\/tr>\n
421<\/td>\n22.10.1 VCL objects
22.10.2 The VCL record definition <\/td>\n<\/tr>\n
424<\/td>\n22.10.3 Effects of acc_initialize() and acc_close() on VCL consumer routines
22.10.4 An example of using VCL ACC routines <\/td>\n<\/tr>\n
427<\/td>\n23. ACC routine definitions <\/td>\n<\/tr>\n
428<\/td>\n23.1 acc_append_delays() <\/td>\n<\/tr>\n
432<\/td>\n23.2 acc_append_pulsere() <\/td>\n<\/tr>\n
434<\/td>\n23.3 acc_close() <\/td>\n<\/tr>\n
435<\/td>\n23.4 acc_collect() <\/td>\n<\/tr>\n
437<\/td>\n23.5 acc_compare_handles() <\/td>\n<\/tr>\n
438<\/td>\n23.6 acc_configure() <\/td>\n<\/tr>\n
447<\/td>\n23.7 acc_count() <\/td>\n<\/tr>\n
448<\/td>\n23.8 acc_fetch_argc() <\/td>\n<\/tr>\n
449<\/td>\n23.9 acc_fetch_argv() <\/td>\n<\/tr>\n
451<\/td>\n23.10 acc_fetch_attribute() <\/td>\n<\/tr>\n
455<\/td>\n23.11 acc_fetch_attribute_int() <\/td>\n<\/tr>\n
456<\/td>\n23.12 acc_fetch_attribute_str() <\/td>\n<\/tr>\n
457<\/td>\n23.13 acc_fetch_defname() <\/td>\n<\/tr>\n
458<\/td>\n23.14 acc_fetch_delay_mode() <\/td>\n<\/tr>\n
460<\/td>\n23.15 acc_fetch_delays() <\/td>\n<\/tr>\n
464<\/td>\n23.16 acc_fetch_direction() <\/td>\n<\/tr>\n
465<\/td>\n23.17 acc_fetch_edge() <\/td>\n<\/tr>\n
467<\/td>\n23.18 acc_fetch_fullname() <\/td>\n<\/tr>\n
469<\/td>\n23.19 acc_fetch_fulltype() <\/td>\n<\/tr>\n
472<\/td>\n23.20 acc_fetch_index() <\/td>\n<\/tr>\n
474<\/td>\n23.21 acc_fetch_location() <\/td>\n<\/tr>\n
476<\/td>\n23.22 acc_fetch_name() <\/td>\n<\/tr>\n
478<\/td>\n23.23 acc_fetch_paramtype() <\/td>\n<\/tr>\n
479<\/td>\n23.24 acc_fetch_paramval() <\/td>\n<\/tr>\n
481<\/td>\n23.25 acc_fetch_polarity() <\/td>\n<\/tr>\n
482<\/td>\n23.26 acc_fetch_precision() <\/td>\n<\/tr>\n
483<\/td>\n23.27 acc_fetch_pulsere() <\/td>\n<\/tr>\n
486<\/td>\n23.28 acc_fetch_range() <\/td>\n<\/tr>\n
487<\/td>\n23.29 acc_fetch_size() <\/td>\n<\/tr>\n
488<\/td>\n23.30 acc_fetch_tfarg(), acc_fetch_itfarg() <\/td>\n<\/tr>\n
490<\/td>\n23.31 acc_fetch_tfarg_int(), acc_fetch_itfarg_int() <\/td>\n<\/tr>\n
491<\/td>\n23.32 acc_fetch_tfarg_str(), acc_fetch_itfarg_str() <\/td>\n<\/tr>\n
492<\/td>\n23.33 acc_fetch_timescale_info() <\/td>\n<\/tr>\n
494<\/td>\n23.34 acc_fetch_type() <\/td>\n<\/tr>\n
496<\/td>\n23.35 acc_fetch_type_str() <\/td>\n<\/tr>\n
497<\/td>\n23.36 acc_fetch_value() <\/td>\n<\/tr>\n
502<\/td>\n23.37 acc_free() <\/td>\n<\/tr>\n
503<\/td>\n23.38 acc_handle_by_name() <\/td>\n<\/tr>\n
505<\/td>\n23.39 acc_handle_calling_mod_m <\/td>\n<\/tr>\n
506<\/td>\n23.40 acc_handle_condition() <\/td>\n<\/tr>\n
507<\/td>\n23.41 acc_handle_conn() <\/td>\n<\/tr>\n
508<\/td>\n23.42 acc_handle_datapath() <\/td>\n<\/tr>\n
509<\/td>\n23.43 acc_handle_hiconn() <\/td>\n<\/tr>\n
511<\/td>\n23.44 acc_handle_interactive_scope() <\/td>\n<\/tr>\n
512<\/td>\n23.45 acc_handle_loconn() <\/td>\n<\/tr>\n
513<\/td>\n23.46 acc_handle_modpath() <\/td>\n<\/tr>\n
515<\/td>\n23.47 acc_handle_notifier() <\/td>\n<\/tr>\n
516<\/td>\n23.48 acc_handle_object() <\/td>\n<\/tr>\n
518<\/td>\n23.49 acc_handle_parent() <\/td>\n<\/tr>\n
519<\/td>\n23.50 acc_handle_path() <\/td>\n<\/tr>\n
520<\/td>\n23.51 acc_handle_pathin() <\/td>\n<\/tr>\n
521<\/td>\n23.52 acc_handle_pathout() <\/td>\n<\/tr>\n
522<\/td>\n23.53 acc_handle_port() <\/td>\n<\/tr>\n
524<\/td>\n23.54 acc_handle_scope() <\/td>\n<\/tr>\n
525<\/td>\n23.55 acc_handle_simulated_net() <\/td>\n<\/tr>\n
527<\/td>\n23.56 acc_handle_tchk() <\/td>\n<\/tr>\n
531<\/td>\n23.57 acc_handle_tchkarg1() <\/td>\n<\/tr>\n
533<\/td>\n23.58 acc_handle_tchkarg2() <\/td>\n<\/tr>\n
534<\/td>\n23.59 acc_handle_terminal() <\/td>\n<\/tr>\n
535<\/td>\n23.60 acc_handle_tfarg(), acc_handle_itfarg() <\/td>\n<\/tr>\n
537<\/td>\n23.61 acc_handle_tfinst() <\/td>\n<\/tr>\n
538<\/td>\n23.62 acc_initialize() <\/td>\n<\/tr>\n
539<\/td>\n23.63 acc_next() <\/td>\n<\/tr>\n
543<\/td>\n23.64 acc_next_bit() <\/td>\n<\/tr>\n
545<\/td>\n23.65 acc_next_cell() <\/td>\n<\/tr>\n
546<\/td>\n23.66 acc_next_cell_load() <\/td>\n<\/tr>\n
548<\/td>\n23.67 acc_next_child() <\/td>\n<\/tr>\n
549<\/td>\n23.68 acc_next_driver() <\/td>\n<\/tr>\n
550<\/td>\n23.69 acc_next_hiconn() <\/td>\n<\/tr>\n
552<\/td>\n23.70 acc_next_input() <\/td>\n<\/tr>\n
554<\/td>\n23.71 acc_next_load() <\/td>\n<\/tr>\n
556<\/td>\n23.72 acc_next_loconn() <\/td>\n<\/tr>\n
557<\/td>\n23.73 acc_next_modpath() <\/td>\n<\/tr>\n
558<\/td>\n23.74 acc_next_net() <\/td>\n<\/tr>\n
559<\/td>\n23.75 acc_next_output() <\/td>\n<\/tr>\n
561<\/td>\n23.76 acc_next_parameter() <\/td>\n<\/tr>\n
562<\/td>\n23.77 acc_next_port() <\/td>\n<\/tr>\n
564<\/td>\n23.78 acc_next_portout() <\/td>\n<\/tr>\n
565<\/td>\n23.79 acc_next_primitive() <\/td>\n<\/tr>\n
566<\/td>\n23.80 acc_next_scope() <\/td>\n<\/tr>\n
567<\/td>\n23.81 acc_next_specparam() <\/td>\n<\/tr>\n
568<\/td>\n23.82 acc_next_tchk() <\/td>\n<\/tr>\n
570<\/td>\n23.83 acc_next_terminal() <\/td>\n<\/tr>\n
571<\/td>\n23.84 acc_next_topmod() <\/td>\n<\/tr>\n
572<\/td>\n23.85 acc_object_in_typelist() <\/td>\n<\/tr>\n
574<\/td>\n23.86 acc_object_of_type() <\/td>\n<\/tr>\n
576<\/td>\n23.87 acc_product_type() <\/td>\n<\/tr>\n
578<\/td>\n23.88 acc_product_version() <\/td>\n<\/tr>\n
579<\/td>\n23.89 acc_release_object() <\/td>\n<\/tr>\n
580<\/td>\n23.90 acc_replace_delays() <\/td>\n<\/tr>\n
584<\/td>\n23.91 acc_replace_pulsere() <\/td>\n<\/tr>\n
587<\/td>\n23.92 acc_reset_buffer() <\/td>\n<\/tr>\n
588<\/td>\n23.93 acc_set_interactive_scope() <\/td>\n<\/tr>\n
589<\/td>\n23.94 acc_set_pulsere() <\/td>\n<\/tr>\n
591<\/td>\n23.95 acc_set_scope() <\/td>\n<\/tr>\n
593<\/td>\n23.96 acc_set_value() <\/td>\n<\/tr>\n
598<\/td>\n23.97 acc_vcl_add() <\/td>\n<\/tr>\n
600<\/td>\n23.98 acc_vcl_delete() <\/td>\n<\/tr>\n
601<\/td>\n23.99 acc_version() <\/td>\n<\/tr>\n
602<\/td>\n24. Using TF routines
24.1 TF routine definition
24.2 TF routine system task\/function arguments
24.3 Reading and writing system task\/function argument values
24.3.1 Reading and writing 2-state parameter argument values
24.3.2 Reading and writing 4-state values <\/td>\n<\/tr>\n
603<\/td>\n24.3.3 Reading and writing strength values
24.3.4 Reading and writing to memories
24.3.5 Reading and writing string values
24.3.6 Writing return values of user-defined functions
24.3.7 Writing the correct C data types <\/td>\n<\/tr>\n
604<\/td>\n24.4 Value change detection
24.5 Simulation time
24.6 Simulation synchronization <\/td>\n<\/tr>\n
605<\/td>\n24.7 Instances of user-defined tasks or functions
24.8 Module and scope instance names
24.9 Saving information from one system TF call to the next
24.10 Displaying output messages
24.11 Stopping and finishing <\/td>\n<\/tr>\n
606<\/td>\n25. TF routine definitions <\/td>\n<\/tr>\n
607<\/td>\n25.1 io_mcdprintf() <\/td>\n<\/tr>\n
608<\/td>\n25.2 io_printf() <\/td>\n<\/tr>\n
609<\/td>\n25.3 mc_scan_plusargs() <\/td>\n<\/tr>\n
610<\/td>\n25.4 tf_add_long() <\/td>\n<\/tr>\n
611<\/td>\n25.5 tf_asynchoff(), tf_iasynchoff() <\/td>\n<\/tr>\n
612<\/td>\n25.6 tf_asynchon(), tf_iasynchon() <\/td>\n<\/tr>\n
613<\/td>\n25.7 tf_clearalldelays(), tf_iclearalldelays() <\/td>\n<\/tr>\n
614<\/td>\n25.8 tf_compare_long() <\/td>\n<\/tr>\n
615<\/td>\n25.9 tf_copypvc_flag(), tf_icopypvc_flag() <\/td>\n<\/tr>\n
616<\/td>\n25.10 tf_divide_long() <\/td>\n<\/tr>\n
617<\/td>\n25.11 tf_dofinish() <\/td>\n<\/tr>\n
618<\/td>\n25.12 tf_dostop() <\/td>\n<\/tr>\n
619<\/td>\n25.13 tf_error() <\/td>\n<\/tr>\n
620<\/td>\n25.14 tf_evaluatep(), tf_ievaluatep() <\/td>\n<\/tr>\n
621<\/td>\n25.15 tf_exprinfo(), tf_iexprinfo() <\/td>\n<\/tr>\n
624<\/td>\n25.16 tf_getcstringp(), tf_igetcstringp() <\/td>\n<\/tr>\n
625<\/td>\n25.17 tf_getinstance() <\/td>\n<\/tr>\n
626<\/td>\n25.18 tf_getlongp(), tf_igetlongp() <\/td>\n<\/tr>\n
627<\/td>\n25.19 tf_getlongtime(), tf_igetlongtime() <\/td>\n<\/tr>\n
628<\/td>\n25.20 tf_getnextlongtime() <\/td>\n<\/tr>\n
629<\/td>\n25.21 tf_getp(), tf_igetp() <\/td>\n<\/tr>\n
630<\/td>\n25.22 tf_getpchange(), tf_igetpchange() <\/td>\n<\/tr>\n
631<\/td>\n25.23 tf_getrealp(), tf_igetrealp() <\/td>\n<\/tr>\n
632<\/td>\n25.24 tf_getrealtime(), tf_igetrealtime() <\/td>\n<\/tr>\n
633<\/td>\n25.25 tf_gettime(), tf_igettime() <\/td>\n<\/tr>\n
634<\/td>\n25.26 tf_gettimeprecision(), tf_igettimeprecision() <\/td>\n<\/tr>\n
635<\/td>\n25.27 tf_gettimeunit(), tf_igettimeunit() <\/td>\n<\/tr>\n
636<\/td>\n25.28 tf_getworkarea(), tf_igetworkarea() <\/td>\n<\/tr>\n
637<\/td>\n25.29 tf_long_to_real() <\/td>\n<\/tr>\n
638<\/td>\n25.30 tf_longtime_tostr() <\/td>\n<\/tr>\n
639<\/td>\n25.31 tf_message() <\/td>\n<\/tr>\n
641<\/td>\n25.32 tf_mipname(), tf_imipname() <\/td>\n<\/tr>\n
642<\/td>\n25.33 tf_movepvc_flag(), tf_imovepvc_flag() <\/td>\n<\/tr>\n
643<\/td>\n25.34 tf_multiply_long() <\/td>\n<\/tr>\n
644<\/td>\n25.35 tf_nodeinfo(), tf_inodeinfo() <\/td>\n<\/tr>\n
648<\/td>\n25.36 tf_nump(), tf_inump() <\/td>\n<\/tr>\n
649<\/td>\n25.37 tf_propagatep(), tf_ipropagatep() <\/td>\n<\/tr>\n
650<\/td>\n25.38 tf_putlongp(), tf_iputlongp() <\/td>\n<\/tr>\n
651<\/td>\n25.39 tf_putp(), tf_iputp() <\/td>\n<\/tr>\n
652<\/td>\n25.40 tf_putrealp(), tf_iputrealp() <\/td>\n<\/tr>\n
653<\/td>\n25.41 tf_read_restart() <\/td>\n<\/tr>\n
654<\/td>\n25.42 tf_real_to_long() <\/td>\n<\/tr>\n
655<\/td>\n25.43 tf_rosynchronize(), tf_irosynchronize() <\/td>\n<\/tr>\n
656<\/td>\n25.44 tf_scale_longdelay() <\/td>\n<\/tr>\n
657<\/td>\n25.45 tf_scale_realdelay() <\/td>\n<\/tr>\n
658<\/td>\n25.46 tf_setdelay(), tf_isetdelay() <\/td>\n<\/tr>\n
659<\/td>\n25.47 tf_setlongdelay(), tf_isetlongdelay() <\/td>\n<\/tr>\n
660<\/td>\n25.48 tf_setrealdelay(), tf_isetrealdelay() <\/td>\n<\/tr>\n
661<\/td>\n25.49 tf_setworkarea(), tf_isetworkarea() <\/td>\n<\/tr>\n
662<\/td>\n25.50 tf_sizep(), tf_isizep() <\/td>\n<\/tr>\n
663<\/td>\n25.51 tf_spname(), tf_ispname() <\/td>\n<\/tr>\n
664<\/td>\n25.52 tf_strdelputp(), tf_istrdelputp() <\/td>\n<\/tr>\n
666<\/td>\n25.53 tf_strgetp(), tf_istrgetp() <\/td>\n<\/tr>\n
667<\/td>\n25.54 tf_strgettime() <\/td>\n<\/tr>\n
668<\/td>\n25.55 tf_strlongdelputp(), tf_istrlongdelputp() <\/td>\n<\/tr>\n
670<\/td>\n25.56 tf_strrealdelputp(), tf_istrrealdelputp() <\/td>\n<\/tr>\n
672<\/td>\n25.57 tf_subtract_long() <\/td>\n<\/tr>\n
674<\/td>\n25.58 tf_synchronize(), tf_isynchronize() <\/td>\n<\/tr>\n
675<\/td>\n25.59 tf_testpvc_flag(), tf_itestpvc_flag() <\/td>\n<\/tr>\n
676<\/td>\n25.60 tf_text() <\/td>\n<\/tr>\n
677<\/td>\n25.61 tf_typep(), tf_itypep() <\/td>\n<\/tr>\n
678<\/td>\n25.62 tf_unscale_longdelay() <\/td>\n<\/tr>\n
679<\/td>\n25.63 tf_unscale_realdelay() <\/td>\n<\/tr>\n
680<\/td>\n25.64 tf_warning() <\/td>\n<\/tr>\n
681<\/td>\n25.65 tf_write_save() <\/td>\n<\/tr>\n
682<\/td>\n26. Using VPI routines
26.1 VPI system tasks and functions
26.2 The VPI interface
26.2.1 VPI callbacks <\/td>\n<\/tr>\n
683<\/td>\n26.2.2 VPI access to Verilog HDL objects and simulation objects
26.2.3 Error handling
26.2.4 Function availability
26.2.5 Traversing expressions <\/td>\n<\/tr>\n
684<\/td>\n26.3 VPI object classifications <\/td>\n<\/tr>\n
685<\/td>\n26.3.1 Accessing object relationships and properties <\/td>\n<\/tr>\n
686<\/td>\n26.3.2 Object type properties
26.3.3 Object file and line properties <\/td>\n<\/tr>\n
687<\/td>\n26.3.4 Delays and values
26.4 List of VPI routines by functional category <\/td>\n<\/tr>\n
689<\/td>\n26.5 Key to data model diagrams <\/td>\n<\/tr>\n
690<\/td>\n26.5.1 Diagram key for objects and classes
26.5.2 Diagram key for accessing properties <\/td>\n<\/tr>\n
691<\/td>\n26.5.3 Diagram key for traversing relationships <\/td>\n<\/tr>\n
692<\/td>\n26.6 Object data model diagrams <\/td>\n<\/tr>\n
693<\/td>\n26.6.1 Module <\/td>\n<\/tr>\n
694<\/td>\n26.6.2 Instance arrays <\/td>\n<\/tr>\n
695<\/td>\n26.6.3 Scope
26.6.4 IO declaration <\/td>\n<\/tr>\n
696<\/td>\n26.6.5 Ports <\/td>\n<\/tr>\n
697<\/td>\n26.6.6 Nets and net arrays <\/td>\n<\/tr>\n
699<\/td>\n26.6.7 Regs and reg arrays <\/td>\n<\/tr>\n
701<\/td>\n26.6.8 Variables <\/td>\n<\/tr>\n
702<\/td>\n26.6.9 Memory <\/td>\n<\/tr>\n
703<\/td>\n26.6.10 Object range
26.6.11 Named event <\/td>\n<\/tr>\n
704<\/td>\n26.6.12 Parameter, specparam <\/td>\n<\/tr>\n
705<\/td>\n26.6.13 Primitive, prim term <\/td>\n<\/tr>\n
706<\/td>\n26.6.14 UDP <\/td>\n<\/tr>\n
707<\/td>\n26.6.15 Module path, path term
26.6.16 Intermodule path <\/td>\n<\/tr>\n
708<\/td>\n26.6.17 Timing check
26.6.18 Task, function declaration <\/td>\n<\/tr>\n
709<\/td>\n26.6.19 Task and function call <\/td>\n<\/tr>\n
710<\/td>\n26.6.20 Frames <\/td>\n<\/tr>\n
711<\/td>\n26.6.21 Delay terminals
26.6.22 Net drivers and loads
26.6.23 Reg drivers and loads <\/td>\n<\/tr>\n
712<\/td>\n26.6.24 Continuous assignment <\/td>\n<\/tr>\n
713<\/td>\n26.6.25 Simple expressions <\/td>\n<\/tr>\n
714<\/td>\n26.6.26 Expressions <\/td>\n<\/tr>\n
715<\/td>\n26.6.27 Process, block, statement, event statement <\/td>\n<\/tr>\n
716<\/td>\n26.6.28 Assignment
26.6.29 Delay control
26.6.30 Event control
26.6.31 Repeat control <\/td>\n<\/tr>\n
717<\/td>\n26.6.32 While, repeat, wait
26.6.33 For
26.6.34 Forever <\/td>\n<\/tr>\n
718<\/td>\n26.6.35 If, if-else
26.6.36 Case <\/td>\n<\/tr>\n
719<\/td>\n26.6.37 Assign statement, deassign, force, release
26.6.38 Disable <\/td>\n<\/tr>\n
720<\/td>\n26.6.39 Callback
26.6.40 Time queue
26.6.41 Active time format <\/td>\n<\/tr>\n
721<\/td>\n26.6.42 Attributes <\/td>\n<\/tr>\n
722<\/td>\n26.6.43 Iterator <\/td>\n<\/tr>\n
723<\/td>\n27. VPI routine definitions <\/td>\n<\/tr>\n
724<\/td>\n27.1 vpi_chk_error() <\/td>\n<\/tr>\n
725<\/td>\n27.2 vpi_compare_objects() <\/td>\n<\/tr>\n
726<\/td>\n27.3 vpi_control() <\/td>\n<\/tr>\n
727<\/td>\n27.4 vpi_flush() <\/td>\n<\/tr>\n
728<\/td>\n27.5 vpi_free_object() <\/td>\n<\/tr>\n
729<\/td>\n27.6 vpi_get() <\/td>\n<\/tr>\n
730<\/td>\n27.7 vpi_get_cb_info() <\/td>\n<\/tr>\n
731<\/td>\n27.8 vpi_get_data() <\/td>\n<\/tr>\n
733<\/td>\n27.9 vpi_get_delays() <\/td>\n<\/tr>\n
736<\/td>\n27.10 vpi_get_str() <\/td>\n<\/tr>\n
737<\/td>\n27.11 vpi_get_systf_info() <\/td>\n<\/tr>\n
738<\/td>\n27.12 vpi_get_time() <\/td>\n<\/tr>\n
739<\/td>\n27.13 vpi_get_userdata() <\/td>\n<\/tr>\n
740<\/td>\n27.14 vpi_get_value() <\/td>\n<\/tr>\n
746<\/td>\n27.15 vpi_get_vlog_info() <\/td>\n<\/tr>\n
747<\/td>\n27.16 vpi_handle() <\/td>\n<\/tr>\n
748<\/td>\n27.17 vpi_handle_by_index() <\/td>\n<\/tr>\n
749<\/td>\n27.18 vpi_handle_by_multi_index() <\/td>\n<\/tr>\n
750<\/td>\n27.19 vpi_handle_by_name() <\/td>\n<\/tr>\n
751<\/td>\n27.20 vpi_handle_multi() <\/td>\n<\/tr>\n
752<\/td>\n27.21 vpi_iterate() <\/td>\n<\/tr>\n
753<\/td>\n27.22 vpi_mcd_close() <\/td>\n<\/tr>\n
754<\/td>\n27.23 vpi_mcd_flush() <\/td>\n<\/tr>\n
755<\/td>\n27.24 vpi_mcd_name() <\/td>\n<\/tr>\n
756<\/td>\n27.25 vpi_mcd_open() <\/td>\n<\/tr>\n
757<\/td>\n27.26 vpi_mcd_printf() <\/td>\n<\/tr>\n
758<\/td>\n27.27 vpi_mcd_vprintf() <\/td>\n<\/tr>\n
759<\/td>\n27.28 vpi_printf() <\/td>\n<\/tr>\n
760<\/td>\n27.29 vpi_put_data() <\/td>\n<\/tr>\n
762<\/td>\n27.30 vpi_put_delays() <\/td>\n<\/tr>\n
765<\/td>\n27.31 vpi_put_userdata() <\/td>\n<\/tr>\n
766<\/td>\n27.32 vpi_put_value() <\/td>\n<\/tr>\n
769<\/td>\n27.33 vpi_register_cb() <\/td>\n<\/tr>\n
770<\/td>\n27.33.1 Simulation-event-related callbacks <\/td>\n<\/tr>\n
772<\/td>\n27.33.1.1 Callbacks on Individual Statements
27.33.1.2 Behavior by Statement Type <\/td>\n<\/tr>\n
773<\/td>\n27.33.1.3 Registering Callbacks on a Module-wide Basis
27.33.2 Simulation-time-related callbacks <\/td>\n<\/tr>\n
774<\/td>\n27.33.3 Simulator action and feature related callbacks <\/td>\n<\/tr>\n
777<\/td>\n27.34 vpi_register_systf() <\/td>\n<\/tr>\n
778<\/td>\n27.34.1 System task and function callbacks <\/td>\n<\/tr>\n
779<\/td>\n27.34.2 Initializing VPI system task\/function callbacks <\/td>\n<\/tr>\n
780<\/td>\n27.34.3 Registering multiple system tasks and functions <\/td>\n<\/tr>\n
781<\/td>\n27.35 vpi_remove_cb() <\/td>\n<\/tr>\n
782<\/td>\n27.36 vpi_scan() <\/td>\n<\/tr>\n
783<\/td>\n27.37 vpi_vprintf() <\/td>\n<\/tr>\n
784<\/td>\nAnnex A
Formal syntax definition
A.1 Source text
A.1.1 Library source text
A.1.2 Configuration source text <\/td>\n<\/tr>\n
785<\/td>\nA.1.3 Module and primitive source text
A.1.4 Module parameters and ports
A.1.5 Module items <\/td>\n<\/tr>\n
786<\/td>\nA.2 Declarations
A.2.1 Declaration types
A.2.1.1 Module parameter declarations <\/td>\n<\/tr>\n
787<\/td>\nA.2.1.2 Port declarations
A.2.1.3 Type declarations <\/td>\n<\/tr>\n
788<\/td>\nA.2.2 Declaration data types
A.2.2.1 Net and variable types
A.2.2.2 Strengths
A.2.2.3 Delays
A.2.3 Declaration lists <\/td>\n<\/tr>\n
789<\/td>\nA.2.4 Declaration assignments
A.2.5 Declaration ranges
A.2.6 Function declarations
A.2.7 Task declarations <\/td>\n<\/tr>\n
790<\/td>\nA.2.8 Block item declarations <\/td>\n<\/tr>\n
791<\/td>\nA.3 Primitive instances
A.3.1 Primitive instantiation and instances
A.3.2 Primitive strengths <\/td>\n<\/tr>\n
792<\/td>\nA.3.3 Primitive terminals
A.3.4 Primitive gate and switch types
A.4 Module and generated instantiation
A.4.1 Module instantiation
A.4.2 Generated instantiation <\/td>\n<\/tr>\n
793<\/td>\nA.5 UDP declaration and instantiation
A.5.1 UDP declaration
A.5.2 UDP ports <\/td>\n<\/tr>\n
794<\/td>\nA.5.3 UDP body
A.5.4 UDP instantiation
A.6 Behavioral statements
A.6.1 Continuous assignment statements
A.6.2 Procedural blocks and assignments <\/td>\n<\/tr>\n
795<\/td>\nA.6.3 Parallel and sequential blocks
A.6.4 Statements
A.6.5 Timing control statements <\/td>\n<\/tr>\n
796<\/td>\nA.6.6 Conditional statements <\/td>\n<\/tr>\n
797<\/td>\nA.6.7 Case statements
A.6.8 Looping statements
A.6.9 Task enable statements
A.7 Specify section
A.7.1 Specify block declaration <\/td>\n<\/tr>\n
798<\/td>\nA.7.2 Specify path declarations
A.7.3 Specify block terminals
A.7.4 Specify path delays <\/td>\n<\/tr>\n
800<\/td>\nA.7.5 System timing checks
A.7.5.1 System timing check commands <\/td>\n<\/tr>\n
801<\/td>\nA.7.5.2 System timing check command arguments
A.7.5.3 System timing check event definitions <\/td>\n<\/tr>\n
802<\/td>\nA.8 Expressions
A.8.1 Concatenations
A.8.2 Function calls <\/td>\n<\/tr>\n
803<\/td>\nA.8.3 Expressions <\/td>\n<\/tr>\n
804<\/td>\nA.8.4 Primaries
A.8.5 Expression left-side values <\/td>\n<\/tr>\n
805<\/td>\nA.8.6 Operators
A.8.7 Numbers <\/td>\n<\/tr>\n
806<\/td>\nA.8.8 Strings
A.9 General
A.9.1 Attributes
A.9.2 Comments
A.9.3 Identifiers <\/td>\n<\/tr>\n
807<\/td>\nA.9.4 Identifier branches <\/td>\n<\/tr>\n
808<\/td>\nA.9.5 White space <\/td>\n<\/tr>\n
809<\/td>\nAnnex B
List of keywords <\/td>\n<\/tr>\n
811<\/td>\nAnnex C
System tasks and functions
C.1 $countdrivers <\/td>\n<\/tr>\n
812<\/td>\nC.2 $getpattern <\/td>\n<\/tr>\n
813<\/td>\nC.3 $input
C.4 $key and $nokey <\/td>\n<\/tr>\n
814<\/td>\nC.5 $list
C.6 $log and $nolog
C.7 $reset, $reset_count, and $reset_value <\/td>\n<\/tr>\n
815<\/td>\nC.8 $save, $restart, and $incsave <\/td>\n<\/tr>\n
816<\/td>\nC.9 $scale
C.10 $scope
C.11 $showscopes <\/td>\n<\/tr>\n
817<\/td>\nC.12 $showvars
C.13 $sreadmemb and $sreadmemh <\/td>\n<\/tr>\n
818<\/td>\nAnnex D
Compiler directives
D.1 `default_decay_time
D.2 `default_trireg_strength <\/td>\n<\/tr>\n
819<\/td>\nD.3 `delay_mode_distributed
D.4 `delay_mode_path
D.5 `delay_mode_unit
D.6 `delay_mode_zero <\/td>\n<\/tr>\n
820<\/td>\nAnnex E
acc_user.h <\/td>\n<\/tr>\n
829<\/td>\nAnnex F
veriuser.h <\/td>\n<\/tr>\n
837<\/td>\nAnnex G
vpi_user.h <\/td>\n<\/tr>\n
851<\/td>\nAnnex H
Bibliography <\/td>\n<\/tr>\n
852<\/td>\nIndex
Symbols <\/td>\n<\/tr>\n
855<\/td>\nNumerics
A <\/td>\n<\/tr>\n
859<\/td>\nB
C <\/td>\n<\/tr>\n
861<\/td>\nD
E <\/td>\n<\/tr>\n
862<\/td>\nF <\/td>\n<\/tr>\n
863<\/td>\nG
H <\/td>\n<\/tr>\n
864<\/td>\nI
K
L <\/td>\n<\/tr>\n
865<\/td>\nM <\/td>\n<\/tr>\n
866<\/td>\nN <\/td>\n<\/tr>\n
867<\/td>\nO <\/td>\n<\/tr>\n
868<\/td>\nP <\/td>\n<\/tr>\n
869<\/td>\nQ <\/td>\n<\/tr>\n
870<\/td>\nR <\/td>\n<\/tr>\n
871<\/td>\nS <\/td>\n<\/tr>\n
873<\/td>\nT <\/td>\n<\/tr>\n
876<\/td>\nU
V <\/td>\n<\/tr>\n
878<\/td>\nW <\/td>\n<\/tr>\n
879<\/td>\nX
Z <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard Verilog Hardware Description Language<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n2001<\/td>\n879<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":80072,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-80071","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/80071","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/80072"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=80071"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=80071"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=80071"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}