IEC 63011-2:2018
$22.75
Circuits intégrés – Circuits intégrés tridimensionnels – Partie 2: Alignement de puces empilées à petits pas d’interconnexion
| Published By | Publication Date | Number of Pages |
| IEC | 2018-11-28 | 32 |
| Published Code | IEC |
|---|---|
| Published By | International Electrotechnical Commission |
| Publication Date | 2018-11-28 |
| Pages Count | 32 |
| Language | France |
| Edition | 1.0 |
| File Size | 1.6 MB |
| ICS Codes | 31.200 - Integrated circuits. Microelectronics |
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